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716 - Data processing: design and analysis of circuit or semiconductor mask

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Class / Patent application numberDescriptionNumber of patent applications / Date published
716004000 Testing or evaluating 764
716008000 Floorplanning 282
716012000 Routing (e.g., routing map, netlisting) 203
716002000 Optimization (e.g., redundancy, compaction) 136
716018000 Logical circuit synthesizer 57
716003000 Translation (e.g., conversion, equivalence) 37
716007000 Partitioning (e.g., function block, ordering constraint) 24
716017000 Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) 24
20090150834METHOD OF REUSING CONSTRAINTS IN PCB DESIGNS - A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file. Finally, the method includes the step of processing the first design constraints output file, the second design constraints output file, and the attribute change file to map constraints associated with changed attributes, thus defining a revised constraints output file for the second design. The revised second constraints output file comprises constraints for at least some signals with changed attributes.06-11-2009
20100083193DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING - A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.04-01-2010
20090044154OVER APPROXIMATION OF INTEGRATED CIRCUIT BASED CLOCK GATING LOGIC - A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.02-12-2009
20080282206Structure for Designing an Integrated Circuit Having Anti-counterfeiting Measures - A design structure for an anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.11-13-2008
20090307635METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.12-10-2009
20090094563Method and System for Enhanced Verification By Closely Coupling a Structural Satisfiability Solver and Rewriting Algorithms - A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satisfiability solver operations with respect to said initial design by a satisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.04-09-2009
20090235209Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.09-17-2009
20090235208LIGHTING APPARATUS - The lighting apparatus according to the present invention is a lighting apparatus which lights by emitting light through solid-state light-emitting devices using an AC power source, the lighting apparatus including an AC to DC conversion unit which converts AC from the power source into DC, and a power source device which includes a rectangular main single-side mounting board, on which a part of the AC to DC conversion unit is mounted, and a rectangular first single-side mounting sub-board, on which a remaining part of the AC to DC conversion unit is mounted, the power source device being shaped like a chopstick box laid out such that the long, rectangular mounting surface of the main single-side mounting board and the rectangular first single-side mounting sub-board face each other along a length-wise direction.09-17-2009
20100005429INTEGRATED SINGLE SPICE DECK SENSITIZATION FOR GATE LEVEL TOOLS - One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.01-07-2010
20100031205ANALYTICAL SYNTHESIS METHOD AND OTA-BASED CIRCUIT STRUCTURE - An analytical Synthesis Method (ASM) is clearly and effectively demonstrated in the realization of current/voltage-mode Operational Trans-conductance Amplifier and Capacitor (OTA-C) circuits, where a complicated nth-order transfer function is manipulated and decomposed by a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint circuitry. The circuits realized includes voltage-mode nth-order OTA-C universal filter structures, tunable voltage/current-mode OTA-C universal biquad filters, voltage-mode odd/even-nth-order OTA-C elliptic filter structures, voltage/current-mode odd-nth-order OTA-C elliptic high-pass filter structures, and OTA-C quadrature oscillators. Some realized OTA-C circuits can be simplified to be OTA-only (OTA-parasiic C) circuits which fit for the operation at high frequencies.02-04-2010
20090144669METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION - A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method.06-04-2009
20090064058METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS - Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.03-05-2009
20090089720METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY - A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.04-02-2009
20090089719Structure for a Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit - Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.04-02-2009
20080244471SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS - An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.10-02-2008
20080216024Method and Apparatus for Allocating Data Paths - A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.09-04-2008
20090064060APPARATUS AND METHOD OF EXTRACTING EQUIVALENT CIRCUIT OF T-TYPE TRANSMISSION CIRCUIT - A method of extracting an equivalent circuit of a T-type transmission circuit measures signals of the first and second terminals to obtain S parameters, converts the S parameters into Z parameters to generate a T-type circuit by using the Z parameters, obtains first to third lead line resistors and first to third lead line inductors in the T-type circuit based on the Z parameters corresponding to constants of the T-type circuit, subtracts the Z parameters corresponding to the T-type circuit from the Z parameters corresponding to all of the equivalent circuit to calculate the Z parameters of a π-type circuit, converts the Z parameters of the π-type circuit into the Y parameters, and calculates first to third coupling capacitances based on the Y parameters.03-05-2009
20080288897Method Of Enforcing A Contract For A CAD Tool - A method for enforcing a contract for a computer-aided-design (CAD) tool is provided. In this method, a first payment for the CAD tool is made in accordance with the contract. The first payment is associated with user access to the CAD tool. At this point, the CAD tool can be used, wherein the computer system running the CAD tool includes criteria for requesting at least one additional payment for the CAD tool. Each additional payment is associated with generating an output. The computer system is responsive to one or more trigger conditions corresponding to the criteria. A payment request is received when an output generated by the CAD tool satisfies a trigger condition. For example, one trigger condition adds a watermark to the output for identifying the output as having been produced by the CAD tool.11-20-2008
20080235635SYSTEM ON CHIP DEVELOPMENT WITH RECONFIGURABLE MULTI-PROJECT WAFER TECHNOLOGY - A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.09-25-2008
20080263480LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS - During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data. The template engine may generate one or more of the following shells: an RTL shell, a documentation shell, a timing analysis shell, a synthesis shell, a manufacturing test shell, and/or a floorplan shell.10-23-2008
20090193367Standard cell including measuring structure - Implementations are presented herein that relate to a standard cell including a measuring structure.07-30-2009
20090106707Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit - Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.04-23-2009
20090106708Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits - A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.04-23-2009
20090249259High-Speed Low-Leakage-Power Standard Cell Library - A high-speed, low leakage-power Standard Cell Library is provided. The high-speed, low-leakage-power Standard Cell Library provides the extra drive-strength of a taller X-Track library (e.g., 14-Track library) and low leakage-power comparable to that of a smaller, N-Track library (e.g., 10-Track library). The high-speed, low leakage-power Standard Cell Library includes a set of cells each having a device area designed to provide maximum drive strength for the cell. The high-speed, low leakage-power Standard Cell Library further includes a second set of cells having varying device areas that provide reduced leakage power characteristics comparable to cells in the smaller, N-Track library. The modified reduced leakage-power cells are formed by adding padding to the cell to achieve a desired leakage-power characteristic of the cell.10-01-2009
20080307371Manufacturing Aware Design and Design Aware Manufacturing - Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout.12-11-2008
20080209364METHOD FOR STORING MULTIPLE LEVELS OF DESIGN DATA IN A COMMON DATABASE - An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.08-28-2008
20090077505GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects.03-19-2009
20100162184High Speed Reduced Area Cell Library With Cells Having Integer Multiple Track Heights - A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that includes active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows.06-24-2010
20100199233Uniquely Marking Products And Product Design Data - Methods and apparatuses for marking the product of an unauthorized use of a process are provided. For example, various implementations of the invention may cause a product to be marked when it is produced by the unauthorized use of a process. With some implementations of the invention, a computer program product may contain operations, which if the computer program product is used without authorization, would cause an inconspicuous mark to be placed within the output of the computer program or computer program product.08-05-2010
20090319959Method and system for the modular design and layout of integrated circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.12-24-2009
20080276205COMPUTER PROGRAM PRODUCT FOR DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY - A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.11-06-2008
20090217215Apparatus for giving assistance in analyzing deficiency in RTL-input program and method of doing the same - An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical with logic description extracted from successive portions of input RTL description data, and having correspondence in signals identical with the same in the input RTL description data, an estimator which receives the partial RTL description data to execute a RTL-input program, and creates error-judgment data indicative of whether the RTL-input program contains deficiency, and an execution controller which controls a volume of logic description contained in partial RTL description data to be next created by the partial RTL creator, based on the error-judgment data, and outputs partial RTL description data causing the same deficiency as deficiency of the input RTL description data, and having a minimum volume of logic description.08-27-2009
20090217214UNIDIRECTIONAL RELABELING FOR SUBCIRCUIT RECOGNITION - A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. In this method, one initial unique label is assigned to each of the plurality of vertices, each of a plurality of connection-types, power connection, and ground connection. A zero label is assigned to each of an input/output ports and a same initial unique label is assigned to same types of circuit components. Then each net is relabeled using labels of neighboring vertices. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Then, each device in the plurality of vertices is relabeled using labels of neighboring vertices excluding a label of a vertex that is connected to the Gate of the each device. The new labels of each vertex are stored in a data store and these labels are used in the calculation of the new labels of the vertices in a next iteration of relabeling.08-27-2009
20090217213REUSE OF CIRCUIT LABELS FOR VERIFICATION OF CIRCUIT RECOGNITION - A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. The method includes recursively relabeling of each of the plurality of vertices until labels of all neighboring vertices of a selected vertex are zero. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Each successive iteration of the relabeling uses labels of each of the plurality of vertices after a previous iteration of the relabeling. Then, a recursive circuit tracing operation is performed starting from the selected vertex until each of the plurality of vertices in the smaller circuit is matched with one of the plurality of vertices in the larger circuit. The circuit tracing operation includes matching a label of each of the plurality of vertices neighboring the selected vertex in the smaller circuit with a label of each of the plurality of vertices in the larger circuit neighboring a vertex corresponding to the selected vertex, wherein labels at a same depth of relabeling iteration is matched.08-27-2009
20090282373Optimization of ROM Structure by Splitting - A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.11-12-2009
20080229259Design flow for shrinking circuits having non-shrinkable IP layout - A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.09-18-2008
20090125851Nonlinear Driver Model For Multi-Driver Systems - A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.05-14-2009
20090064059APPARATUS AND METHOD FOR ANALYZING CIRCUIT SPECIFICATION DESCRIPTION DESIGN - An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.03-05-2009
20100115474NON-CONTACT POWER TRANSMISSION APPARATUS AND METHOD FOR DESIGNING NON-CONTACT POWER TRANSMISSION APPARATUS - A non-contact power transmission apparatus having a resonance system is disclosed. The resonance system includes a primary coil to which an alternating-current voltage from an alternating-current source is applied, a primary-side resonance coil, a secondary-side resonance coil, and a secondary coil to which a load is connected. The impedance of the primary coil is set such that the output impedance of the alternating-current source and the input impedance of the resonance system are matched to each other.05-06-2010
20090300556Hierarchical Partitioning - Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance.12-03-2009
20100031204PROCESS-INDEPENDENT SCHEMA LIBRARY - Methods are provided for utilizing a process-independent schema library that contains all the devices and all the device parameters in each of various process-specific schema libraries that a user or a group of users is working with. A process-specific schematic based on a first process technology can be converted to a process-specific schematic based on a second process technology by being first converted to a process-independent schematic that is based on the process-independent schema library, which is then converted to the process-specific schematic based on the second process technology. Circuits can be also be stored as a process-independent schematic that is based on the process-independent schema library but designed using a user interface that displays process-specific devices and device parameters.02-04-2010
20100023896METHOD OF DESIGNING A MULTI-WINDING DEVICE - A method for designing a transformer using three secondary winding phase shift angles and a minimized core cross-sections. The method includes receiving an indication of an acceptable level of total harmonic distortion (THD) for the transformer, identifying a desired number of secondary windings per output phase of the transformer, simulating performance of various models for the transformer various potential phase shift angles, wherein each of the various models includes a set of phase shift angles for the secondary windings of the transformer. The method further includes identifying, based on the simulation, a transformer model that both has no more than three unique phase shift angles in the set and exhibits a primary side THD that is within the acceptable level, identifying an optimized core cross-sections, and reporting the identified transformer model having the three unique phase shift angle and the optimized core cross-sections.01-28-2010
20090172608Techniques for Selecting Spares to Implement a Design Change in an Integrated Circuit - A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.07-02-2009
20100095252CHANNEL LENGTH SCALING FOR FOOTPRINT COMPATIBLE DIGITAL LIBRARY CELL DESIGN - Effective GDS-based channel length scaling. A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The poly lines and contacts can be shifted by starting at the center and going out radially, or by beginning at the perimeter and moving radially inward. The method can be used with any library cell design which is entirely GDS based, including, for example, 32 nm library cell design.04-15-2010
20080229260STRUCTURE FOR AUTOMATED TRANSISTOR TUNING IN AN INTEGRATED CIRCUIT DESIGN - A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.09-18-2008
20080222576DESIGN SUPPORT APPARATUS, METHOD FOR SUPPORTING DESIGN, AND MEDIUM RECORDING DESIGN SUPPORT PROGRAM - A design support apparatus and method generating design data of a circuit and updating the design data, storing the design data and update history data representing an update content in association with an updated circuit component when the design data is updated. The disclosed apparatus and method include receiving an extraction criterion for extracting a particular piece of update history data from among a plurality of pieces of update history data, extracting the update history data from the history database in accordance with the extraction criterion, and restoring an original design data of the circuit before updating as represented by the extracted update history data.09-11-2008

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