Class / Patent application number | Description | Number of patent applications / Date published |
714801000 | Parity generator or checker circuit detail | 56 |
20080201630 | Storage controlling device and storage controlling method - According to an aspect of an embodiment, a method of storing user data (UD) with parity data (PD) for correcting the UD in a storage apparatus comprising disk units, each of the disk units storing data in data blocks(DBs), each of the DBs storing the UD or associated PD and position information(PI) indicative of the location of the DBs, comprising: obtaining the UD, dividing the UD into UD blocks (UDBs) which are adapted to be stored in the DBs, and determining which UDBs are to be stored into which DBs, respectively; determining PI of the DBs for storing the UDBs; generating PD for a group of UDBs and associated PI by parity operation using a weighting function to the UDBs and the PI; determining PI for the PD for said group by modifying a part of the PD; and storing the group of the UDBs, associated PI, and the PD. | 08-21-2008 |
20080209306 | ERROR MONITORING FOR SERIAL LINKS - Methods, apparatuses and systems for physical link error data capture and analysis. | 08-28-2008 |
20080222499 | CYCLIC COMPARISON METHOD FOR LOW-DENSITY PARITY-CHECK DECODER - The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log | 09-11-2008 |
20080235561 | Methodology and apparatus for soft-information detection and LDPC decoding on an ISI channel - A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system. | 09-25-2008 |
20080250304 | Construction and Use of Shortened Eg-Idpc Codes - Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes. | 10-09-2008 |
20080250305 | Method for generating non-binary structured low density parity check code - A method for generating a non-binary Low Density Parity Check (LDPC) code. The method includes generating non-binary identity matrixes so as to satisfy at least one condition, wherein the non-binary LDPC code is defined by a parity check matrix, and the parity check matrix includes a plurality of sub-matrixes, which are divided into zero matrixes and the non-binary identity matrixes. | 10-09-2008 |
20080250306 | CODING CIRCUIT FOR RECORDING DATA ON DVD DISK - A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a temporal storage memory which stores the digital data, a buffer manager which successively reads the digital data m bytes at a time from said temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the digital data m bytes at a time as the m bytes are supplied from said buffer manager so as to generate a PI sequence parity based on the digital data for one row extending in the main scan direction, and a PI parity unit which includes m operation units, each of which processes a corresponding one byte of the digital data as m bytes of the digital data are supplied from said buffer manager so as to generate a PO sequence parity based on the digital data for one column extending in the sub-scan direction. | 10-09-2008 |
20080256425 | Method of Encoding and Decoding Adaptive to Variable Code Rate Using Ldpc Code - A variable code rate adaptive encoding/decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The present invention includes the steps of generating a second parity check matrix corresponding to a code rate by reducing a portion of a plurality of submatrices configuring a first parity check matrix according to the code rate to be applied to encoding an input source data and encoding the input source data using the second parity check matrix. | 10-16-2008 |
20080256427 | SYSTEM, METHOD, AND SERVICE FOR PROVIDING A GENERIC RAID ENGINE AND OPTIMIZER - A generic RAID engine system accepts an access request, accepts a metadata input comprising a layout description and, optionally, a plurality of resource optimization objectives, accepts a dynamic input comprising a dynamic state of an I/O stack comprising the generic RAID engine and a fault configuration of a plurality of storage devices in the I/O stack, and accepts RAID code input comprising information about the RAID code used by the I/O stack. The metadata input, the dynamic input, and the RAID code input are utilized to transform the access request into individual device reads and individual device writes such that RAID code relationships for the storage devices are maintained at all times. An optional optimizer module selects strategies that meet the resource optimization objectives. | 10-16-2008 |
20080263431 | Apparatus and method for transmitting and receiving signal in a communication system - An apparatus and method for transmitting and receiving a signal in a communication system are provided. The signal transmission apparatus generates a parity check matrix for an LDPC code in accordance with a code rate to be used and generates a codeword vector by encoding an information vector using the parity check matrix. When the code rate is a first code rate, the signal transmission apparatus generates a first parity check matrix as the parity check matrix for the LDPC code. When the code rate is the second code rate, the signal transmission apparatus generates a second parity check matrix supporting a second code rate lower than the first code rate by adding columns of a degree of 1 and columns of a degree of 2 to the first parity check matrix and generates the second parity check matrix as the parity check matrix for the LDPC code. | 10-23-2008 |
20080270877 | Method of Encoding and Decoding Using Low Density Parity Check Code - A method of encoding and decoding using an LDPC code is disclosed, by which a memory for storing a parity check matrix necessary for the encoding or decoding using the LDPC code and calculation amount and complexity necessary for the encoding or decoding can be reduced. The present invention includes a step of encoding an input data using a parity check matrix H having a configuration of H=[H | 10-30-2008 |
20080276156 | LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 11-06-2008 |
20080282135 | PARITY GENERATOR, PRIORITY ENCODER, AND INFORMATION PROCESSOR - In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator having a plurality of first component circuits arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is “0s” or “1s”; and a second level generator generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits of said first level generator. | 11-13-2008 |
20080282136 | Parity generation circuit, counter circuit, and counting method - A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit. | 11-13-2008 |
20080294968 | Ultra High-Speed Optical Transmission Based on LDPC-Coded Modulation and Coherent Detection for All-Optical Network - An optical communication system includes a bit-interleaved coded modulation (BICM) coder; and a low-density parity-check (LDPC) coder coupled to the BICM coder to generate codes used as component codes and in combination with a coherent detector. | 11-27-2008 |
20080294969 | RATE-COMPATIBLE PROTOGRAPH LDPC CODE FAMILIES WITH LINEAR MINIMUM DISTANCE - Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero. LDPC codes built from the protographs created by these methods can simultaneously have low error floors and low iterative decoding thresholds, and families of such codes of different rates can be decoded efficiently using a common decoding architecture. | 11-27-2008 |
20080294970 | Method for implementing stochastic equality nodes - The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state. | 11-27-2008 |
20080320374 | METHOD AND APPARATUS FOR DECODING A LDPC CODE - In a decoder having a predetermined decoder structure for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes is provided. An associated method is provided. The method comprises the steps of: providing a memory for the decoding with the memory size proportional to the number of circularly shifted-identity matrices I (t); and providing a number M for both row update unit numbers and column-update unit numbers. Whereby an improved architecture having an improved logic and the memory is provided such that an improved throughput, power consumption, and memory area are achieved. | 12-25-2008 |
20090013239 | LDPC (Low Density Parity Check) decoder employing distributed check and/or variable node architecture - LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at least one portion of the variable/bit node processing functionality is actually integrated into the check node processing functionality (e.g., distributed variable/bit node embodiment). In even other embodiments, some check node processing functionality is moved and integrated into the variable/bit node processing functionality, and some variable/bit node processing functionality is also moved and integrated into the check node processing functionality (e.g., combined distributed embodiment). It is also noted that, when appropriately selected, the modification of the check engine and bit engine can also allow for reduction in routing layout between such a check engine and bit engine within a communication device. | 01-08-2009 |
20090031200 | High Rate, Long Block Length, Low Density Parity Check Encoder - There is provided a parity check encoder ( | 01-29-2009 |
20090070659 | LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD USING A SET OF RELATIVE VALUES FREE FROM A SHIFTING ACTION - In a decoder having an improved LLR (log-likelihood-ratio) update method is provided. The method comprising the steps of: providing a parity check matrix; and using merely a set of parameters on a row of the parity check matrix instead of data of the whole non-zero elements of the parity check matrix free from at least one shifting action after each row updating; thereby saving memory space and process time. | 03-12-2009 |
20090077453 | TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX - A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry. | 03-19-2009 |
20090083609 | EFFICIENT LOW COMPLEXITY HIGH THROUGHPUT LDPC DECODING METHOD AND OPTIMIZATION - A decoder and method for iteratively decoding of low-density parity check codes (LDPC) includes, in a code graph, performing check node decoding by determining messages from check nodes to variable nodes. In the code graph, variable node decoding is performed by determining messages from the variable nodes to the check nodes. The variable node decoding is independent from degree information regarding the variable nodes. Decoded results are output. | 03-26-2009 |
20090113276 | Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described. | 04-30-2009 |
20090204876 | Method for Encoding a Data Message K' for Transmission from Sending Station to Receiving Station as Well as Method for Decoding, Sending Station, Receiving Station and Software - Irregular LDPC codes have a construction which allows one to obtain a number of codes with different length from a single prototype code with a parity check matrix given by H=[Hz Hi], where Hz specifies the well-known zigzag pattern in the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz′ Π diag(Hi, . . . , Hi)], where Hz′ specifies a longer zigzag pattern depending on the number of matrices Hi used, and Π represents some permutation. This allows one to construct the decoder for a longer code by reusing hardware components developed for decoding the prototype code. | 08-13-2009 |
20090210774 | ERROR DETECTING/CORRECTING SCHEME FOR MEMORIES - A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation. | 08-20-2009 |
20090249173 | Storage system and data storage method - The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device. | 10-01-2009 |
20100023847 | Storage Subsystem and Method for Verifying Data Using the Same - A subject of the invention is to propose a storage subsystem assuring high reliability and not impairing processing performance. The invention is a storage subsystem which includes a storage device including a hard disk drive and a controller for controlling an access to the storage device in response to a predetermined access command transmitted from a host computer. The storage subsystem stores, in response to a write request transmitted from the host computer, data associated with the write request together with its parity in the storage device as well as verifies the validity of the data stored in the storage device independently of a response to the write request and, when there is an abnormality in the data, repairs the abnormal data. | 01-28-2010 |
20100058153 | CHAINED CHECKSUM ERROR CORRECTION MECHANISM TO IMPROVE TCP PERFORMANCE OVER NETWORK WITH WIRELESS LINKS - Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first CSUM; error checking the received data block in a second sequence using a second polynomial, using the first CSUM as a second predetermined initial error checking state, producing a second CSUM; comparing the second CSUM to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial. | 03-04-2010 |
20100115386 | Scalable Folded Decoder Architecture for Low Density Parity Check Codes - A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1. | 05-06-2010 |
20100122150 | CPU INSTRUCTION RAM PARITY ERROR PROCEDURE - A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor. | 05-13-2010 |
20100174972 | METHOD FOR GENERATING PARITY-CHECK MATRIX - A method for generating a parity check matrix to decode a plurality of underdetermined nodes, includes the steps of: determining a plurality of specific nodes according to a predetermined parity check matrix; determining a plurality of weightings corresponding to the plurality of specific nodes; and sorting the plurality of specific nodes according to the plurality of weightings to generate the parity check matrix to store in a storage device. | 07-08-2010 |
20100223538 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DECODING CODED DATA - A memory card including a word line control portion configured to perform control of applying intermediate voltages made up of a first intermediate voltage lower than a center voltage of four threshold voltage distributions and a second intermediate voltage higher than the center voltage to the memory cell, a logarithmic likelihood ratio table memory portion configured to store 9-level logarithmic likelihood ratios based on read voltages, and a decoder configured to perform decoding processing on the data read using the logarithmic likelihood ratio stored in the logarithmic likelihood ratio table memory portion. | 09-02-2010 |
20100281349 | Systems and Methods for Retransmission Return Channel Error Detection - A method implemented in a digital subscriber line (DSL) system is described for minimizing a misdetection probability at a far-end coded message receiver during transmission of a coded message. The method comprises jointly determining, at the far-end coded message receiver, a P matrix and a modulation scheme. The method further comprises encoding a message into a coded message with a systematic linear block code, the systematic linear block code having a generator matrix [I P], where I represents a linear block code component identity matrix and P represents the determined P matrix. The method also comprises modulating the encoded message to one or more tones forming a discrete multi-tone (DMT) symbol according to the determined modulation scheme. | 11-04-2010 |
20100306632 | ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL AND DENSELY PACKED DECIMAL CONVERSIONS - Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits. | 12-02-2010 |
20100306633 | PARITY DATA ENCODER FOR SERIAL COMMUNICATION - A prepended parity data encoder is loaded with sets of data and constant data, which are used for parity calculation. A shift circuit shifts each of the plural sets of data and the constant data, one bit at a time in parallel. When the constant data is output from the shift circuit, a parity generator dynamically generates prepended parity data based on the constant data and the plural sets of data. | 12-02-2010 |
20110029847 | PROCESSING OF DATA INTEGRITY FIELD - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data. | 02-03-2011 |
20110113312 | CHECK MATRIX GENERATING METHOD, CHECK MATRIX, DECODING APPARATUS, AND DECODING METHOD - A check matrix generating method of generating a check matrix (H) for decoding coded modulation data, which is encoded by a low-density parity check code and which is modulated by converting a-bit data (wherein a is a natural number) to b-bit data (wherein b is a natural number) wherein a is a modulation symbol unit, the method provided with: a check matrix generating process of generating the check matrix by determining each element such that the number of elements of 1 is less than or equal to one, out of a elements corresponding to data of the same modulation symbol in each of rows which constitute the check matrix. | 05-12-2011 |
20110154168 | EFFECTIVE HIGH-SPEED LDPC ENCODING METHOD AND APPARATUS USING THE SAME - Disclosed is an effective high-speed encoding method using a parity-check matrix proposed in an IEEE 802.1x standard for high-speed low-density parity-check encoding. In the prior art, encoding was performed by blocking and dividing the parity-check matrix of the LDPC code and through relevant matrix equations, or encoding was performed by an encoding apparatus that divides a matrix multiplication operation of a generated matrix acquired by using an arbitrary parity-check matrix of a quasi-cyclic (QC) LDPC code and information vectors into two sequential steps and implements each step as a cyclic shift-register. Unlike the prior art, the present invention provides an effective high-speed encoding method having low additional complexity by using a quasi-cyclic characteristic of a parity-check matrix as well as an encoding method through generation of a temporary parity bit, generation of a correction bit, and correction of a parity bit by using the parity-check matrix having a dual-diagonal parity structure proposed in the standard. | 06-23-2011 |
20110161788 | LOW DENSITY PARITY CHECK CODES DECODER AND METHOD THEREOF - It is an object of the present invention to provide a low density parity check codes decoder that can decode an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder according to the present invention is configured to enable decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well. | 06-30-2011 |
20110239096 | DATA MEMORY DEVICE AND METHOD OF PROGRAMMING TO THE SAME - A memory element array includes plural memory elements capable of storing M-value data (M is a natural number not smaller than 2). Among first to M-th data, the first data gives a largest physical impact on memory elements. | 09-29-2011 |
20110307769 | ERROR DETECTION IN A CONTENT ADDRESSABLE MEMORY (CAM) AND METHOD OF OPERATION - A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit. | 12-15-2011 |
20120137199 | Cloud Storage Data Access Method, Apparatus and System - This invention relates to field of cloud storage technology and especially relates to a cloud storage data access method, apparatus and system. The data storing step comprises: creating parity values of original data on a data transmitting end before the original data is transmitted to multiple cloud storage centers; transmitting and storing the original data and the parity values according to a preset redundant storing rule into the cloud storage data centers separately; the data retrieving step comprises: following the preset redundant storing rule to access at least one of the cloud storage data centers into which the original data is stored according to an access request; determining whether the original data is available in the accessed cloud storage data center, if not available, retrieving the parity value of the original data and the data used to create the parity value from at least one of the other cloud storage data centers according to the preset redundant storing rule; restoring the original data from its parity value and the data used to create the parity value. This invention also provides a cloud storage data access apparatus and system. This invention has enhanced the data availability and fault tolerance of cloud storage. | 05-31-2012 |
20120185757 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION/BROADCASTING SYSTEM - An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (N | 07-19-2012 |
20120204083 | TRANSMISSION DEVICE - A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code. | 08-09-2012 |
20120240014 | Error Tolerant Flip-Flops - One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error. | 09-20-2012 |
20130179758 | CIRCUITS, INTEGRATED CIRCUITS, AND METHODS FOR INTERLEAVED PARITY COMPUTATION - Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal. | 07-11-2013 |
20140331110 | CIRCUITS, INTEGRATED CIRCUITS, AND METHODS FOR INTERLEAVED PARITY COMPUTATION - Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal. | 11-06-2014 |
20140372837 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PROCESSING IN SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, wherein the first-combinational-circuit outputs a current state-value depending on the state-value output by the selector and the input signal. | 12-18-2014 |
20140372838 | Bad disk block self-detection method and apparatus, and computer storage medium - It is described a bad disk block self-detection method, including: each mounted chunk is partitioned into n sub-chunks, all sub-chunks having a same size, where n is an integer not less than 2; checking information is set at a fixed location of each sub-chunk, data is stored onto locations of each sub-chunk other than the fixed location, where the checking information is parity checking information for the data; and when the data is read or written, data verification is performed based on the checking information set at the fixed location of the read sub-chunk. It is also described a bad disk block self-detection apparatus and a computer storage medium. With the described above, the bad block on the disk can be detected rapidly, and it is able to instruct data migration and disk replacement. | 12-18-2014 |
20150309862 | CACHE CONTROL DEVICE HAVING FAULT-TOLERANT FUNCTION AND METHOD OF OPERATING THE SAME - The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation. | 10-29-2015 |
20150363267 | ERROR DETECTION IN STORED DATA VALUES - A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit. | 12-17-2015 |
20150363268 | ERROR DETECTION IN STORED DATA VALUES - An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value. | 12-17-2015 |
20160085614 | ADDRESS VERIFICATION ON A BUS - Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal. | 03-24-2016 |
20160162351 | PARITY CHECK CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A parity check circuit may include a first signal combination unit for generating first to N | 06-09-2016 |
20160191205 | DECODING DEVICE, INFORMATION TRANSMISSION SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - Provided is a decoding device including a reception unit that receives data of which the number of bits is converted and encoded such that a ratio between appearance frequency of a first code and appearance frequency of a second code is a predetermined range, and to which an error correcting code including redundant bits for calculating an error position of the data and a parity check bit of the data is appended, and a detection unit that detects that there are an odd number of bit errors in the data when a value of a syndrome corresponding to an error position is a first predetermined value and an error occurs in the decoding, or when the value of the syndrome is not the first value and a value of the parity check bit is a second predetermined value and an error occurs in the decoding on the data. | 06-30-2016 |