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Error/fault detection technique

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714807000 Check character 215
714800000 Parity bit 114
714819000 Comparison of data 63
714811000 Forbidden combination or improper condition 7
714806000 Constant-ratio code (m/n) 4
20130086457DETECTING CODEWORDS IN SOLID-STATE STORAGE DEVICES - A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.04-04-2013
20110138262METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING A LOW-DENSITY PARITY CHECK CODE - A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups; determining an order of the plurality of groups to be shortened, based on a ratio of a number of bits to be shortened to a number of bits to be punctured; determining a length of an information word to be obtained by shortening the plurality of groups; shortening the plurality of groups on a group basis in the determined order based on the determined length of the information word; and LDPC-encoding a shortened information word.06-09-2011
20100095192BERGER INVERT CODE ENCODING AND DECODING METHOD - A Berger invert code encoding and decoding method is disclosed. The method includes steps: Selecting logic value 0 or 1 to represent the stable and unstable states respectively. Calculating the stable bit count and the unstable-bit count of the codeword. Checking whether the unstable bit count is larger than the stable bit count or not. Setting the Invert Bit to the unstable state for indicating the inversion when the unstable bit count is larger than the stable bit count. Resetting the Invert Bit to the stable state for indicating the non-inversion when the unstable bit count is not larger than the stable bit count. Concatenating the Invert Bit to the codeword as a new codeword.04-15-2010
20090204877Block Modulus Coding (BMC) Systems and Methods for Block Coding with Non-Binary Modulus - Block modulus coding (BMC) systems implement block coding on non-binary modulus m symbols, where m is greater than 2. BMC systems can be used for, among other things, forward error correction (FEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data is represented by non-binary symbols that may be corrupted by burst errors. The block coding is preferably performed using a distributed arrangement of block encoders or decoders. A distributed block modulus encoder (DBME) encodes sequential source data symbols of modulus m with a plurality of sequential block encoders to produce interleaved parity codewords. The codewords utilize modulus m symbols where the medium can reliably resolve m symbol states. The interleaved parity codewords enable decoding of error-corrected source data symbols of modulus m with a distributed block modulus decoder (DBMD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols.08-13-2009
714809000 Code constraint monitored 3
20080235562REVERSE CONCATENATION FOR PRODUCT CODES - Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.09-25-2008
20100153830CARRY BUCKET-AWARE MULTIPLICATION - An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.06-17-2010
20110093768DATA LOSS DETECTION METHOD FOR HANDLING FUZZINESS IN SENSITIVE KEYWORDS - A method and apparatus for handling fuzziness in sensitive keywords from data loss prevention (DLP) policies. In one embodiment, the method includes identifying a keyword included in a DLP policy, generating multiple permutations of the keyword, and adding the multiple permutations to the DLP policy. The method further includes causing information content to be searched for the keyword permutations to detect a violation of the DLP policy in the information content.04-21-2011
Entries
DocumentTitleDate
20090193322INFORMATION PROCESSING APPARATUS INCLUDING TRANSFER DEVICE FOR TRANSFERRING DATA - According to an aspect of an embodiment, an apparatus has a first storage, a read write unit for reading and writing data from/into the first storage, a first error detector for detecting an error of data read out from the first storage, an address storage for storing an address of the first storage, a determining unit for determining whether an address of the first storage in which data to be written is matched with the error detected address, a second storage for storing data to be written into the first storage when the address of the first storage in which the data to be written is matched with the error detected address, a second error detector for detecting an error of data read out from the second storage and a selector for outputting one of the data stored in the first storage or the second storage.07-30-2009
20100115384METHOD FOR PACKET-SWITCHING TRANSMISSION OF MEDIA DATA AND DEVICE FOR PROCESSING MEDIA DATA - The invention relates to a method for packet-switching transmission of media data and a device for processing media data. Media data may be video, audio or text data, or other data. Transmission of the data is usually effected according to a streaming method. The data is therein transmitted in packets and re-assembled in the receiving device. For Internet applications, the real-time transport protocol is very widely used in the transmission of data streams. However, this data transmission protocol does not enable a secure transmission which is based on a repetition of the defectively transmitted data. Sequence counters are used according to this protocol so that left-out data packets can be detected in the receiving device. According to the invention, it is provided that error information data is inserted in the destination media data record which is generated from the received data in the receiving device when, according to the transmission protocol, transmission errors are detected in the analysis of the data packets received. The transmission errors are then documented in the destination data record. The stored error information can be analyzed upon reproduction of the destination data record so that it can be evaluated, in particular, whether the recorded original data is so seriously defective that a new recording is inevitable. In particular, this is advantageous in video production where it is necessary to quickly evaluate whether a recorded film or video scene is of acceptable quality (if necessary, taking potential retouching into account) or whether it must be repeated and recorded again.05-06-2010
20100042909DOCUMENT ERROR INFERENCE PROCESSING PROGRAM, PROCESSING DEVICE AND PROCESSING METHOD - A device includes a taxonomy schema; a display link base; a calculation link base; an XBRL document memory unit which stores an instance; an error inference unit which compares a calculated value of an input value of the instance corresponding to an item element of the calculation value in accordance with the calculation link base with the input value of the instance corresponding to the calculated value based on the display link base, detects a discrepancy between the calculation value and the input value, specifies a calculation tree structure of the calculation link base including the item element in which the discrepancy is detected and a display tree structure of the display link base including the item element in which the discrepancy is detected, and infers that a state of too many or too few item elements is regarded as a discrepancy error in the case that such an item element is set only in either one of the trees and that the item element has an input that is consistent with an absolute value of the difference between the input value and the calculated value; and an inference result display processing unit which outputs the error inferred result.02-18-2010
20100107042WIRELESS COMMUNICATION APPARATUS, WIRELESS COMMUNICATION METHOD, AND COMPUTER PROGRAM - A wireless communication apparatus that operates in a network environment with mixed different packet formats, includes: a first format detecting unit detecting a format by executing signal processing on a preamble of a received packet before decoding; an estimating unit using the preamble to carry out multiple types of estimations; a decoding unit decoding the received packet in accordance with the detected format based on the estimations; a second format detecting unit detecting the format of the received packet based on decoded control information in the preamble of the received packet; an error detection determination unit, when the format detected by the first format detecting unit differs from the format detected by the second format detecting unit, determining that the format detected by the first format detecting unit is error detection; and a control unit controlling operations of the estimating unit and the decoding unit based on a determined result.04-29-2010
20100095191METHOD AND APPARATUS FOR DEINTERLEAVING IN A DIGITAL COMMUNICATION SYSTEM - A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds to at least one of the plurality of data units deinterleaved by the data deinterleaver; and apply the deinterleaved SQI units to the corresponding deinterleaved data units.04-15-2010
20130047057DETECTING INTENTIONAL CORRUPTION OF DATA IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.02-21-2013
20090044086Error correction in a set associative storage device - A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.02-12-2009
20090044085DEFECT MANAGEMENT METHOD FOR STORAGE MEDIUM AND SYSTEM THEREOF - A defect management method for a storage medium is provided. An initial check is performed on the storage medium, and then diving the storage medium into blocks, which at least include a using data area with endurance blocks. Each endurance block is given an initial endurance value. Then, an endurance table is established in the storage medium for recording endurance blocks and the initial endurance values. According to the endurance table, data is written to the storage medium based on its importance. When the writing cycles reach a predetermined times, the endurance values are recalculated and the table is updated accordingly. Data is then moved according to the new endurance values.02-12-2009
20120192043LOOPBACK TESTING WITH PHASE ALIGNMENT OF A SAMPLING CLOCK AT A TEST RECEIVER APPARATUS - Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.07-26-2012
20090271689INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - An information processing device, comprising: a first encoder configured to encode data having an error detecting code in a first encoding format to generate first data; a second encoder configured to encode the first data in a second encoding format corresponding to decoding of the first encoding format to generate second data; and an error detector configured to perform error detection on the second data based on the error detecting code added to the data.10-29-2009
20090031198Method, an electrical system, a digital control module, and an actuator control module in a vehicle - A method, control module and system of a vehicle including at least a first and a second control computer each containing a number of local Digital Control Modules and at least one Actuator Control Module wherein the Actuator Control Module of each control computer is operatively connected to all local Digital Control Modules of the same control computer, wherein the Actuator Control Module of each control computer is further operatively connected to all Digital Control Modules of the electrical system in a manner that enables each Actuator Control Module of the system to receive internal data of each Digital Control Module of the electrical system.01-29-2009
20130067298AUTOMATICALLY ALLOCATING CLIENTS FOR SOFTWARE PROGRAM TESTING - Techniques are described herein that are capable of automatically allocating clients for testing a software program. For instance, a number of the clients that are to be allocated for the testing may be determined based on a workload that is to be imposed by the clients during execution of the testing. For example, the number of the clients may be a minimum number of the clients that is capable of accommodating the workload. In accordance with this example, the minimum number of the clients may be allocated in a targeted environment so that the test may be performed on those clients. Additional clients may be allocated along with the minimum number of the clients in the targeted environment to accommodate excess workload.03-14-2013
20130067299DIAGNOSTIC TOOL FOR METROLOGY ERRORS CAUSED BY COMMUNICATION ACTIVITIES - Described herein are embodiments of methods and systems for detecting communications of a first meter board by a second meter board and correlating the time and duration of the communications with metrology data gathered during that time. In accordance with one aspect, a method is provided for diagnosing metrology errors caused by communication activities of a meter board. In one embodiment, the method includes: receiving a signal, wherein the signal indicates a presence of communication activities between a first processor of a meter and another device over a network; recording a time of receipt and duration of the communication activities between the first processor of the meter and another device over the network; and correlating the time and duration of the communication activities between the first processor of the meter and another device over the network with metrology data of the meter measured at the same time and duration.03-14-2013
20090006931Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint - Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.01-01-2009
20130166993ERROR DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other.06-27-2013
20120290904ERROR GENERATION DIRECTION CIRCUIT, STORAGE UNIT, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF ERROR GENERATION DIRECTION CIRCUIT - Determining whether or not an instruction execution part that executes an instruction from a processor meets an error generation condition; when an error setting direction that directs to set an error has been input, outputting a determination direction to determine whether or not the instruction execution part meets the error generation condition, and, in a case where the error generation condition is not met when the error setting direction has been input, again outputting, after a predetermined time has elapsed from the output of the determination direction, the determination direction; and outputting an error generation direction to the instruction execution part in a case where the instruction execution part meets the error generation condition by the determination are carried out.11-15-2012
20120290903SEMICONDUCTOR APPARATUS AND INFORMATION PROCESSING APPARATUS - A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.11-15-2012
20110191658Method and Apparatus for Storing Data - When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data.08-04-2011
20100031131METHOD FOR PROCESSING NOISE INTERFERENCE IN DATA ACCESSING DEVICE WITH SERIAL ADVANCED TECHNOLOGY ATTACHMENT INTERFACE - A method for processing noise interference in a serial advanced technology attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.02-04-2010
20090282321Optional Memory Error Checking - A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the controller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.11-12-2009
20090177952TRANSCODER AND RECEIVER - An error extracting unit 07-09-2009
20120110423COMMAND CONTROL CIRCUIT, INTEGRATED CIRCUIT HAVING THE SAME, AND COMMAND CONTROL METHOD - A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.05-03-2012
20110173519WIRELESS COMMUNICATION APPARATUS AND ERROR DETECTION RESULT FEEDBACK METHOD - A wireless communication apparatus and an error detection result feedback method wherein unnecessary retransmissions are avoided to improve the system throughput. At a base station (07-14-2011
20100100798ERROR DETECTION - A method of error detection for a data packet, the method comprising the steps of: i) identifying a set of non-compliances (N), the non-compliances being illegal bit sequences according to a coding standard; ii) identifying a first subset (N+) of non-compliances that are to be treated as errors; iii) identifying a second subset (N.) of non-acceptable near-compliances; iv) decoding the data packet according to the coding standard; and v) adaptively deciding based on the first and second subsets whether to treat a detected non-compliance within the decoded data packet as an error or as an acceptable near-compliance.04-22-2010
20090276689Using short burst error detector in a queue-based system - A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.11-05-2009
20090276688DATA CONVERTER, INFORMATION RECORDER, AND ERROR DETECTOR - A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.11-05-2009
20080244366ADAPTABLE CHANNEL COMPENSATION FOR RELIABLE COMMUNICATION OVER FADING COMMUNICATION LINKS - A method for reducing fading channel signal data loss for serial data rates rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.10-02-2008
20090265602LIQUID CONTAINER - When a semiconductor storage device 10-22-2009
20090265601MITIGATION OF TRANSMISSION ERRORS OF QUANTIZED CHANNEL STATE INFORMATION FEEDBACK IN MULTI ANTENNA SYSTEMS - Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.10-22-2009
20090172506SEMICONDUCTOR DEVICE AND SIGNAL PROCESSING METHOD - A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.07-02-2009
20090177951PRIORI DECODING SCHEME BASED ON MAP MESSAGES - A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit values may be removed from the possible decoding paths to consider, and decoding the encoded data bits by selecting a decoding path from remaining decoding paths of the possible decoding paths that were not removed. A-priori bit values may be extracted from various messages, such as DL-MAP, UL-MAP, RNG-REQ, and BW-REQ messages.07-09-2009
20090024908Method for error registration and corresponding register - A method for error registration and a register which is assigned to a dual-computer system, information in the form of bits being stored in the register, the dual-computer system including an error-detection mechanism, and the bits in the register as error bits representing at least one error signal of the error-detection mechanism.01-22-2009
20110225477SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.09-15-2011
20090199076ACKNOWLEDGEMENT MESSAGE MODIFICATION IN COMMUNICATION NETWORKS - A station for a communications network. In one embodiment, the station includes a decoder, a check processor, and a transmitter. The decoder is adapted to decode a received encoded data unit. The check processor is adapted to determine whether the encoded data unit has been correctly received. The transmitter is adapted to initiate, prior to the check processor completing the determination whether the encoded data unit has been correctly received, the transmission of an acknowledgment message comprising a frame having a plurality of different fields of data. The transmitter is adapted to modify the transmission of the acknowledgment message if the check processor determines that the data unit has not been correctly received.08-06-2009
20110145684TRANSPARENT ENVELOPE FOR XML MESSAGES - Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination.06-16-2011
20120079357Systems and Methods For Measuring the Effectiveness of a Workload Predictor on a Mobile Device - Systems and methods for measuring the effectiveness of a workload predictor operative on a mobile device are disclosed. A load manager includes a workload predictor, a sensor, an error generator and a controller. The workload predictor generates an estimate of the workload on a processor core operative on the mobile device. The sensor generates a measure of the actual workload on the processor core. The error generator receives the estimate of the workload and the measure of the actual workload on the processor core and generates an error signal. The controller receives the error signal and determines the effectiveness of the workload predictor as a function of the error signal over time.03-29-2012
20110231742Error detection method - An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).09-22-2011
20090094506MILLIMETER-WAVE COMMUNICATIONS FOR PERIPHERAL DEVICES - A wireless device couples an electronic device employing a wired-link protocol to, for example, a wireless personal area network (WPAN). The wireless device comprises a wired interface configured for coupling to the electronic device, a wired transceiver coupled to the wired interface, the at least one wired transceiver configured for functioning as a terminus of a wired link coupled to the electronic device, and a wireless transmitter or transceiver coupled to the wired transceiver and configured for functioning as a terminus of a wireless link in the WPAN. The wireless device may be configured for coupling a plurality of dissimilar wired devices together via a wireless link.04-09-2009
20100180181APPARATUS AND METHOD FOR WRITING DATA TO BE STORED TO A PREDETERMINED MEMORY AREA - Method and apparatus for writing data to be stored to a predetermined memory area, the method comprising: reading stored data from the predetermined memory area, the stored data comprising a stored data block and an associated stored error detection value, manipulating, after reading the stored data, at least one of the stored data block and the associated stored error detection value in the predetermined memory area, and writing, after manipulating, the data to be stored to the predetermined memory area.07-15-2010
20110225478COMMUNICATION APPARATUS - A communicating unit used in an X-ray image pickup apparatus in this invention has an error detecting function to detect communication errors, and an FIFO for temporarily storing data received from a control and image processing apparatus, which is an external apparatus, by a receiving function of a communication control unit. Only when no error is detected within a predetermined period before and after receipt of data, by the receiving function of the communication control unit, from the control and image processing apparatus, a transmitting function of the communication control unit performs controls to transmit and write the data received and temporarily stored in the FIFO to an external portion. Thus, when a cable is plugged or unplugged or the control and image processing apparatus which is an external apparatus is rebooted, the error detecting function detects this as a communication error. In such cases also, an inadvertent writing of the data can be prevented. Therefore, a writing operation can be carried out also when there is no communication error. As a result, even if a communication error occurs, an inadvertent writing of data is prevented, and working efficiency is improved.09-15-2011
20090249172METHODS AND APPARATUS FOR IMPROVED DECODING OF BURSTS THAT INCLUDE MULTIPLE CONCATENATED PROTOCOL DATA UNITS - A corrupted protocol data unit (PDU) within a received burst of data may be identified. The received burst of data may include multiple concatenated PDUs. The received burst of data may continue to be processed despite the identification of the corrupted PDU. A next PDU in the received burst of data may be identified after the corrupted PDU is identified.10-01-2009
20090204875Method, System And Computer Program Product For Diagnosing Communications - A method for diagnosing communications includes sending a message from a sending node to a receiving node. The sending node detects an error in the receiving node receiving the message. A force log request is sent from the sending node to the receiving node, the force log request including a request for the receiving node to log information. A force log response is received from the receiving node at the sending node, the force log response including the logged information. The sending node diagnoses the communications error in response to the force log response.08-13-2009
20110231743CONTROL CIRCUIT, INFORMATION PROCESSING APPARATUS, AND METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS - A control circuit of a chip 09-22-2011
20090259923Method for fail-safe transmission, safety switching device and control unit - A method for fail-safe transmission of information between a transmitter and a receiver is disclosed. At least two telegrams relating to the information are transmitted as a first telegram via a first channel and a second telegram via a second channel from the transmitter to the receiver. To identify an error affecting the information during transmission, a first identifier is generated from a first subset of the first telegram being used at the receiver to identify the information contained in the first telegram. This method is used for communication from a safety switching device to a control unit.10-15-2009
20100037124WIRELESS COMMUNICATION APPARATUS, WIRELESS LAN SYSTEM, INTERFERENCE DETECTING METHOD, AND INTERFERENCE AVOIDANCE METHOD - A wireless communication apparatus, a wireless LAN system, an interference detecting method, and an interference avoidance method which detect the occurrence of a communication error caused by the occurrence of interference. A wireless communication apparatus (02-11-2010
20090259922CHANNEL DECODING-BASED ERROR DETECTION - Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets.10-15-2009
20100192048TRANSMITTING APPARATUS AND COMMUNICATION SYSTEM - A transmitting apparatus included in a communication system that performs message communication using an error detection code with a receiving apparatus, the transmitting apparatus includes a transmission interval determining means that, based on a parameter related to a transmission error non-detection probability of a message per time, a data length of the message, and a code length of the error detection code used for the message, determines a transmission interval for transmitting the message, so that the transmission error non-detection probability of the message satisfies a condition related to a transmission error non-detection probability included in the parameter, wherein the message is transmitted to the receiving apparatus, based on the transmission interval determined by the transmission interval determining means.07-29-2010
20090077452METHOD OF GENERATING ERROR DETECTION CODES - A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.03-19-2009
20100153827Multicast With UDP Using Packet Identifier in MPEG Payload - Content information is multicast via a data network to a plurality of receivers, using data packets in a transport stream. The content information is encapsulated according to a container format standard that allows an optional field in a packet header. Each data packet forms a payload of a datagram in a connectionless communication protocol. The optional field in each data packet is used to carry an identifier for identifying the data packet in a pre-determined sequence of the data packets. The use of the optional field enables packet loss detection at the receiver.06-17-2010
20100205514METHOD AND DEVICE FOR IDENTIFYING VIDEO DATA LOSSES - To identify data losses in a video sequence transmitted between a server and at least one client over a communication network, the sequence comprising a plurality of video data containers coded using scalable video coding employing a predetermined number of hierarchical levels, the video data containers being transmitted over the network via a series of data transport packets: a process (08-12-2010
20100251081APPARATUS AND METHOD FOR ARQ FEEDBACK POLLING IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for Automatic Repeat reQuest (ARQ) feedback polling in a wireless communication system are provided. The method for ARQ feedback polling includes transmitting at least one ARQ block to a receive end, polling ARQ feedback to the receive end using an extended header, determining if ARQ feedback information is received from the receive end within a lifetime of ARQ feedback, determining success or failure of transmission of the at least one ARQ block through the ARQ feedback information if it is determined that the ARQ feedback information is received within the lifetime of ARQ feedback, and polling ARQ feedback again to the receive end if it is determined that the ARQ feedback information is not received within the lifetime of ARQ feedback.09-30-2010
20130219252METHOD AND SYSTEM FOR PREVENTING HOLDING-OFF OF A PROTECTION SWITCHING FOR A PLURALITY OF ALARMS - The various embodiments herein provide a method and system for providing protection switching at a client layer on squelching of clients by a server layer protection controller in a nested protection system. The method comprises of marking a plurality of alarms of a pre-defined pattern and disabling a hold-off period for the plurality of marked alarms on receiving a squelch operation indication. The system comprises of one or more hold-off timers pre-configured with a hold off period and an alarm filter and hold-off processor (AFHP) for disabling the hold-off timer to invalidate the hold-off period for the plurality of marked alarms, wherein the plurality of marked alarms is an AIS generated due to squelching.08-22-2013
20110113311APPARATUS AND METHOD FOR SYNCHRONIZATION WITHIN SYSTEMS HAVING MODULES PROCESSING A CLOCK SIGNAL AT DIFFERENT RATES - In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules.05-12-2011
20100064202DECODING APPARATUS FOR HIGH-DENSITY RECORDING MEDIUM - A decoding apparatus for a high-density recording medium includes a demodulator, a long-distance code (LDC) processing module, a burst indicator subcode (BIS) processing module, an erasure code generator, and a decoder. The demodulator demodulates data from a high-density recording medium to obtain a demodulated data and a demodulation error flag. The LDC processing module and the BIS processing module deinterleave the demodulated data to respectively obtain an LDC data and a BIS data. The erasure code generator sets an erasure flag corresponding to the LDC data according to the demodulation error flag and the BIS error flag. The decoder decodes the LDC data according to the erasure flag. Further, the decoder decodes the BIS data to obtain the BIS error flag.03-11-2010
20100017691AUDIO CODEC AND BUILT-IN SELF TEST METHOD FOR THE SAME - An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components.01-21-2010
20110131476RECORDING APPARATUS AND RECORDING METHOD - A recording apparatus includes a first operation unit that calculates an EDC intermediate value from first data in a first region at least including data to be read after an EDC when reading data in a second sequence in a first sector from a data buffer that stores a block, a data memory that stores at least part of the first data used for operation by the first operation unit, a second operation unit that reads data excluding the first data from the block as second data from the data buffer and calculates the EDC based on the second data and the EDC intermediate value, and an integration unit that integrates the first data, the second data and the EDC, wherein the integration unit receives the EDC and the second data from the second operation unit, receives the first data from the data memory, and integrates and outputs them.06-02-2011
20090019343Loss Compensation device, loss compensation method and loss compensation program - It is possible to save storage resources. A loss compensation device for compensating a loss in periodical signals when the loss occurs in an arbitrary section of the periodical signals which are divided into predetermined sections and received in time series, includes: a periodical signal storage which stores one or more sections of newly received periodical signals for a predetermined period of time; a loss detector which detects a loss of each section of the periodical signals; and an element periodical signal generator which generates a plurality of element periodical signals for interpolation having different waveforms, in accordance with the periodical signals stored in the periodical signal storage, at time of detection of the loss if the loss is detected by the loss detector. The plurality of element periodical signals generated by the element periodical signal generator are synthesized, and a result of the synthesizing is arranged at the section where the loss in the periodical signals has occurred.01-15-2009
20080270875Two-Phase Data-Transfer Protocol - A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.10-30-2008
20090106635APPARATUS AND METHOD FOR DECODING IN MOBILE COMMUNICATION SYSTEM - An apparatus and method for reducing power consumption of a receiver by performing a Hybrid Automatic Repeat reQuest (HARQ) according to a detected decoding error are provided. The apparatus includes a decoding reliability metric generator for setting a decoding result as a decoding reliability metric, which is a reference value for determining a code block having a decoding error, based on a decoding result, a decoding reliability metric buffer for storing the decoding reliability metric set by the decoding reliability metric generator and a code block controller for, when the decoding error occurs, identifying code blocks having the decoding error by checking the decoding reliability metric and for controlling to decode the identified code blocks.04-23-2009
20100306630SYSTEM FOR SENDING SIGNALS BETWEEN MODULES - A system for transmission of signals between modules wherein, for example, it is possible to transmit reliably, between modules, information relating to, for example, the actuation of safety devices. A transmission module for transmitting a pulse signal of a specific period, which indicates the existence of information, generates, in time division, pulse signals by a plurality of signal generating units that are provided in parallel, and then combines these pulse signals into a single time series pulse signal. Then an attempt is made to output this pulse signal towards a receiving-side module through a relay for controlling the output, and the signals appearing at a normally-open terminal and at a normally-closed terminal of the relay are monitored to determine whether or not there is a failure, where the generation of the pulse signal is stopped when a failure is detected.12-02-2010
20110246864DATA DEPENDENT NPML DETECTION AND SYSTEMS THEREOF - According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting each IIR filter to actual noise conditions: a variance hank storing a plurality of prediction error variance values; and a data-dependent prediction error variance computation unit which updates the plurality of prediction error variance values. The maximum-likelihood sequence detector includes a metric computation unit that employs the plurality of IIR filters in the filter bank and the plurality of prediction error variances in the variance bank to adaptively compute detector branch metrics. Other systems and methods are also described in other embodiments.10-06-2011
20110055670Programming Method and Memory Device Using the Same - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.03-03-2011
20100138728APPARATUS FOR SUPPORTING DYNAMIC CHANGE OF EVENT RULE UNDER SCA AND METHOD THEREOF - An apparatus according to the present invention is an apparatus for supporting dynamic change of event rules in an SDR terminal under an SCA. The apparatus for supporting dynamic change of event rules includes: an event rule DB storing the rules that replicate event signals from an event generator and transmits the replicated event signals to an event consumer; an event manager that updates an event rule table recorded in a domain by using the event rules stored in the event rule DB; and an event relay unit that replicates the event signals from the event generator based on the event rule table and transmits the replicated event signals to the corresponding event consumer.06-03-2010
20100269027USER LEVEL MESSAGE BROADCAST MECHANISM IN DISTRIBUTED COMPUTING ENVIRONMENT - A data processing system is programmed to provide a method for enabling user-level one-to-all message/messaging (OTAM) broadcast within a distributed parallel computing environment in which multiple threads of a single job execute on different processing nodes across a network. The method comprises: generating one or more messages for transmission to at least one other processing node accessible via a network, where the messages are generated by/for a first thread executing at the data processing system (first processing node) and the other processing node executes one or more second threads of a same parallel job as the first thread. An OTAM broadcast is transmitting via a host fabric interface (HFI) of the data processing system as a one-to-all broadcast on the network, whereby the messages are transmitted to a cluster of processing nodes across the network that execute threads of the same parallel job as the first thread.10-21-2010
20100070837Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such - Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set. The second detector is operable to perform a data detection on the derivative of the decoded data set and to provide a second detected data set that is written to the unified memory buffer.03-18-2010
20100064203METHOD FOR MANAGING STORAGE APPARATUS, STORAGE APPARATUS AND STORAGE SYSTEM - A method for managing a storage apparatus includes acquiring error information for each of physical addresses assigned to a logical address, and managing the error information for each of the physical addresses.03-11-2010
20090217143On-Demand Service Reconciliation, Audit, and Alert Apparatus and Method - An audit tool (AT) operates in cooperation with an audit tool manager (ATM), a policy file (PF) and a query file (QF) in order to provide a real time display of usage within an on-demand service system. The ATM identifies the data to be gathered. Using the ATM, the user identifies comparison points, maps the comparison points to audit controls, defines policies and develops SQL queries to report transactions and record quantities. The AT gathers data, displays the gathered data, and compares the data points, and alerts the user to a discrepancy. The AT displays the compared data points side by side so that real time visual verification can be made, and the AT also alerts the user to discrepancies.08-27-2009
20110179340DEVICE AND METHOD FOR THE FINE SYNCHRONISATION OF DIFFERENT VERSIONS OF A RECEIVED DATA STREAM - The Invention pertains to the field of broadcasting digital services to terminals for transmitting said services, and concerns the problem of the smooth transfer between two versions of a same stream upstream from a transmitter within transmission networks on a single modulation frequency. The invention relates to a device for the fine synchronization of different versions of a data stream received with a certain offset or various jitters. In order to do so, the device includes different paths for detecting errors (ETR) and synchronising the stream (SNF).07-21-2011
20100070836ADAPTIVE COMPRESSION OF COMPUTED TOMOGRAPHY PROJECTION DATA - A compression subsystem for a computed tomography system compresses projection data to for efficient data transfer and storage. The compression includes applying an attenuation profile to an array of projection data samples. The attenuation profile is a function of sample coordinates and determines attenuation values applied to the samples. The attenuated samples are encoded and packed for data transfer. Alternatively, difference operators are applied to the attenuated samples and the differences are encoded. The average number of bits per compressed sample is monitored and the attenuation profiles can be modified to achieve a desired number of bits per compressed sample. The compressed samples are decompressed prior to image reconstruction processing. Decompression includes decoding the compressed samples and applying a gain profile to the decoded samples to restore the original dynamic range. This abstract does not limit the scope of the invention as described in the claims.03-18-2010
20100064204Monitoring Complex Data Feeds Through Ensemble Testing - Managing and monitoring multiple complex data feeds is a major challenge for data mining tasks in large corporations and scientific endeavors alike. The invention describes an effective method for flagging abnormalities in data feeds using an ensemble of statistical tests that may be used on complex data feeds. The tests in the ensemble are chosen such that the speed and ability to deliver real time decisions are not compromised.03-11-2010
20110154165STORAGE APPARATUS AND DATA TRANSFER METHOD - A storage apparatus includes: a host control unit for sending/receiving data to/from a host server; a drive control unit for sending/receiving the data to/from a storage device; a cache memory for temporarily storing the data sent and received between the host control unit and the drive control unit; a switch for switching between a transfer source and a transfer destination when transferring the data by selecting the transfer source and the transfer destination from among the host control unit, the cache memory, and the drive control unit; and a controller for controlling the host control unit, the drive control unit, and the switch; wherein processing for generating an error check code for the data and error check processing using the error check code are executed by the switch or are distributed among and executed by the host control unit, the drive control unit, the switch, and the controller.06-23-2011
20110154166AUTHENTICATION MODULE, ELECTRIC DEVICE, AND INTERLEAVED SIGNAL RESTORING METHOD - In one embodiment, an authentication module includes: a memory module that a plurality of data elements of an input interleaved signal are written to and read from; and a memory access controller configured to write the data elements of the input interleaved signal to the memory module sequentially in accordance with address information in a specific writing order commonly set between different signal formats of interleaved signals, and read the data elements written to the memory module from the memory module sequentially in accordance with address information in a specific reading order commonly set between the different signal formats, and output the read data elements as a restore signal.06-23-2011
20110060973Systems and Methods for Stepped Data Retry in a Storage System - Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.03-10-2011
20110016373SYSTEM, METHOD, AND APPARATUS FOR DATA COMMUNICATION - A system, method, and apparatus for data communication including a transmitter and first processor for data transmission in at least two states of operation, a receiver, memory device, and second processor providing at least two states of operation for processing the data. In a ready state, received data is ready for processing upon reception. In an active state, received data is converted into a different format prior to processing. The transmitter transmits first data associated with the ready state, a first transition command associated with transitioning from the ready state to the active state, second data associated with the active state, and a second transition command associated with transitioning from the active state to the ready state. The second processor processes the first data in the ready state, transitions to the active state, processes the second data in the active state, and transitions to the ready state.01-20-2011
20100306629PROCESSING OF BIT ERRORS IN A DIGITAL AUDIO BIT FRAME - The invention relates to a method of processing bit errors in a bit frame emanating from a digital audio coder, comprising a step of receiving a current bit frame liable to comprise bit errors. According to the invention, the bit frame comprises sensitive bits to be protected which are catalogued in at least one category according to the type of parameter that they code and the method furthermore comprises the steps of receiving protection bits, of reading the sensitive bits received in the current bit frame, the number of sensitive bits being lower than the number of bits of the bit frame, of detecting bit errors as a function of said protection bits received and of said sensitive bits received and in the event of detecting at least one erroneous bit in said bit frame, of modifying the current bit frame before decoding, as a function of the category in which the erroneous bit is catalogued. The invention also pertains to a device implementing the method according to the invention as well as to a decoder and a coding/decoding system comprising such a device.12-02-2010
20110055669SYSTEMS AND METHODS FOR DETECTING MACHINE FAULTS IN NETWORK USING ACOUSTIC MONITORING - Embodiments relate systems and methods for detecting machine faults in a network using acoustic monitoring. In embodiments, one or more servers, clients, or other machines in a managed network can have a microphone or other acoustic sensor integrated into motherboard or other hardware. The sensor can sample acoustic signals from inside or near the machine, and can digitize that data. The resulting set of acoustic data can be transmitted to a management server or other destination for analysis of the operating sounds related to that machine. For instance, the acoustic data can be analyzed to detect indications of a failed or failing hard drive, for instance by detecting spindle whine or head movement noises, or a failed or failing power supply based on other sounds. The management server can respond to potential fault events for instance by issuing configuration commands, such as instructions to power down the malfunctioning component.03-03-2011
20100180182DATA MEMORY DEVICE AND CONTROLLER WITH INTERFACE ERROR DETECTION AND HANDLING LOGIC - The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.07-15-2010
20100115385DETECTING DATA-ACCESS-ELEMENT-SELECTION ERRORS DURING DATA ACCESS IN DATA-STORAGE ARRAYS - An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.05-06-2010
20100017690METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM - A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).01-21-2010
20110307768ERROR DETECTION DEVICE, COMMUNICATION ERROR DETECTION SYSTEM, COMMUNICATION ERROR DETECTION METHOD - An error detection device includes a control unit configured to identify two links that connects a relay communication device to two communication devices as a link pair, identify, from pluralities of inspection devices under the respective two links, a number of inspection devices corresponding to the number N of links where communication errors simultaneously occur (N is an integer of 1 or more) plus 1, determine (N+1) number of inspection flows between the (N+1) number of inspection device pairs, and generate inspection coverage information that includes the determined inspection flows. The error detection device includes a storage unit that stores the inspection coverage information, and a communication unit that sends the inspection coverage information to one device of the inspection device pairs.12-15-2011
20090172505MAGNETIC DATA PROCESSING DEVICE, MAGNETIC DATA PROCESSING METHOD, AND MAGNETIC DATA PROCESSING PROGRAM - In a magnetic data processing device, an input part sequentially receives magnetic data output from a magnetic sensor. A storage part stores a plurality of the magnetic data as a data set of statistical population. An index derivation part derives a distribution index of the data set of the statistical population. A reliability determination part determines whether or not reliability of the data set of the statistical population is acceptable based on the distribution index and a decision criterion. A decision criterion setting part increases strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is acceptable, and decreases the strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is unacceptable.07-02-2009
20120005562ENCODED STREAM DECODING DEVICE - In an encoded stream decoding device, a storage amount checking circuit confirms that a sufficient amount of stream has been stored in a buffer circuit. Thereafter, a control circuit starts repeatedly outputting a control signal to a decoding circuit to instruct the decoding circuit to perform a variable-length decoding process. If, by iterating the decoding process, the total amount of a consumed stream in the buffer circuit 01-05-2012
20120210197APPARATUS AND METHOD FOR DECODING IN COMMUNICATION SYSTEM - An apparatus and a method for decoding bits of a received signal in a communication system are provided. The method includes determining path metrics of respective states in a trellis corresponding to the received signal, selecting a start state in the trellis for a traceback in a last window of the trellis, repeating the traceback at least twice within the last window, and when the repeating of the traceback is completed, determining the decoded bits of the received signal using a survived path of a last traceback.08-16-2012
20110167324Logic circuit protected against transient disturbances - The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (07-07-2011
20110167325Back Channel Communication - Various embodiments are described for back channel communication. One embodiment is a method that comprises receiving data at customer premises equipment (CPE), determining at least one error in the received data, formatting the determined error for communication to a central office (CO), and sending the formatted error to the CO via a back channel, wherein the formatted error is sent between sync frames of a discrete multitone (DMT) superframe.07-07-2011
20120011422MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN - A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.01-12-2012
20120011421FAIL ANALYSIS SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE - According to one embodiment, a fail analysis system performs mesh division of a physical fail bit map and stores fail bit map image data of a part bit fail region in a first image data storage region while classifying the fail bit map image data in each contraction ratio, in each chip, and in each layer. The fail analysis system also stores the fail bit map image data in a second image data storage region while classifying the fail bit map image data in each kind of a fail mode, in each contraction ratio, in each chip, and in each layer. Further, based on an instruction of a display format and/or a display region from a user, the fail analysis system extracts the pieces of fail bit map image data from the first image data storage region or second image data storage region to combine the pieces of fail bit map image data, and displays the combined fail bit map image data on a display unit.01-12-2012
20120060076Adaptive Communication Systems and Methods - Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and impulse noise protection parameters are adjusted according to the monitored impulse noise without interrupting communication service.03-08-2012
20120159289DATA SIGNATURES TO DETERMINE SUCESSFUL COMPLETION OF MEMORY BACKUP - Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. If an error is detected, a data integrity signature may be corrupted. A completion signature may be written. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature and completion signature checked.06-21-2012
20080276154LIGHTING CONTROL PROTOCOL - A digital lighting control network protocol with forward and backward frames, each of the frames including an error check code. A no-acknowledgment (NAK) signal is sent from a receiving node to a transmitting node responsive to the error check code. An interface circuit of the receiving node may include an energy storage section to store at least some energy from the network while receiving digital signals, and an output section to transmit digital signals to the network using the stored energy. The interface circuit may also include a high voltage buffer circuit. The transmitting node may send forward frames to receiving nodes based on device type.11-06-2008
20120124455CODING APPARATUS, CODING METHOD, DECODING APPARATUS, DECODING METHOD, PROGRAM AND TRANSMISSION SYSTEM - Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.05-17-2012
20120124454Systems and Methods for ADC Sample Based Timing Recovery - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples.05-17-2012
20090132898IC CARD, INFORMATION PROCESSING DEVICE, COMMUNICATION TYPE IDENTIFICATION METHOD, AND PROGRAM - An IC card is provided that is capable of identifying a communication type of incoming data received by non-contact communication. The IC card includes: an error detection portion that, for each of a plurality of communication types, performs error detection of incoming data based on an encoding format defined by each of the communication types; and a type identification portion that identifies, among the plurality of communication types, a communication type in which error information is not detected by the error detection portion as a communication type of the incoming data.05-21-2009
20120317464RECEIVING APPARATUS AND METHOD THAT DETECT RECEPTION OF SERIAL DATA HAVING A PLURALITY OF BLOCKS - Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N12-13-2012
20120131425METHODS FOR LAYOUT ERROR DETECTION - A layout error detection method includes the following steps, reading a layout file, in which the layout file includes a plurality of elements and a plurality of coordinates, and each element is corresponding to one coordinate; reading a record table, in which the record table includes an identification column, a coordinate column, and a flag column; scanning the layout file to obtain an error detection result, in which the error detection result is corresponding to an identification data and a coordinate data; searching the identification column of the record table to judge whether the identification column has the same identifier according to the identification data, and when a judgment result is false, writing the identification data and the coordinate data of the error detection result, setting a flag value to logic 0, and marking the error detection result; and scanning the layout file repeatedly until all the elements are scanned.05-24-2012
20100275107Method and Arrangement for Improved Turbo Decoding - In a method for improved turbo decoding in a wireless communication system, jointly allocating (S10-28-2010
20120179954DEVICE AND METHOD FOR IMPROVED LOST FRAME CONCEALMENT - Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame.07-12-2012
20120226964DYNAMIC SYNCHRONIZATION OF DATA CAPTURE ON AN OPTICAL OR OTHER HIGH SPEED COMMUNICATIONS LINK - A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.09-06-2012
20110004815Method and apparatus for masking signal loss - A method and apparatus are capable of masking a signal loss condition. According to an exemplary embodiment, the method includes steps of receiving a signal, detecting a period of loss of the signal, and enabling a received portion of the signal to be reproduced continuously and causing a portion of the signal lost during the period to be skipped.01-06-2011
20110004814SEMICONDUCTOR MEMORY APPARATUS AND DATA WRITE METHOD OF THE SAME - A Semiconductor memory apparatus includes: a data latch driving unit configured to latch and drive data and to transfer the driven data via a first data bus, based on a detection start signal and a detection stop signal; a data masking latch driving unit configured to latch and drive a data masking signal and to transfer the driven data masking signal via a second data bus, based on the detection start signal and the detection stop signal; an error detection unit configured to perform an error detection operation on the data and the data masking signal to generate an error detection signal, based on the detection start signal and the detection stop signal; an error detection driving unit configured to drive the error detection signal and to transfer the driven error detection signal via a third data bus; a write control unit configured to generate a write control signal based on the data masking signal transferred via the second data bus and the error detection signal transferred via the third data bus; and a data write unit configured to write aligned data transferred via the first data bus into a core circuit, based on the write control signal.01-06-2011
20120278688SEMICONDUCTOR DEVICE, INFORMATION PROCESSING APPARATUS, AND METHOD OF DETECTING ERROR - Each of (n−1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n−1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.11-01-2012
20110320921FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS - Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.12-29-2011
20120151305FILTERING METHOD, SYSTEM AND EQUIPMENT - A filtering method, system, and equipment applied in digital communication technologies are disclosed in the embodiments of the present invention. The filtering method of the present embodiments includes: acquiring filtering coefficients of a part of all subcarriers according to data transmission errors; acquiring filtering coefficients of remaining subcarriers through an interpolation algorithm according to the filtering coefficients of the part of subcarriers; and finally, filtering the data corresponding to the multiple subcarriers according to the filtering coefficients of the part of subcarriers and the filtering coefficients of the remaining subcarriers. The part of subcarriers may be selected at a regular interval, or may be subcarriers which are located at a motion value away from the part of subcarriers selected in the previous update of the filtering coefficients. The method of the present embodiments reduces the amount of operation and hardware expenditure, and saves the cost.06-14-2012
20130024753DECODING DEVICE AND DECODING ORDER CONTROL METHOD - A decoding device that performs decoding of data transmitted from each of a plurality of users comprises an iterative decoding section that repeats decoding of the data until no error is detected in a result of decoding, an error detection section that performs error detection on the decoding result each time decoding is performed, and a decoding order control section that estimates with respect to each of the plurality of users a decoding completion time, which is a time period the time period required until no error is detected in the result of decoding of the data transmitted from the user, and that assigns priorities to the users in increasing order of the estimated decoding completion time. The iterative decoding section performs decoding of the data transmitted from the users for the users in descending order of the priorities.01-24-2013
20130024752MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION - Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.01-24-2013
20120254707METHOD OF DETECTING TRANSPORTATION NETWORK DATABASE ERRORS AND DEVICES THEREOF - A method of detecting errors in road characteristics in a transportation network database includes collecting sequential location measurements from probes traversing between two end points, fitting trace segments having a curved or linear shape between the sequential location measurements collected from the probes to form a probe trace, comparing a position of the probe traces with a position of a calculated path between the two end points, where the calculated path is formed from linked transportation network segments each of the linked transportation segments having a curved or linear shape, where the calculated path follows the road characteristics defined by the attributes associated with the linked transportation segments, and identifying a potential error in the attributes if a probe trace deviating in position from the calculated path is greater than a deviation threshold.10-04-2012
20130104010Arrangements for Increasing Detection Confidence - In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed.04-25-2013
20130132805ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.05-23-2013
20130205185Systems and Methods for Low Latency Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.08-08-2013
20130159818Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling - Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.06-20-2013
20130159819METHOD, APPARATUS AND DECODER FOR DECODING CYCLIC CODE - A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.06-20-2013
20110314359ERROR DETECTION CODE GENERATING CIRCUIT AND ENCODING CIRCUIT UTILIZING WHICH AND METHOD THEREOF - An encoding circuit comprising: a memory unit; an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit and an decoder. The EDC generating circuit is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The scrambler is used for generating a scrambled main data according to the main data, and for storing the scrambled main data to the memory unit. The header generator is used for generating a header according to header information. The EDC correcting circuit is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC. The encoder is used for encoding optical data according to the second EDC and the scrambled main data.12-22-2011
20120030547SYSTEM AND METHOD FOR SAVING BATTERY POWER IN A VITAL-SIGNS MONITOR - A vital-signs device in a patient monitoring system is disclosed. The patch includes a housing configured to be attached to the skin of a patient. The housing contain monitoring circuitry configured to acquire and store measurements of vital signs of the patient, a wireless transmitter configured to transmit signals to another device, a wireless receiver configured to receive signals from the other device; and a processor operably connected to the monitoring circuitry, transmitter, and receiver. Upon receipt of an upload signal from the other device, the processor is configured to send a message to the other device via the transmitter. The message packet structure includes a data payload of variable size, a header containing transmit and route information and data payload length, and a data integrity check value.02-02-2012
20120089892METHOD AND APPARATUS FOR DATA MANAGEMENT THROUGH TIMER COMPENSATION IN A WIRELESS COMMUNICATION SYSTEM - A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.04-12-2012

Patent applications in class Error/fault detection technique

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