# Syndrome computed

## Subclass of:

## 714 - Error detection/correction and fault detection/recovery

## 714699000 - PULSE OR DATA ERROR HANDLING

## 714746000 - Digital data error correction

## 714752000 - Forward correction by block code

## 714781000 - Code based on generator polynomial

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

714785000 | Syndrome computed | 63 |

20080222497 | Decoding method and decoding circuit - An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing signal having a code sequence having a decoding unit generating first decoded signal and second decoded signal based on the code sequence and an error correction unit performing error correction for the second signal in response to the first signal. | 09-11-2008 |

20100011278 | Soft Error Correction in Sleeping Processors - An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence. | 01-14-2010 |

20100115383 | MEMORY DEVICE WITH AN ECC SYSTEM - A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks. | 05-06-2010 |

20140344652 | METHOD FOR GENERATING A MAXIMIZED LINEAR CORRECTING CODE, METHOD AND DEVICE FOR DECODING SUCH A CODE - A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error. | 11-20-2014 |

20120117448 | Apparatus and Method for Correcting at least one Bit Error within a Coded Bit Sequence - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 05-10-2012 |

20130061117 | TIME-VARYING LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES - The present disclosure is directed to communication systems and more specifically to communication devices having encoder and/or decoder blocks employing Low Density Parity Check Convolutional Codes (LDPC CCs). According to exemplary embodiments, improved LDPC CC techniques are disclosed to construct the syndrome former of an LDPC-CC code in a systematic way based on desired Rate (b/c), Memory (m | 03-07-2013 |

20110296281 | APPARATUS AND METHOD OF PROCESSING CYCLIC CODES - An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively. | 12-01-2011 |

20110296282 | FRAME BOUNDARY DETECTION AND DECODING - Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection. | 12-01-2011 |

20100269025 | Method for error correction and error detection of binary data - For algebraic single symbol error correction and detection, a method is proposed which achieves correcting single symbol errors at unknown positions within codewords, identifiying cases where multiple symbols within a codeword are uncorrectably corrupted, and identifying cases where a single symbol within a codeword is uncorrectably corrupted. The method comprises the steps of calculating a syndrome of a received word, splitting the syndrome into two parts, checking 3 integer weight quantities calculated from the two syndrome parts, converting the syndrome into a vector of integer valued “orthogonal bit error weights” associated to the received bits, and toggling those bits of the received word, where the associated “orthogonal bit error weight” is in the upper half of its possible value range. | 10-21-2010 |

20090164874 | Collecting Failure Information On Error Correction Code (ECC) Protected Data - Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug. | 06-25-2009 |

20130305127 | FORWARD ERROR CORRECTION ENCODER - A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width. | 11-14-2013 |

20120036415 | Systems and Methods for Performing Forward Error Correction - In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit. | 02-09-2012 |

20100100797 | DUAL MODE ERROR CORRECTION CODE (ECC) APPARATUS FOR FLASH MEMORY AND METHOD THEREOF - A dual mode error correction code (ECC) apparatus for the flash memory and method thereof are described. The dual mode error correction code (ECC) apparatus includes a syndrome detection unit, a first ECC unit, a second ECC unit, a switch module, and an interface module. The syndrome detection unit detects the data content for computing the amount of errors in the data content to determine whether the amount of the errors exceeds a pre-determined threshold value. The first ECC unit corrects the errors in the data content based on a first coding mode. The second ECC unit corrects the errors in the data content based on a second coding mode. The switch module either switches to the first ECC unit for activating the first coding mode of the first ECC unit if the amount of the errors is fewer than a pre-determined threshold value or switches to the second ECC unit for activating the second coding mode of the second ECC unit if the amount of the errors is greater than the pre-determined threshold value. | 04-22-2010 |

20090287983 | Decoding method and error correction method of a cyclic code decoder - A decoding method of a cyclic code decoder includes the machine-implemented steps of: establishing a lookup table; receiving a codeword; computing a syndrome and a Hamming weight; if the Hamming weight is not equal to zero and not greater than an error correcting capability value, performing a first error correcting operation; if the Hamming weight is greater than the error correcting capability value, and if the syndrome has a matching syndrome pattern in the lookup table, performing a second error correcting operation; if a second Hamming weight corresponding to a syndrome difference is smaller than a check value, performing a third error correcting operation, otherwise performing a fourth error correcting operation; and if a counter value is greater than zero, performing a fifth error correcting operation before decoding a corrected codeword. | 11-19-2009 |

20120216098 | DATA STORAGE DEVICE AND METHOD FOR CHECKING AND CORRECTING ERRORS - According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected. | 08-23-2012 |

20100174970 | EFFICIENT IMPLEMENTATION OF A KEY-EQUATION SOLVER FOR BCH CODES - The present invention relates to a method for solving the key equation and finding the error locator polynomial coefficients of a received word comprising the steps of: (a) providing the syndrome elements of said received word; (b) initializing said coefficients of said error locator polynomial; (c) providing an auxiliary polynomial; (d) initializing said auxiliary polynomial coefficients; (e) processing said syndrome elements and said auxiliary polynomial coefficients for iteratively updating said coefficients of said error locator polynomial; and (f) outputting said updated coefficients of said error locator polynomial. | 07-08-2010 |

20100241933 | Parallel Forward Error Correction with Syndrome Recalculation - A system and method are provided for parallel processing data that is forward error correction (FEC) protected with multiple codewords. The method accepts an electrical waveform representing a digital wrapper frame of interleaved FEC codewords. Typically, the codeword encoding is solved using an algorithm such as linear block codes, cyclical block codes, Hamming, Reed-Solomon, or Bose-Chaudhuri-Hocquenghem (BCH). The method calculates a first set of syndromes for a first codeword. In parallel with the calculation of the first set of syndromes, a second set of syndromes is calculated for a second codeword with a data component shared with the first codeword. Using the first set of syndromes, an error magnitude and location (EML) of the first codeword is performed. Using the second set of syndromes, an EML of the second codeword is performed in parallel with the EML of the first codeword. | 09-23-2010 |

20100241934 | RADIO COMMUNICATION APPARATUS AND ERROR DETECTING ENCODING METHOD - A wireless communication device is provided to make it possible to detect errors with high accuracy while to suppress reduction in throughput in the case that an LDPC (Low-Density Parity-Check) code is used for an error correcting code. In the wireless communication device, a CRC (Cyclic Redundancy Check) coding unit ( | 09-23-2010 |

20090106633 | METHOD AND APPARATUS FOR CORRECTING AND DETECTING MULTIPLE SPOTTY-BYTE ERRORS WITHIN A BYTE OCCURRED IN A LIMITED NUMBER OF BYTES - An apparatus for correcting and detecting multiple spotty-byte errors within a byte occurred in a limited number of bytes and which has a function capable of controlling multiple spotty-byte errors within a byte occurred in the limited number of bytes, is provided. | 04-23-2009 |

20090037796 | ERROR CORRECTION DEVICE - An error correction device for reducing the amount of access to an external memory while preventing the capacity of an internal memory from increasing. An optical disc stores scramble data for each data block. A descramble circuit reads scramble data in the data blocks from the optical disc as read blocks and applies a predetermined scramble value to the scramble data of each read block to generate descramble data. A 1-shift calculator generates a first calculated value by shifting the scramble value by one byte using a generation polynomial. A second shift calculator generates a second calculated value by shifting the scramble value by a number of bytes corresponding to {(total bytes of the data block in the column direction)+1−(total bytes of each read block in the column direction)} using the generation polynomial. An EOR circuit generates descramble data by applying the first or second calculated value as the scramble value to the input scramble data. | 02-05-2009 |

20100199156 | Method And Circuit For Encoding An Error Correction Code - The invention provides a method for decoding an error correction code. First, an error syndrome of the error correction code is calculated. A plurality of coefficients of an error locator polynomial of the error correction code is then sequentially determined according to the error syndrome. When a new coefficient of the error locator polynomial is determined, it is also determined whether the new determined coefficient is equal to zero. When the new determined coefficient is equal to zero, a speculated error locator polynomial is built according to a plurality of low-order-term coefficients of the error locator polynomial, wherein the orders of the low-order-term coefficients are lower than that of the new determined coefficient. A Chien search is then performed to determine a plurality of roots of the speculated error locator polynomial. The error correction code is then corrected according to the roots of the speculated error locator polynomial. | 08-05-2010 |

20090217140 | MEMORY SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION - An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error. | 08-27-2009 |

20100058151 | IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING - Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed. | 03-04-2010 |

20080256423 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 10-16-2008 |

20100162087 | METHOD OF DETECTING AND CORRECTING A PRESCRIBED SET OF ERROR EVENTS BASED ON ERROR DETECTING CODE - A method of constructing an effective generator polynomial for error correction by which a unique set of syndromes for each error event is produced is provided. The method includes preparing a set of dominant error events from the intersymbol interference characteristics of media; and generating a codeword from the data using a non-primitive generator polynomial that produces a unique syndrome set which can completely specify each dominant error event. | 06-24-2010 |

20130346834 | APPARATUS AND METHOD FOR CORRECTING AT LEAST ONE BIT ERROR WITHIN A CODED BIT SEQUENCE - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 12-26-2013 |

20110197111 | Method and apparatus for error-correction in and processing of GFP-T superblocks - The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected. | 08-11-2011 |

20090106634 | ERROR DETECTING AND CORRECTING CIRCUIT USING CHIEN SEARCH, SEMICONDUCTOR MEMORY CONTROLLER INCLUDING ERROR DETECTING AND CORRECTING CIRCUIT, SEMICONDUCTOR MEMORY SYSTEM INCLUDING ERROR DETECTING AND CORRECTING CIRCUIT, AND ERROR DETECTING AND CORRECTING METHOD USING CHIEN SEARCH - An error detecting and correcting circuit is provided with a syndrome calculating circuit calculating a syndrome of an inputted data sequence including an error correcting code, a polynomial deriving circuit deriving an error location polynomial, a Chien searching circuit obtaining a location of error data of the data sequence, and an error correcting circuit correcting an error of the data, and every time the Chien searching circuit specifies the location of error data, the error correcting circuit immediately corrects the error of the data at the error location, and outputs the corrected data to an external circuit, thereby the error can be efficiently detected and corrected. | 04-23-2009 |

20130042166 | FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD - Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention. | 02-14-2013 |

20140068392 | MEMORY CONTROLLER, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a Chien search unit, wherein the Chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements. | 03-06-2014 |

20120072810 | ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT - An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. | 03-22-2012 |

20140047305 | MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data. | 02-13-2014 |

20090150754 | High Speed Syndrome-Based FEC Encoder and System Using Same - A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding. | 06-11-2009 |

20140372836 | Systems and Methods for Data Processing Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding. | 12-18-2014 |

20120317463 | MEMORY CONTROLLER - An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data. | 12-13-2012 |

20100205513 | SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA - Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified. | 08-12-2010 |

20140068391 | Memory with Segmented Error Correction Codes - A code word is received that was derived from a plurality of smaller code words that represent a data word of 2 | 03-06-2014 |

20120254705 | ERROR CORRECTION DECODER AND ERROR CORRECTION METHOD THEREOF - An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data, wherein the plurality of channel data is received via a plurality of channels, and wherein the plurality of processing elements are driven independently from the plurality of channels | 10-04-2012 |

20090077449 | METHODS AND APPARATUS FOR ENCODING AND DECODING CYCLIC CODES BY PROCESSING MULTIPLE SYMBOLS PER CYCLE - Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of a different cyclic code for each codeword. Further provided is a hybrid device which provides the configurability of two modes of operation, whereby in one mode, the hybrid device functions as the encoder as provided above and, in the other mode, the hybrid device functions as the syndrome computer as provided above, with the majority of the components of the hybrid device being shared between the encoding function and the syndrome computing function. | 03-19-2009 |

20110320919 | HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE - Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points. | 12-29-2011 |

20140075272 | DEVICE AND METHOD FOR TESTING A CIRCUIT TO BE TESTED - A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (T | 03-13-2014 |

20080256422 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 10-16-2008 |

20080215956 | COMPUTING AN ERROR DETECTION CODE SYNDROME BASED ON A CORRECTION PATTERN - The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation. | 09-04-2008 |

20110029846 | MULTI-SOURCE DATA ENCODING, TRANSMISSION AND DECODING USING SLEPIAN-WOLF CODES BASED ON CHANNEL CODE PARTITIONING - System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources. | 02-03-2011 |

20110264987 | Systems and Methods for Low Density Parity Check Data Encoding - Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value. | 10-27-2011 |

20080282132 | Error Correcting Code | 11-13-2008 |

20120005561 | REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR - An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2 | 01-05-2012 |

20140136931 | ERROR-CORRECTING DECODER - Provided is an error-correcting decoder including: a syndrome generation unit for calculating, as a syndrome, coefficients of a residual polynomial that are obtained by dividing received data by a generator polynomial; information bit error pattern generation unit for generating all error patterns of information bits; a check bit error pattern generation unit for calculating, for each of the error patterns of the information bits, an error pattern of check bits based on the syndrome value; and an error correction unit for correcting the error pattern generated for a combination of codes having a weight of the error patterns of the information bits and the check bits smaller than a threshold value. | 05-15-2014 |

20100125776 | Multi-syndrome error correction circuit - In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream. | 05-20-2010 |

20110246862 | HARD INPUT LOW DENSITY PARITY CHECK DECODER - A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated. The exemplary method terminates based on a predefined syndrome output. | 10-06-2011 |

20110276862 | ERROR DETECTION MODULE, AND ERROR CORRECTION DEVICE INCLUDING THE SAME - An error detection module includes a known-syndrome computing unit, an unknown-syndrome computing unit, and an error detection unit. The known-syndrome computing unit is operable to convert a received signal into a target signal, to obtain known syndromes based upon the target signal, and to generate an errata-locator polynomial based upon an erasure-locator polynomial and the known syndromes. The unknown-syndrome computing unit is operable to compute unknown syndromes based upon the errata-locator polynomial and the known syndromes. The error detection unit is operable to obtain a syndrome set that includes the known syndromes and the unknown syndromes, to obtain an error detection signal according to the syndrome set, and to provide an error correction module coupled thereto with the syndrome set and the error detection signal for enabling the error correction module to correct an error of the received signal. | 11-10-2011 |

20120284589 | MEMORY SYSTEM AND ERROR CORRECTION METHOD - Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data. | 11-08-2012 |

20140089768 | ERROR LOCATION SEARCH CIRCUIT, AND ERROR CHECK AND CORRECTION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2 | 03-27-2014 |

20100070833 | ARITHMETIC CIRCUIT FOR CONCATENATED CODES AND ADDRESS CONTROL METHOD - Concatenated codes are improved, and a memory capacity and a memory diagnosis circuit are reduced. Address control used in an interleaver of related art is applied to a register included in a syndrome arithmetic circuit or a check code calculation circuit of related art, and an arithmetic operation result equivalent to that obtained by interleaving is derived. | 03-18-2010 |

20130111304 | CYCLIC CODE DECODING METHOD AND CYCLIC CODE DECODER | 05-02-2013 |

20130318423 | MIS-CORRECTION AND NO-CORRECTION RATES FOR ERROR CONTROL - An embodiment is a method for encoding data with an error correction code. The method includes receiving a first number of data symbols by a memory controller, receiving a second number of meta-data sub-symbols, generating a third number of check symbols using an ECC, where the third number includes a difference between a number of symbols in an ECC codeword and the first number and generating a mismatch vector from the check and meta-data sub-symbols, where a number of sub-symbols of the mismatch vector includes the second number. The method also includes generating an adjustment syndrome symbol by multiplying the mismatch vector by a matrix, generating the third number of adjusted check symbols responsive to the adjustment syndrome symbol, and generating a final codeword by concatenating the adjusted check symbols and the data symbols, where the final codeword includes the number of symbols in the ECC codeword. | 11-28-2013 |

20130254637 | ENCODING APPARATUS, CONTROL METHOD OF ENCODING APPARATUS, AND MEMORY DEVICE - According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit. | 09-26-2013 |

20130111303 | SINGLE ERROR CORRECTION & DEVICE FAILURE DETECTION FOR X8 SDRAM DEVICES IN BL8 MEMORY OPERATION | 05-02-2013 |

20130326315 | EVALUATION OF POLYNOMIALS OVER FINITE FIELDS AND DECODING OF CYCLIC CODES - An apparatus and method are disclosed for evaluating an input polynomial (p(x)) in a (possibly trivial) extension of the finite field of its coefficients, which are useful in applications such as syndrome evaluation in the decoding of cyclic codes. The apparatus comprises a decomposition/evaluation module ( | 12-05-2013 |

20130031447 | FAST DETECTION OF CONVERGENCE OR DIVERGENCE IN ITERATIVE DECODING - A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate. | 01-31-2013 |

20140164884 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 06-12-2014 |

20140181624 | Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity-Check Codes - A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword. | 06-26-2014 |

20130036341 | COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA - Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug. | 02-07-2013 |