# Reed-Solomon code

## Subclass of:

## 714 - Error detection/correction and fault detection/recovery

## 714699000 - PULSE OR DATA ERROR HANDLING

## 714746000 - Digital data error correction

## 714752000 - Forward correction by block code

## 714781000 - Code based on generator polynomial

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

714784000 | Reed-Solomon code | 85 |

20090172501 | Multi-State Symbol Error Correction in Matrix Based Codes - Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols in error are reconstructed from symbols not in error, error syndromes and check symbols not in error. Deliberately created errors that can be corrected are used as nuisance errors. | 07-02-2009 |

20080288851 | DIGITAL BROADCAST TRANSMISSION AND RECEPTION APPARATUSES AND METHODS THEREOF - A digital broadcast transmission apparatus includes a Reed-Solomon (RS) encoder to perform RS encoding of data to obtain RS-encoded data formatted in data packets each including a predetermined number of bytes; a sync byte inserter to insert sync bytes indicating a start point of one of the data packets in a predetermined location of the RS-encoded data; an interleaver to interleave the RS-encoded data after the sync bytes have been inserted in the RS-encoded data to obtain interleaved data; and a data stuffer to sequentially insert complete packets of the interleaved data each including the predetermined number of bytes in a field, and insert an initial portion of a final packet of the interleaved data beginning in the field in residual bytes of the field that are less than the predetermined number of bytes. | 11-20-2008 |

20120246547 | HIGH RATE LOCALLY DECODABLE CODES - Data storage techniques and solutions simultaneously provide efficient random access to information and high noise resilience. The amount of storage space utilized is only slightly larger than the size of the data. The solution is based on locally decodable error-correcting codes (also referred to as locally decodable codes or LDCs). Locally decodable codes are described herein that are more efficient than conventional locally decodable codes. Such locally decodable codes are referred to as “multiplicity codes”. These codes are based on evaluating multivariate polynomials and their derivatives. Multiplicity codes extend traditional multivariate polynomial based (e.g., Reed-Muller) codes. Multiplicity codes inherit the local decodability of Reed-Muller codes, and at the same time achieve substantially better parameters. | 09-27-2012 |

20130080863 | STORAGE DEVICE - According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits. | 03-28-2013 |

20100107041 | METHOD AND SYSTEM FOR REDUCTION OF DECODING COMPLEXITY IN A COMMUNICATION SYSTEM - Method and System for Utilization of an Outer Decoder in a Broadcast Services Communication System is described. Information to be transmitted is provided to a systematic portion of a plurality of transmit buffers and encoded by an outer decoder communicatively coupled to the transmit buffer. The resulting redundant bits are provided to a parity portion of each transmit buffer. The content of the transmit buffers, is multiplexed and encoded by an inner decoder to improve protection by adding redundancy. The receiving station recovers the transmitted information by an inverse process. Because a decoding complexity depends on the size of a systematic portion of the transmit buffer, reasoned compromise between a systematic portion size and number of transmit buffers yields decreased decoding complexity. | 04-29-2010 |

20090307566 | ITERATIVE DECODING METHOD AND APPARATUS - An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N. | 12-10-2009 |

20090271688 | COMMUNICATION SIGNAL DECODING WITH ITERATIVE COOPERATION BETWEEN INNER AND OUTER CODES - Received communication signals may be decoded according to a combined, iterative inner code-outer code decoding technique. The inner code decoding is based on information produced by the outer code decoding. | 10-29-2009 |

20090271686 | COMMUNICATION SIGNAL DECODING WITH ITERATIVE COOPERATION BETWEEN TURBO AND REED-SOLOMON DECODING - Received communication signals may be decoded according to a combined turbo-RS (Reed-Solomon) decoding technique. The turbo decoding is based on information produced by the RS decoding. | 10-29-2009 |

20100235719 | ENCODER AND OPTICAL DISK RECORDING APPARATUS - An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block. | 09-16-2010 |

20100115382 | Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method - An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal. | 05-06-2010 |

20090271687 | TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING DATA IN THE TRANSMITTING/RECEIVING SYSTEM - A digital broadcasting system and a data processing method of the same are disclosed. The receiving system includes a receiving unit, a demodulator, a block decoder, and an RS frame decoder. The receiving unit receives a broadcast signal including mobile service data divided into a plurality of output masses, signaling information associated with the mobile service data, and known data. The demodulator demodulates the received broadcast signal. The block decoder block-decodes the demodulated mobile service data of the plurality of output masses based upon the signaling information, thereby outputting the mobile service data of one output mass. And, the RS frame decoder configures an RS frame with the block-decoded and outputted mobile service data, and performs error-correction decoding on the corresponding mobile service data in RS frame units. | 10-29-2009 |

20120011420 | CHANNEL EQUALIZER AND METHOD OF PROCESSING TELEVISION SIGNAL IN DTV SYSTEM - A channel equalizer includes a channel estimator, a coefficient calculator, a multiplier, and an error remover. The channel estimator estimates a channel impulse response (CIR) of input data in which a known data sequence is periodically inserted. The coefficient calculator calculates equalization coefficients using estimated CIR, and the multiplier multiplies the input data with the equalization coefficients for channel equalization. The error removes estimates a residual carrier phase error of the channel-equalized input data and removes the estimated phase error from the input data. | 01-12-2012 |

20100223536 | DTV TRANSMITTING SYSTEM AND METHOD OF PROCESSING DATA IN DTV TRANSMITTING SYSTEM - A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaver interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets. | 09-02-2010 |

20100281346 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet. | 11-04-2010 |

20100281344 | SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON DECODER - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword. | 11-04-2010 |

20100281345 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet. | 11-04-2010 |

20090177949 | METHOD FOR PROTECTING MULTIMEDIA DATA USING ADDITIONAL NETWORK ABSTRACTION LAYERS (NAL) - A method for protecting multimedia data encoded by the H.264 standard, the data being encapsulated in a structure of the network abstraction layer or NAL type, characterized in that the user inserts at least one redundancy NAL containing the error-correcting code used for transmitting the data. | 07-09-2009 |

20100146373 | CONFIGURABLE HIERARCHICAL COMMA-FREE REED-SOLOMON DECODING CIRCUIT AND METHOD THEREOF - The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements. | 06-10-2010 |

20080244363 | REED SOLOMON DECODER AND IBMA METHOD AND PARALLEL-TO-SERIAL CONVERSION METHOD THEREOF - A parallel-to-serial conversion method for IBMA in a Reed Solomon decoder is used for obtaining discrepancies in IBMA iterations, thereby acquiring an error location polynomial and an error value polynomial. Syndrome sequences for the calculation of discrepancies in IBMA iterations have a fixed length. The number of syndromes is t+1, where t is the largest number of symbols that can be corrected of the error location polynomial. The feature that syndrome sequences have the same length is based on the fact that the discrepancies are not affected if the coefficients of polynomial orders of the error location polynomial are zero. | 10-02-2008 |

20100138727 | DIGITAL BROADCASTING RECEIVER AND METHOD FOR CONTROLLING THE SAME - A reception system and a method for processing data in the reception system are disclosed. The reception system includes a baseband processor receiving a broadcasting signal including mobile service data and main service data, the mobile service data including first service data and second service data having a format different from that of the first service data, the second service data configuring a Reed Solomon (RS) frame, and the RS frame including a table which describes the second service data and signaling information of the second service data, a table handler parsing the table from the RS frame and extracting the signaling information of the second service data, and service handlers parsing the second service data from the RS frame on the basis of the extracted signaling information of the second service data. Accordingly, it is possible to transmit/receive service data having a format different from that of the existing method in a single MH system. | 06-03-2010 |

20080270873 | Decoding Method for Algebraic Geometric Codes and Associated Device - The present invention relates to a method of decoding a one-point algebraic geometric code defined on an algebraic curve of type C(a,b) represented by an equation F(X,Y)=0 of degree b in X and of degree a in Y over F | 10-30-2008 |

20090083607 | CODING PATTERN COMPRISING REED-SOLOMON CODEWORDS ENCODED BY MIXED MULTI-PULSE POSITION MODULATION - A substrate having a coding pattern disposed on a surface thereof. The coding pattern comprises a plurality of macrodots encoding Reed-Solomon codewords. Each codeword is comprised of Reed-Solomon data symbols and Reed-Solomon redundancy symbols. The coding pattern encodes the symbols using mixed multi-pulse position modulation, with a higher number of symbol values available for redundancy symbols than data symbols. | 03-26-2009 |

20080201627 | Communication Device, Communication Method, and Computer Program - A communication device configured to perform packet reception processing, with the header of a packet including a header sequence and a Reed-Solomon code, includes: a header check sequence inspecting unit configured to detect, based on the header check sequence included in a received packet header, an error of the header; a Reed-Solomon encoding unit configured to encode the header of a received packet other than the Reed-Solomon code to generate a Reed-Solomon code; a Reed-Solomon code inspecting unit configured to detect whether or not the Reed-Solomon code generated by the Reed-Solomon encoding unit is completely identical to the Reed-Solomon code within the received packet header; and a processing control unit configured to control payload processing of a received packet in accordance with the inspection results of the header check sequence inspecting unit and the Reed-Solomon code inspecting unit. | 08-21-2008 |

20090031197 | ERASURE DECODING FOR RECEIVERS - A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction. | 01-29-2009 |

20090199075 | Array form reed-solomon implementation as an instruction set extension - A parallelized or array method is developed for the generation of Reed Solomon parity bytes which utilizes multiple digital logic operations or computer instructions implemented using digital logic. At least one of the operations or instructions used performs the following combinations of steps: a) provide an operand representing N feedback terms where N is greater than one, b) computation of N by M Galios Field polynomial multiplications where M is greater than one, and c) computation of (N−1) by M Galios Field additions producing M result bytes. In this case the result bytes are used to modify the Reed Solomon parity bytes in either a separate operation or instruction or as part of the same operation. | 08-06-2009 |

20090063937 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-05-2009 |

20090055716 | Efficient Chien search method and system in Reed-Solomon decoding - An efficient Chien search method in Reed-Solomon decoding is adapted for use in a processor having a parallel processing instruction set. The method includes the following steps: (a) if an error location polynomial that has been found matches a preset condition, finding at least one error symbol location directly through table lookup; (b) if the error location polynomial does not match the preset condition, executing steps (c) to (e); (c) calculating an error evaluation value; (d) if the error evaluation value is equal to 0, storing an error symbol location in an error location memory; and (e) if the error evaluation value is not equal to 0, the flow returning to step (c). | 02-26-2009 |

20090083608 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-26-2009 |

20080307291 | PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed. | 12-11-2008 |

20100211857 | ERROR CORRECTION DECODING DEVICE AND REPRODUCTION DEVICE - A decoding device which performs error correction decoding of encoded data formed from a combination of an outer code for first error correction and an inner code for second error correction is disclosed. The decoding device has: a demodulator for creating a data series of likelihood information values; a second error correction decoder for creating a hard decision value series by executing repetitive decoding for the second error correction based on the likelihood information values; and a first error correction decoder for detecting a lost bit in the hard decision value series and creating an erasure flag indicating the position of the detected lost bit. The second error correction decoder, according to the erasure flag, executes the repetitive decoding based on a likelihood information value not corresponding to the position of the lost bit among the data series of the likelihood information values and a predetermined value that invalidates the likelihood information value corresponding to the position of the lost bit. | 08-19-2010 |

20090282320 | ITERATIVE DECODER WITH STOPPING CRITERION GENERATED FROM ERROR LOCATION POLYNOMIAL - A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code. | 11-12-2009 |

20090063938 | Decoding Error Correction Codes Using A Modular Single Recursion Implementation - Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm. | 03-05-2009 |

20100223535 | METHOD AND APPARATUS FOR ENCODING AND DECODING DATA - The embodiments of the present invention provide a data coding method. In this data coding method, a synchronization header is added to the data that has undergone line coding and FEC coding, and then the data is framed and sent out. The embodiments of the present invention also provide the corresponding data decoding method, data coding apparatus, and data decoding apparatus. Because the redundant information for synchronization is added, the synchronization performance of the transmission system is ensured effectively even if the algorithm selected in the line coding provides low redundancy; moreover, the added synchronization header does not participate in the FEC coding calculation, thus preventing impact on the FEC coding gain. | 09-02-2010 |

20100306628 | COMPUTER READABLE MEDIUM WITH INSTRUCTIONS FOR RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT - A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system. | 12-02-2010 |

20090106632 | DIGITAL BROADCAST TRANSMITTER/RECEIVER HAVING AN IMPROVED RECEIVING PERFORMANCE AND SIGNAL PROCESSING METHOD THEREOF - A digital broadcast transmitting/receiving system, and a signal processing method thereof, includes a randomizer for randomizing a transport stream into a specified position of which stuff bytes are inserted, a stuff-byte exchanger for replacing the stuff bytes included in data output from the randomizer with specified known data, an RS encoder for performing an RS-encoding of data output from the stuff-byte exchanger, an interleaver for interleaving data output from the RS encoder, a trellis encoder for performing a trellis encoding of data output from the interleaver, an RS parity generator for generating a parity by performing an RS encoding of data output from the RS encoder, and outputting the generated parity to the trellis encoder, and a modulator/RF converter for modulating data output from the trellis encoder and performing an RF up-converting of the modulated data. The digital broadcast receiving performance can be improved even in an inferior multi-path channel by detecting the known data from the received signal and using the known data for synchronization and equalization in a digital broadcast receiver. | 04-23-2009 |

20100199155 | METHOD AND APPARATUS FOR QUANTIFICATION OF DNA SEQUENCING QUALITY AND CONSTRUCTION OF A CHARACTERIZABLE MODEL SYSTEM USING REED-SOLOMON CODES - Data extracted from fluorosphore responses of fluorophore labeled bases in genetic material used in sequencing of unknown fragments from a defined set of for example a model system are converted into a class of block codes that are then employed in a computer-based process to compare and correct preliminary calls of calls of the categorically known genetic material. In a specific embodiment, the Reed-Solomon codes are employed to identify one or more errors as may occur in a finite block of codes. The methodology is also useful to identify elements of a real system containing known elements in the form of a tag. Reed-Solomon sensors may be employed with and in addition to other types of genome sensors. | 08-05-2010 |

20100199154 | Reduced processing in high-speed Reed-Solomon decoding - Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift. | 08-05-2010 |

20120042228 | BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS - Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure. | 02-16-2012 |

20100138726 | MPE-FEC RS DECODER AND DECODING METHOD THEREOF - A decoding method of an MPE-FEC (MultiProtocol Encapsulation-Forward Error Correction) RS (Reed-Solomon) decoder, includes: substituting a value corresponding to an erasure error position with 0 in a reception signal; calculating a syndrome by using the reception signal; calculating an erasure position polynomial by using erasure information; calculating a modified syndrome by using the syndrome and the erasure position polynomial; calculating an erasure error size polynomial by using the modified syndrome; calculating an error position by using the erasure position polynomial; calculating an error size by using a modified Formey's algorithm; and correcting an error through the error position and the error size. | 06-03-2010 |

20100031127 | SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERASURE DECODER - A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial. | 02-04-2010 |

20100241932 | ERROR DETECTOR/CORRECTOR, MEMORY CONTROLLER, AND SEMICONDUCTOR MEMORY DEVICE - An error detector/corrector includes an ECC cache unit configured to store an error bit address which represents an error location by associating the error bit address with an error page address and a coefficient α of an error location polynomial; a comparison unit configured to check for a match by comparing new values with stored values, where the new values are an error page address detected by a syndrome calculation unit and a coefficient α of the error location polynomial calculated by a polynomial calculation unit while the stored values are an error page address and a coefficient α of the error location polynomial stored in the ECC cache unit; and a first error localization unit configured to identify a location of the error bit address stored in the ECC cache unit as the error location when the comparison unit determines that the compared values match. | 09-23-2010 |

20100192045 | DEVICE FOR PROCESSING STREAMS AND METHOD THEREOF - A device for processing streams is disclosed. The device includes a stream arranging unit which stacks and rearranges a stream, and a dummy inserting unit which inserts a dummy into the rearranged stream. The device may further include a convolutional interleaver which interleaves the stream with a dummy or an RS encoder and a CRC encoder. | 07-29-2010 |

20100058150 | Coding Apparatus and Method - Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in units of mp (a multiple of p) symbols; mp generator polynomials are used; and the generator polynomials g | 03-04-2010 |

20110214038 | Methods and Systems for Rapid Error Correction of Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor. | 09-01-2011 |

20110252293 | Concatenated Coding Architecture for G.hnem PHY - Embodiments provide a method for determining the number of parity bytes that are added by a Reed-Solomon encoder. The number of parity bytes are equivalent to the error correcting capability of the Reed-Solomon code. The number of parity bytes is based on the payload length or the information block size used in the Reed-Solomon encoder. Other factors may also be used to make this choice. | 10-13-2011 |

20110154164 | TRANSMITTER AND RECEIVER FOR TERRESTRIAL DIGITAL MULTIMEDIA BROADCASTING - Provided is a terrestrial digital broadcasting transmitter. The terrestrial digital broadcasting transmitter may include a Reed-Solomon (RS) encoder to RS-encode an inputted broadcast signal, a forward error correction (FEC) encoder to channel-encode an inputted additional signal associated with the broadcast signal, a selector to select the RS-encoded broadcast signal or the channel-encoded additional signal, and a vestigial side band (VSB) transmitting part to transmit, to a receiver via a transmitting antenna, the selected signal, the selected signal being the RS-encoded broadcast signal or the channel-encoded additional signal selected by the selector. | 06-23-2011 |

20110258520 | LOCATING AND CORRECTING CORRUPT DATA OR SYNDROME BLOCKS - Disclosed is a method and system of determining a data block of a RAID level 6 stripe that has corrupted or incorrect data. For each data block of the stripe, a reconstructed data block is created using the other data blocks and the P syndrome data block. The reconstructed data block and the other data blocks are used to create a new Q syndrome data block. The new Q syndrome data block and the stored Q syndrome data block are compared. If the new Q syndrome data block and the stored Q syndrome data block match, the data block is marked as being suspected as having corrupted or incorrect data. This process is repeated for every data block in the stripe. If there is only a single suspected data block, the reconstructed data block is stored as a replacement of the suspect data block in the stripe. | 10-20-2011 |

20110191657 | Systems for High-Speed Backplane Applications Using FEC Encoding - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. | 08-04-2011 |

20090292976 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR IDENTIFICATION AND EVALUATION - Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | 11-26-2009 |

20100031128 | SHARED INFORMATION GENERATING APPARATUS AND RECOVERING APPARATUS - There is disclosed a system for identifying falsified secret information shares included in k secret information shares used to recover secret information according to a (k,n)-threshold secret sharing scheme, and producing falsified secret information shares of reduced size. A shared information generating apparatus generates cheater identifying information Ai (i=1, 2, . . . , n) using n secret information shares Vi generated according to the (k,n)-threshold secret sharing scheme and random polynomials. A recovering apparatus detects cheated secret information shares using the arbitrary k secret information shares and k cheater identifying information, and recovers the secret information from the k secret information shares if it detects no cheated secret information shares. | 02-04-2010 |

20090150753 | Data Fragmentation Identification in a Data Table - The subject matter disclosed herein provides a mechanism for identifying packet boundaries in a data table, such as a Reed-Solomon table. The method may include receiving one or more packets for insertion into a table. A first indicator may be inserted into the table. The first indicator may be associated with one or more rows of the table and may identify whether each of the one or more rows includes one or more fragments (e.g., a packet beginning, a packet ending, and the like). In each of the rows identified by the first indicator as including one or more fragments, a second indicator may be inserted. The second indicator may represent a length in bytes of at least one of the corresponding packet fragments. Related systems, apparatus, methods, and/or articles are also described. | 06-11-2009 |

20120011419 | TRANSMISSION SYSTEM, METHOD AND PROGRAM - A transmitting apparatus generates and transmits 3t+1 or more number of codewords for a message and multiple faulty encoded message identifying data, wherein the information regarding the message may not be obtained from t or less number of encoded messages and the message can be decoded from 2t+1 or more codewords. The faulty encoded message identifying data are able to detect t or less number of faulty codewords of the message, even if there are t or less number of faulty codewords. A receiving apparatus checks whether there is no fault in each codeword for the message, using the codewords of the message and faulty encoded message identifying data for the codewords of the message received and the corresponding faulty encoded message identifying data and also checks whether the codewords decided to be non-faulty are all of the same message. The receiving apparatus, if the codewords decided to be non-faulty are all of the same message, decodes the message from the codewords decided to be non-faulty, and outputs the so decoded message and if otherwise, outputs a signal indicating failure in message reception. | 01-12-2012 |

20120159287 | Off-Line Delivery Of Content Through An Active Screen Display - A computer-implemented system and method for off-line delivery of content through an active screen display are provided. A processor includes an encoding application to assemble and encode digitally-stored content into encoded content, and to interleave the encoded content with a signal conveying a live screen representation. The live screen representation includes output of a user interface for applications executing on the processor. An active screen display is coupled to the processor over a physical display interface connection. The active screen display includes a runtime application to identify the encoded content within the signal on the active screen display and to decode the encoded content into decoded content. The active screen display further includes an offline application to unilaterally display the decoded content on the active screen display without use of the processor and in an absence of the live screen presentation. | 06-21-2012 |

20120233527 | Methods and Systems for Rapid Error Location in Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor. | 09-13-2012 |

20120079356 | DIGITAL BROADCASTING SYSTEM AND DATA PROCESSING METHOD - A digital broadcasting system and method of processing data therein are disclosed. According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups. | 03-29-2012 |

20100205512 | DIGITAL TELEVISION TRANSMITTER/RECEIVER AND METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER/RECEIVER - A digital television (DTV) transmitter/receiver and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced, data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and inserts known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. And, an RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity plate holders to each enhanced data packet. Herein, the RS encoder may insert non-systematic RS parity data or null data into the RS parity place holders included in each enhanced data packet. | 08-12-2010 |

20110185266 | METHOD OF DECODING A PATTERN-ENCODED COORDINATE - A method of decoding a coding pattern disposed on or in a substrate. The method comprises the steps of: (a) operatively positioning an optical reader relative to a surface of the substrate; (b) capturing an image of a portion of the coding pattern, the coding pattern comprising a plurality of square tags of length/identifying two-dimensional location coordinates; and (c) sampling and decoding x-coordinate data symbols within the imaged portion and y-coordinate data symbols within the imaged portion. The imaged portion has a predetermined diameter and is guaranteed to contain sufficient data symbols from each of the Reed-Solomon codes so that symbol errors are correctable in each of the codes during the decoding. | 07-28-2011 |

20100275106 | DTV TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets. | 10-28-2010 |

20100011277 | ADJUSTABLE ERROR-CORRECTION FOR A REED SOLOMON ENCODER/DECODER - Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices. | 01-14-2010 |

20120254704 | REED-SOLOMON DECODER AND RECEPTION APPARATUS - According to one embodiment, a Reed-Solomon decoder comprises an analyzer and a calculator. The analyzer analyzes a data frame and calculates a size of a last code word located at an end of a data portion, using information included in a header portion. The calculator calculates correction coefficients, using the size of the last code word, for correcting coefficients of an error locator polynomial and coefficients of an error value polynomial for the last code word in accordance with a difference between a base size of Reed-Solomon code words and the size of the last code word, before error detection for a code word located immediately before the last code word in the data portion begins. | 10-04-2012 |

20120254703 | APPARATUS AND METHODS FOR SELECTIVE BLOCK DECODING - Apparatus and methods for selective decoding of received code blocks are disclosed. An example method includes receiving a code block, determining a code block quality indicator for the received code block, and attempting to decode the received code block if the code block quality indicator is greater than or equal to a threshold. If the code block quality indicator is less than the threshold, the received code block is discarded without decoding attempts. The threshold may be a static or dynamic threshold. | 10-04-2012 |

20100229075 | CHIP BLANKING AND PROCESSING IN SCDMA TO MITIGATE IMPULSE AND BURST NOISE AND/OR DISTORTION - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-09-2010 |

20110320918 | ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM - Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations. | 12-29-2011 |

20120151303 | FORWARD ERROR CORRECTION WITH BIT-WISE INTERLEAVING - The present invention improves communication systems by providing a virtual binary erasure channel over a frame-based data exchange infrastructure, through a combination of time diversity mechanisms with bit-based interleaving agents. The interleaving agents are judiciously positioned in the data processing path to provide benefits to the forward error correction functions of the communication system. The invention thus allows for a significant reduction of the complexity of the error correction facilities of a communication system such as a DVB-SH system, by allowing the efficient use of a low-complexity binary based decoder. | 06-14-2012 |

20080244364 | Method And Apparatus For Code Group Identification And Frame Synchronization By Use Of Reed-Solomon Decoder And Reliability Measurement For UMTS W-CDMA - A method and apparatus having a modified Reed-Solomon decoder is used for finding a specific code group used by a base station and the frame timing synchronization with the base station. The modified Reed-Solomon decoder uses a standard Reed-Solomon decoder and some reliability measurements computed from the received code word symbols. If the reliability of a received symbol is too low, this symbol is considered as erasure. By selecting code word symbols with higher reliabilities and erasing code word symbols with lower reliabilities, the symbol error probability is reduced and the performance is improved. Several modified Reed-Solomon decoders and a few decoding strategies are introduced in order to decode the received code word sequences with a power- and memory-effective method. | 10-02-2008 |

20130097475 | LDPC Decoder With Targeted Symbol Flipping - Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor. | 04-18-2013 |

20100017688 | Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously - Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach. | 01-21-2010 |

20130145237 | Methods and Systems for Rapid Error Location in Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor. | 06-06-2013 |

20120137197 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 05-31-2012 |

20130238961 | Systems for High-Speed Backplane Applications Using FEC Encoding - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmuted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. | 09-12-2013 |

20110035648 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaver which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet. | 02-10-2011 |

20130185614 | Lost Real-Time Media Packet Recovery - Systems, methods and computer program products for facilitating the recovery of lost real-time media packets within a computer network real-time application implementing Forward Error Control (FEC), such that server performance is not affected from a CPU and memory perspective, are disclosed. In an embodiment, a conference server that is part of a communication network compliant with the Real Time Transport Protocol (RTP) is able to avoid regenerating FEC packets by not performing any FEC coding operation on the packets unless it is flagged to indicate regeneration via an FEC (e.g., Reed-Solomon) coding is necessary. Absent the flag, the conference server updates the received FEC packet as per the RTP and transmits the packet to its ultimate destination. Such disclosed systems, methods and computer program products are independent of the nature of the media being protected and flexible enough to support a wide variety of FEC techniques. | 07-18-2013 |

20130254636 | SYSTEM ON CHIP AND METHOD FOR CRYPTOGRAPHY USING A PHYSICALLY UNCLONABLE FUNCTION - A system and method for performing cryptographic functions in hardware using read-N keys comprising a cryptographic core, seed register, physically unclonable function (PUF), an error-correction core, a decryption register, and an encryption register. The PUF configured to receive a seed value as an input to generate a key as an output. The error-correction core configured to transmit the key to the cryptographic core. The encryption register and decryption register configured to receive the seed value and the output. The system, a PUF ROK, configured to generate keys that are used N times to perform cryptographic functions. | 09-26-2013 |

20090055717 | ARCHITECTURE AND CONTROL OF REED-SOLOMON LIST DECODING - Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | 02-26-2009 |

20100153825 | DIGITAL BROADCASTING SYSTEM AND METHOD - A digital broadcasting system and method, where the digital broadcasting system includes: a transmission stream generator multiplexing a normal stream and a turbo stream to generate a dual transmission stream; a transmitter inserting an supplementary reference signal (SRS) into the dual transmission stream, processing the turbo stream to reconstitute the dual transmission stream, and outputting the reconstituted dual transmission stream; and a receiver receiving the reconstituted dual transmission stream, separately turbo decoding the turbo stream, inserting the turbo decode turbo stream into the dual transmission stream, and decoding the dual transmission stream into which the turbo decoded turbo stream has been inserted, to restore normal stream data and turbo stream data. Thus, reception sensitivity of a digital broadcasting signal can be efficiently improved. | 06-17-2010 |

20130061116 | CONCURRENT DECODING OF DATA STREAMS - A method begins by a dispersed storage (DS) processing module receiving one or more pairs of coded values. The method continues with the DS processing module creating a received coded matrix from the one or more pairs of coded values. When the received coded matrix includes a decode threshold number of pairs of coded values, the method continues with the DS processing module generating a data matrix from the received coded matrix and an encoding matrix, reproducing a one of a first plurality of data segments from a first plurality of data blocks of the data matrix, and reproducing a one of a second plurality of data segments from a second plurality of data blocks of the data matrix, wherein the one of the first plurality of data segments and the one of the second plurality of data segments maintain the time alignment of a first and second data streams. | 03-07-2013 |

20090300470 | MEMORY ARCHITECTURE FOR HIGH THROUGHPUT RS DECODING FOR MEDIAFLO RECEIVERS - A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput. | 12-03-2009 |

20130275840 | DISTRIBUTED DATA DISTRIBUTION - Data may be distributed using data carousels. After a device receives the data, or a portion thereof, the device may make available a data carousel that allows others to receive the data. Each data carousel may contain a portion of the data. Data carousels may also contain error correction information that can be used to reconstruct missing portions of the data being distributed. A carousel directory may keep track of the carousel structure and direct the behavior of devices that are receiving data and/or distributing data. | 10-17-2013 |

20140040708 | Method And Apparatus For Determining Bits in a Convolutionally Decoded Output Bit Stream to be Marked For Erasure - A method and apparatus are provided for determining bits in a convolutionally decoded output bit stream to be marked for erasure. K-bits and p-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits and p-bits of a delayed version of the input bit stream. For each bit of the k-bits (p-bits) in the convolutionally encoded output bit stream and in the corresponding k-bits (p-bits) of the delayed version of the input bit stream, a number of or pattern of conflicting bits and whether the number of conflicting bits exceeds a threshold number or pattern of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the k-bit streams marked for erasure. | 02-06-2014 |

20080320372 | Reed solomon decoder - Techniques, systems and computer program products are described for providing a Reed Solomon decoder. The Reed Solomon decoder includes a syndrome polynomial generator to generate syndrome polynomials for subchannel data received from subchannels. In addition, a syndrome polynomial selector selects one of the generated syndrome polynomials according to a preset priority. An error location/error value polynomial generator generates an error location polynomial and an error value polynomial by applying a first algorithm to the selected syndrome polynomial. Also an error location/error value calculator calculates an error location by applying a second algorithm to the error location polynomial and calculates an error value by applying a third algorithm to the error value polynomial. Further, an error corrector corrects an error included in the received subchannel data by applying the calculated error location and the calculated error value to the received subchannel data. | 12-25-2008 |

20080320371 | EFFICIENT CHIEN SEARCH METHOD IN REED-SOLOMON DECODING, AND MACHINE-READABLE RECORDING MEDIUM INCLUDING INSTRUCTIONS FOR EXECUTING THE METHOD - An efficient Chien search method in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes the following steps: (a) calculating an error evaluation value; (b) subjecting the error evaluation value to mapping processing so as to find an index adjusting value; (c) storing a symbol index into an error location memory corresponding to a location index; (d) updating the location index according to the index adjusting value; (e) updating the symbol index; and (f) repeating steps (a) to (e) a particular number of times. The method primarily aims to reduce program flow branching so as to enhance the computation efficiency of the Chien search process. | 12-25-2008 |

20120284588 | 11-08-2012 | |

20120166915 | Method and Device for Decoding Reed-Solomon (RS) Code - The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result. | 06-28-2012 |

20100070832 | REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS - A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values. | 03-18-2010 |

20100070831 | VARIABLE REDUNDANCY REED-SOLOMON ENCODER - A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols. | 03-18-2010 |