Class / Patent application number | Description | Number of patent applications / Date published |
714782000 | Bose-Chaudhuri-Hocquenghem code | 52 |
20090024906 | Method and apparatus for data transmission using multiple transmit antenas - A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements may be provided in antenna output channels, or with suitable code construction delay may be omitted. n signals represent n symbols of a codeword are transmitted with n different transmit antennas. At the receiver MLSE or other decoding is used to decode the noisy received sequence. The parallel transmission and channel coding enables an increase the data rate over previous techniques, and recovery even under fading conditions. The channel coding may be concatenated with error correction codes under appropriate conditions. | 01-22-2009 |
20090044081 | METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES IN SUPPORT OF BROADBAND SATELLITE APPLICATIONS - An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite. | 02-12-2009 |
20090049366 | MEMORY DEVICE WITH ERROR CORRECTION SYSTEM - There is disclosed a memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: divide an error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of the solution candidates with those of the syndromes, the corresponding relationships being previously obtained as a table, thereby obtaining error locations. | 02-19-2009 |
20090077448 | Forward error correction codec - A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes. The invention encodes a stream of data employing a plurality of serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes, arranging said data into a frame of parallel data blocks (the outer frame) with redundancy bits appended by a BCH( | 03-19-2009 |
20090113275 | BCH CODE WITH 256 INFORMATION BYTES AND UP TO 8 BYTES OF PARITY CHECK ELEMENTS - A coding system comprises pre-multiply the message u(x) by Xn−k. Obtain the remainder b(x), i.e. the parity check digits. And combine b(x) and Xn−ku(x) to obtain the code polynomial. A decoding method comprises calculating a syndrome; finding an error-location polynomial; and computing a set of error location numbers. | 04-30-2009 |
20090158129 | METHOD AND APPARATUS FOR ENCODING AND DECODING CHANNEL IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES - A method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes generating a plurality of column groups by grouping (categorizing) columns corresponding to an information word in a parity-check matrix of the LDPC code, and ordering the column groups; determining a range of an information word desired to be obtained by performing shortening; based on the determined range of the information word, performing column group-by-column group shortening on the column groups in order according to a predetermined shortening pattern; and LDPC encoding the shortened information word. | 06-18-2009 |
20090187811 | METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) ENCODING - An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix. | 07-23-2009 |
20090187812 | PROCESSING MODULE, ERROR CORRECTION DECODING CIRCUIT, AND PROCESSING METHOD FOR ERROR LOCATOR POLYNOMIAL - A Euclid processing module for binary BCH code which have been encoded with multidimensional Galois fields, and which correct a large number of word errors. The coefficients of polynomials R | 07-23-2009 |
20090259921 | METHOD AND APPARATUS FOR DECODING SHORTENED BCH CODES OR REED-SOLOMON CODES - The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied. | 10-15-2009 |
20100031126 | System and method for using the universal multipole for the implementation of a configurable binary bose-chaudhuri-hocquenghem (BCH) encoder with variable number of errors - The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output. | 02-04-2010 |
20100042907 | Programmable Error Correction Capability for BCH Codes - An embodiment of the invention relates to a BCH encoder formed with linear feedback shift registers (LFSRs) to form quotients and products of input polynomials with irreducible polynomials of a generator polynomial g(x) of the BCH encoder, with and without pre-multiplication by a factor x | 02-18-2010 |
20100115381 | ERROR CORRECTION OF AN ENCODED MESSAGE - An encoded message is stored in a first memory. The encoded message is retrieved from the first memory as a retrieved encoded message that may contain an error. Syndromes are generated from the retrieved encoded message. The syndromes are used to determine if the retrieved encoded message has an error. Polynomial coefficients are generated for establishing a polynomial equation having a first number of solutions. The polynomial equation is solved only for a second number of solutions. The first number is greater than the second number. The second number of solutions comprises solutions corresponding to locations in the retrieved encoded message. Each location is corrected in the retrieved encoded message that corresponds to a solution of zero of the polynomial equation. The result is efficient error correction. | 05-06-2010 |
20100122149 | CONTINUOUSLY INTERLEAVED ERROR CORRECTION - Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes. | 05-13-2010 |
20100131831 | LOW POWER CHIEN-SEARCH BASED BCH/RS DECODING SYSTEM FOR FLASH MEMORY, MOBILE COMMUNICATIONS DEVICES AND OTHER APPLICATIONS - A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied. | 05-27-2010 |
20100229074 | METHOD AND APPARATUS FOR TRANSMITTING DATA IN OPTICAL TRANSPORT NETWORK - A method of transmitting data in an optical transport network is provided. The method comprises generating an optical transmission unit frame including an in-band area including a first area to which information data is allocated and a second area to which the information data is not allocated and an out-band area including parity information and transmitting the data through the optical transmission unit frame. | 09-09-2010 |
20100262894 | ERROR CORRECTION FOR A DATA STORAGE DEVICE - An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers. | 10-14-2010 |
20100299580 | BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION - An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to calculate a plurality of preliminary syndromes from a plurality of received symbols. The second circuit may be configured to calculate a plurality of normal syndromes by modifying the preliminary syndromes using at most two Galois Field multiplications. The third circuit is generally configured to calculate an errata polynomial based on the normal syndromes. | 11-25-2010 |
20100332956 | POLYNOMIAL DIVISION - Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number. | 12-30-2010 |
20110004812 | CODER-DECODER AND METHOD FOR ENCODING AND DECODING AN ERROR CORRECTION CODE - The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data. | 01-06-2011 |
20110055668 | METHOD, DEVICE, AND DIGITAL CIRCUITY FOR PROVIDING A CLOSED-FORM SOLUTION TO A SCALED ERROR LOCATOR POLYNOMIAL USED IN BCH DECODING - A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed. | 03-03-2011 |
20110185265 | High-speed and agile encoder for variable strength long BCH codes - Agile BCH encoders are useful when the noise characteristics of the channel change which demands that the strength of the error correcting BCH code to be a variable. An agile encoder for encoding a linear cyclic code such as a BCH code, is a code that switches code strength (depth) relatively quickly in unit increments. The generator polynomial for the BCH code is provided in the factored form. The number of factored polynomials (minimal polynomials) chosen by the system determines the strength of the BCH code. The strength can vary from a weak code to a strong code in unit increments without a penalty on storage requirements for storing the factored polynomials. The BCH codeword is formed by a dividing network and a combining network. Special method is described that provides a trade off mechanism between latency and throughput while simultaneously optimizing the delay in the critical path which is in the forward path. Speed enhancements at minimal polynomial level are also provided by retiming, loop unfolding, loop unrolling, and special mathematical transformations. The presented invention can be implemented as an apparatus using software or hardware or in integrated circuit form. | 07-28-2011 |
20110202820 | METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) ENCODING AND DECODING - An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information. | 08-18-2011 |
20110209034 | Method for Improving the Acquisition of a Data Set Transmitted Repeatedly in a Difficult Environment - A method is provided for improving the acquisition of a data set transmitted repeatedly in a difficult environment, which is particularly appropriate to satellite radionavigation systems. The main characteristic of the method is to provide “contextual” aid relating to the transmitted data by indicating the nature and the possible updating of these data so that the receiver can accumulate the energy when the data are repeated in an identical manner. These aid data being short, it is possible to obtain good quality of reception and protection of this aid by virtue of its longer coding than that of the data. | 08-25-2011 |
20110239094 | ERROR CORRECTION MECHANISMS FOR FLASH MEMORIES - Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionaless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array. | 09-29-2011 |
20110283168 | Method of Handling Packet Loss Using Error-Correcting Codes and Block Rearrangement - A method of handling packet loss uses errorcorrecting codes and block rearrangement. This method divides the original data stream into data blocks, then codes the blocks by errorcorrecting codes. After coding the blocks, rearranges the coding blocks for spreading original data into new blocks and then transmitting the new blocks. | 11-17-2011 |
20120030546 | WATERMARKING ELECTRONIC TEXT DOCUMENTS - A text watermarking method embeds an auxiliary message in an original electronic text document to form a watermarked text document. The method applies a spreading function to message symbols to spread the symbols over a carrier, which forms a modulated carrier. It maps elements of the modulated carrier to corresponding inter-word spaces in the electronic text document, and applies an embedding function to modify the corresponding inter-word spaces according to elements of the modulated carrier signal such that the modified inter-word spaces hide the modulated carrier signal in the watermarked text document. The message symbols are automatically decodable from the watermarked document without the original electronic text document. A compatible decoder extracts the auxiliary message from a printed or electronic watermarked text document. The decoder automatically measures inter-word spaces in the watermarked text document. It estimates elements of a modulated carrier signal embedded in the inter-word spaces to form an estimated modulated carrier signal, and applies a de-spreading function to the estimated modulated carrier signal to extract message symbols. | 02-02-2012 |
20120072809 | DECODER, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE SAME - A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit. | 03-22-2012 |
20120131423 | BINARY BCH DECODERS - Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (Ω)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (Ω)} | 05-24-2012 |
20120137196 | FORWARD ERROR CORRECTION MAPPING AND DE-MAPPING TECHNIQUES - Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame. | 05-31-2012 |
20120198314 | SOFT DECODING SYSTEMS AND METHODS FOR FLASH BASED MEMORY SYSTEMS - Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword. | 08-02-2012 |
20120240013 | BCH DECODING WITH MULTIPLE SIGMA POLYNOMIAL CALCULATION ALGORITHMS - Bose-Chaudhuri-Hocquenghem (BCH) decoder architectures which execute a plurality of different algorithms to calculate an error location polynomial. The multiple algorithms may be implemented in a storage controller for increased throughput per gate count. Codewords needing up to a threshold number of corrections may be processed via a first algorithm while those with a greater number of corrections may be processed via the second algorithm. In embodiments, the Peterson-Gorenstein-Zierler (PGZ) algorithm and the Berlekamp-Massey algorithm (BMA) are executed either serially or in parallel to increase throughput of the decoder. | 09-20-2012 |
20120266051 | STAIRCASE FORWARD ERROR CORRECTION CODING - In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B | 10-18-2012 |
20130055051 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING INFORMATION IN A BROADCASTING/COMMUNICATION SYSTEM - A method and apparatus are provided for transmitting and receiving information in a broadcasting/communication system. The method includes comparing a number of bits of an information word to be transmitted with a predetermined threshold value; if the number of bits of the information word is less than the predetermined threshold value, determining a first parameter pair; if the number of bits of the information word is not less than the predetermined threshold value, determining a second parameter pair; determining a number of bits to be punctured based on one of the first parameter pair and the second parameter pair; and puncturing the determined number of bits to be punctured, with respect to parity bits of a codeword generated by encoding the information word. | 02-28-2013 |
20130080862 | SYSTEM AND METHOD FOR CORRECTING ERRORS IN DATA USING A COMPOUND CODE - Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data. | 03-28-2013 |
20130104007 | CYCLICALLY INTERLEAVED DUAL BCH, WITH SIMULTANEOUS DECODE AND PER-CODEWORD MAXIMUM LIKELIHOOD RECONCILIATION - A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255, 239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation. | 04-25-2013 |
20130139039 | Error-Correcting Code and Process for Fast Read-Error Correction - Subject matter, for example, disclosed herein relates to an embodiment of a process, system, device, or article involving error correction codes. In a particular embodiment, an error-correcting device may comprise an input port to receive an error correcting code (ECC) based, at least in part, on contents of a memory array; a nonlinear computing block to process the ECC to provide a plurality of signals representing a nonlinear portion of an error locator polynomial; and a linear computing block to process the ECC concurrently with processing the ECC to provide a plurality of signals representing the nonlinear portion of the error locator polynomial, to provide a plurality of signals representing a linear portion of the error locator polynomial. | 05-30-2013 |
20130232396 | APPARATUSES AND METHODS FOR ENCODING USING ERROR PROTECTION CODES - Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. | 09-05-2013 |
20130275839 | Programmable Error Correction Capability for BCH Codes - An embodiment of the invention relates to a BCH encoder formed with linear feedback shift registers (LFSRs) to form quotients and products of input polynomials with irreducible polynomials of a generator polynomial g(x) of the BCH encoder, with and without pre-multiplication by a factor x | 10-17-2013 |
20140053046 | CONFIGURABLE ENCODER FOR CYCLIC ERROR CORRECTION CODES - Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode. | 02-20-2014 |
20140068390 | HYBRID DECODING OF BCH CODES FOR NONVOLATILE MEMORIES - An apparatus and a method for correcting data errors in a data block. The data block contains original data which are supplemented by such a security syndrome that the data block effects a correction of at most t data errors, wherein a parallel-operating quick corrector is used. The quick corrector is only designed for a correction of a subset t | 03-06-2014 |
20140173386 | Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error - A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′ | 06-19-2014 |
20140195881 | BOSE-CHAUDHURI-HOCQUENGHEM (BCH) DECODER - A decoder for decoding a set of bits encoded using a Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC) includes a syndrome generator, a key equation solver, and an error bit locator. The syndrome generator receives the set of encoded bits and generates a set of syndromes. The key equation solver generates an error location polynomial based on the set of syndromes. The error bit locator generates an error match bit using the error location polynomial, and the error match bit is used to identify and correct errors in the set of encoded bits. | 07-10-2014 |
20140201604 | Methods and Systems For 2-Dimensional Forward Error Correction Coding - A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a plurality of rows and a plurality of columns. The plurality of rows include a row component code. The plurality of columns include a column component code. The row component code is configured to achieve a lower bit error rate than the column component code in communication channels having a same signal to noise ratio. | 07-17-2014 |
20140237325 | STAIRCASE FORWARD ERROR CORRECTION CODING - In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B | 08-21-2014 |
20140258815 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION/BROADCASTING SYSTEM - An apparatus and a method for performing shortening and puncturing in case of performing encoding and decoding using a parity test matrix in a communication/broadcasting system are provided. The method includes determining a number of zero-padding bits, determining a number N | 09-11-2014 |
20140325320 | SYNDROME TABLES FOR DECODING TURBO-PRODUCT CODES - A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes. | 10-30-2014 |
20140344651 | SYSTEM AND METHOD FOR VARYING MEMORY SIZE IN A DATA STREAM PROCESSING - The present disclosure relates to methods, systems, and computer-readable media for varying a memory size in a data stream processing while improving a connection degree sketch. Embodiments of the present disclosure may encode an input data by using an error coding technique to produce an encoded data, wherein the encoded data results in a modified memory size; generate a host connectivity using a set of parameters and applying a reverse sketching technique over the encoded data in order to obtain estimated encoded data; and decode the encoded data after the host connectivity is established using a decoding technique and obtaining an output data. The memory size of the output data may be proportional to the memory size of the input data. | 11-20-2014 |
20150039976 | Efficient Error Correction of Multi-Bit Errors - A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw | 02-05-2015 |
20150318869 | ENCODING AND SYNDROME COMPUTING CO-DESIGN CIRCUIT FOR BCH CODE AND METHOD FOR DECIDING THE SAME - An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of X | 11-05-2015 |
20150349804 | METHOD FOR ENCODING MULTI-MODE OF BCH CODES AND ENCODER THEREOF - A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix. | 12-03-2015 |
20160036464 | Multi-Code Chien's Search Circuit for BCH Codes with Various Values of m in GF(2m) - The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2 | 02-04-2016 |
20160087650 | BCH DECODING METHOD AND DECODER THEREOF - The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. Finally, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data. | 03-24-2016 |