# Code based on generator polynomial

## Subclass of:

## 714 - Error detection/correction and fault detection/recovery

## 714699000 - PULSE OR DATA ERROR HANDLING

## 714746000 - Digital data error correction

## 714752000 - Forward correction by block code

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

714784000 | Reed-Solomon code | 90 |

714785000 | Syndrome computed | 64 |

714782000 | Bose-Chaudhuri-Hocquenghem code | 48 |

714783000 | Golay code | 8 |

Entries | ||

Document | Title | Date |
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20100115380 | METHOD OF GENERATING CODEWORD IN WIRELESS COMMUNICATION SYSTEM - A method of generating a codeword for a control signal in a wireless communication system is provided. The method includes preparing a control signal and generating a codeword by applying a Reed-Muller (RM) extension matrix to the control signal. The RM extension matrix is generated by extending a RM basic matrix. A control signal can reliably be transmitted by the codeword with low complexity. | 05-06-2010 |

20150095747 | METHOD FOR DATA RECOVERY - A method for encoding multiple data symbols, the method may include receiving or calculating, by a computerized system, multiple (k) input data symbols; wherein the multiple input data symbols belong to a finite field F of order q; q being a positive integer that may exceed n; mapping the multiple input data symbols, by an injective mapping function, to a set of encoding polynomials; wherein the set of encoding polynomials comprises at least one encoding polynomial; and constructing a plurality (n) of encoded symbols that form multiple (t) recovery sets by evaluating the set of encoding polynomials at points of pairwise disjoint subsets (A | 04-02-2015 |

20150039975 | ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD - According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s | 02-05-2015 |

20130055050 | ERROR CORRECTION ENCODING APPARATUS, ERROR CORRECTION DECODING APPARATUS, NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM, AND PARITY CHECK MATRIX GENERATION METHOD - According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification. | 02-28-2013 |

20120192040 | ENCODING DEVICE FOR ERROR CORRECTION, ENCODING METHOD FOR ERROR CORRECTION AND ENCODING PROGRAM FOR ERROR CORRECTION - The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(x | 07-26-2012 |

20100251079 | METHOD AND DEVICE FOR INFORMATION BLOCK CODING AND SYNCHRONIZATION DETECTING - A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization. | 09-30-2010 |

20090187810 | ERROR CORRECTION CODING METHOD AND DEVICE - An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k | 07-23-2009 |

20090031196 | Error-correcting method used for decoding data transmissions - An error-correcting method used for decoding of data transmissions is disclosed. The error-correcting method is used for data with an error-correcting part and comprises: providing a multinomial for processing an error-correcting part to get an operational result; providing a database for saving the corresponding operational results of each single bit; and finding the error bit according to the operational results. | 01-29-2009 |

20100332955 | CHIEN SEARCH USING MULTIPLE BASIS REPRESENTATION - A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP. | 12-30-2010 |

20090119568 | Single CRC polynomial for both turbo code block CRC and transport block CRC - Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal. | 05-07-2009 |

20090031195 | Method and apparatus for encoding and decoding Reed-Muller codes - A method and apparatus for encoding and decoding Reed-Muller codes are provided. In exemplary embodiments, a method comprises receiving a code-word encoded with a Reed-Muller code, generating a pattern to retrieve voting bits, decoding the code-word based on the voting bits and, and providing the decoded code-word. | 01-29-2009 |

20110145683 | Instruction-set architecture for programmable cyclic redundancy check (CRC) computations - A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands. | 06-16-2011 |

20090132895 | ERROR CORRECTING CODES FOR RANK MODULATION - We investigate error-correcting codes for a novel storage technology, which we call the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by the different levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigates the problem of asymmetric errors. In this discussion, the properties of error correction in rank modulation codes are studied. We show that the adjacency graph of permutations is a subgraph of a multi-dimensional array of a special size, a property that enables code designs based on Lee-metric codes and L | 05-21-2009 |

20090106631 | PARALLEL CYCLIC CODE GENERATION DEVICE AND PARALLEL CYCLIC CODE ERROR DETECTION DEVICE - To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit | 04-23-2009 |

20100199153 | LOW-DENSITY PARITY CHECK CONVOLUTION CODE (LDPC-CC) ENCODER AND LDPC-CC DECODER - It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder ( | 08-05-2010 |

20100174969 | ERROR-LOCATOR-POLYNOMIAL GENERATION WITH ERASURE SUPPORT - A system and method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial. In an embodiment, a ECC decoding method, uses “erasure” data indicative of bits of data that are unable to be deciphered by a decoder. Such a method may use an Berlekamp-Massey algorithm that receives two polynomials as inputs; a first polynomial indicative of erasure location in the stream of bits and a syndrome polynomial indicative of all bits as initially determined. The Berlekamp-Massey algorithm may use the erasure identification information to more easily decipher the overall codeword when faced with a error-filled codeword. | 07-08-2010 |

20100174968 | HEIRARCHICAL ERASURE CODING - Arrangements are provided for efficient erasure coding of files to be distributed and later retrieved from a peer-to-peer network, where such files are broken up into many fragments and stored at peer systems. The arrangements further provide a routine to determine the probability that the file can be reconstructed. The arrangements further provide a method of performing the erasure coding in an optimized fashion, allowing fewer occurrences of disk seeks. | 07-08-2010 |

20130086456 | System and Method for Determining Quasi-Cyclic Low-Density Parity-Check Codes Having High Girth - A system and a method determine a quasi-cyclic (QC) low-density parity-check (LDPC) code corresponding to a protograph and having a predetermined girth. At least several elements of the connectivity matrix representing the protograph are duplicated along at least one line of duplication to produce an inflated connectivity matrix, wherein values of at least several elements in the connectivity matrix form a pattern indicated by the predetermined girth. A hierarchical quasi-cyclic (HQC) LDPC code corresponding to the inflated connectivity matrix is determined and at least several elements of a matrix representing the HQC LDPC code are removed, such that the matrix is squashed along the line of duplication to produce the QC LDPC code. | 04-04-2013 |

20130346833 | PROCESSING ELEMENTARY CHECK NODES OF AN ITERATIVE ED TRANSMITTER APPAR - Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed. | 12-26-2013 |

20110083062 | Method for Encoding and/or Decoding Multimensional and a System Comprising Such Method - The present discloses a method for detection and correction of errors, based on the proposition of multidimensional error correcting code, presenting the first example of implementation of MECC called BCHMD, that employ the BCH or BCH algebraic in each dimension of the set of symbols in the encoder and decoder sides of the communication system, in the error correcting code stage. Especially the described method claimed by the present invention embraces bits in different dimensions, which improves performance, speed and capacity in the ECC. | 04-07-2011 |

20100031125 | Tail-biting turbo coding to accommodate any information and/or interleaver block size - Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder. | 02-04-2010 |

20080288850 | METHOD AND APPARATUS FOR CODE BLOCK SEGMENTATION IN A MOBILE COMMUNICATION SYSTEM - A method for segmenting an information word into code blocks in a mobile communication system. The method includes setting a number C of code blocks to a minimum integer not less than a value obtained by dividing X by Z; when sizes K of all code blocks are determined to be equal when a length X of the information word is greater than a maximum length Z of each code block, determining a minimum integer value T not less than a value obtained by dividing a size of the information word by a number of code blocks, and determining, as K, a maximum value most approaching the value T among the values based on which a size of the code block can be set in units of eight bits; and generating a code block by inserting filler bits into a specific code block when a value obtained by multiplying K by C is greater than X. | 11-20-2008 |

20110072334 | SYSTEMATIC ENCODER WITH ARBITRARY PARITY POSITIONS - An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested. | 03-24-2011 |

20110004811 | Encoding/decoding apparatus and method - An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable node corresponding to a codeword symbol position. The protograph has a plurality of groups of nodes, each group of nodes comprising both variable nodes and check nodes. Each of the check nodes in a group is of degree 2 and has connections to two variable nodes in the same group. The protograph also has a plurality of check nodes of degree n, where n is the number of said plurality of groups, wherein each of the plurality of check nodes has a connection to a variable node in each group such that the symbol positions in a codeword are interleaved between the groups of nodes. | 01-06-2011 |

20100205511 | ENCODING METHOD, ENCODER, AND DECODER - A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3 | 08-12-2010 |

20120254702 | ERROR CORRECTION APPARATUS AND ERROR CORRECTION METHOD - A plurality error correction circuits connected with series includes a calculator circuit corrects the codeword when the determination results of a determining circuit indicate that the error correcting circuit at the present stage is to correct the codeword, and a determining circuit at a subsequent error correction apparatus determines whether the error correcting circuit at the subsequent stage is to correct the codeword when the determination results of the determining circuit indicate that the error correcting circuit at the present stage is not to correct the codeword. | 10-04-2012 |

20120185755 | METHOD FOR PERFORMING SOFT DECISION DECODING OF EUCLIDEAN SPACE REED-MULLER CODES - Soft decision decoding of a codeword of a Reed-Muller (RM) code by | 07-19-2012 |

20150067453 | MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G | 03-05-2015 |

20110320917 | METHOD OF DETERMINING A COORDINATE VALUE WITH RESPECT TO PATTERNS PRINTED ON A DOCUMENT - A method is disclosed of determining a coordinate value with respect to patterns printed on a document. Each pattern represents a sequence, with each sequence consisting of a repeating codeword of a cyclic position code. The pattern is sensed, and from each sensed pattern a respective sub-sequence of symbols is obtained. Each of the sub-sequences is then mapped to a respective mapped codeword of the cyclic position code. An offset between each mapped codeword and the codeword is determined, and a difference is derived between pairs of offsets. The coordinate value is derived by interpreting one of the differences as a marker separating the coordinate value from an adjacent coordinate value, and the remaining differences as digits of the coordinate value. | 12-29-2011 |

20100138725 | ERROR DETECTION DEVICE, ERROR CORRECTION/ERROR DETECTION DECODING DEVICE AND METHOD THEREOF - Error detection that detects an error in an input data sequence, the input data sequence created by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code and adding the error detection code to the data sequence so the remainder becomes ‘0’. Including calculating remainder values by dividing polynomials that correspond to each respective bit position by the generator polynomial and saving those remainder values; inputting together with an input data sequence, bit position information that indicates proper bit position of each data of the input data sequence, finding remainder values that correspond to proper bit positions of data of the input data sequence that are not ‘0’, performing bit-corresponding addition of each of the found remainder values; and determining no error in the input data sequence when all bits of the addition result become ‘0’. | 06-03-2010 |

20120102381 | SIMPLIFIED PARALLEL ADDRESS-GENERATION FOR INTERLEAVER - An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel. | 04-26-2012 |

20140317478 | CONFIGURABLE AND LOW POWER ENCODER FOR CYCLIC ERROR CORRECTION CODES - A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols. | 10-23-2014 |

20110219287 | REMOTE PRESENTATION OVER LOSSY TRANSPORT WITH FORWARD ERROR CORRECTION - In various embodiments, methods and systems are disclosed for integrating a remote presentation protocol with a datagram based transport. In one embodiment, an integrated protocol is configured to support lossless or reduced loss transport based on Retransmission (ARQ) combined with Forward Error Correction (FEC). The protocol involves encoding and decoding of data packets including feedback headers and FEC packets, continuous measurement of RTT, RTO and packet delay, dynamically evaluating loss probability to determine and adjust the ratio of FEC, congestion management based on dynamically detecting increase in packet delay, and fast data transmission rate ramp-up based on detecting a decrease in packet delay. | 09-08-2011 |

20130024751 | FLASH MEMORY CONTROLLER AND DATA READING METHOD - A data reading method is provided. The data reading method includes: utilizing a first sense voltage to read a data unit from a flash memory block; performing an error detection operation on the data unit and calculating an error polynomial according to a detection result; and determining whether the error polynomial conforms to a predetermined condition and deciding whether to perform read retry on the data unit according to a determining result. | 01-24-2013 |

20100299579 | Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration - Convolutional coders having an n-state with n≧2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also provided. A convolutional coder generates a sequence of coded n-state symbols. A content of a starting position of an LFSR in a decoder is determined when sufficient error free coded symbols are available. Up to k symbols in error are corrected. A systematic convolutional coder and decoder are also provided. | 11-25-2010 |

20080270872 | Apparatus and method for encoding low density parity check codes in a communication system - A Low Density Parity Check (LDPC) code encoding apparatus for a communication system is provided. The encoding apparatus receives information bits, and generates an LDPC code by encoding the information bits using an interleaving scheme. The interleaving scheme is generated such that when the LDPC code is punctured, there is no short-length cycle in a Tanner graph of the punctured LDPC code. | 10-30-2008 |

20100169747 | OPTIMUM DISTANCE SPECTRUM FEEDFORWARD LOW RATE TAIL-BITING CONVOLUTIONAL CODES - Method and apparatus for generating a set of generator polynomials for use as a tail biting convolutional code to operate on data transmitted over a channel comprises: (0) specifying a constraint and a low code rate for a tail biting convolutional code, where the low rate code is lower than 1/n (n being an integer greater than 4); (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code of the low rate code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a circuit(s) of a data transceiver to implement the optimum code(s). | 07-01-2010 |

20090019342 | Determining a Message Residue - A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory. | 01-15-2009 |

20130254635 | Chien Search Using Multiple Basis Representation - A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP. | 09-26-2013 |

20100287451 | Incremental generation of polynomials for decoding reed-solomon codes - An error locator polynomial is incrementally generated by flipping a bit pattern Y | 11-11-2010 |

20120290901 | MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY CONTROLLER - A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector. | 11-15-2012 |

20140032997 | QPP INTERLEAVER/DE-INTERLEAVER FOR TURBO CODES - A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: | 01-30-2014 |

20130031446 | CODING DEVICE, ERROR-CORRECTION CODE CONFIGURATION METHOD, AND PROGRAM THEREOF - A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix. | 01-31-2013 |

20130073928 | POWER-OPTIMIZED DECODING OF LINEAR CODES - A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word. | 03-21-2013 |

20140108895 | ERROR CORRECTION CODE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value. | 04-17-2014 |

20140059409 | SYSTEM AND METHOD HAVING OPTIMAL, SYSTEMATIC q-Ary CODES FOR CORRECTING ALL ASYMMETRIC AND SYMMETRIC ERRORS OF LIMITED MAGNITUDE - A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided. | 02-27-2014 |

20140237324 | CHANNEL CODING METHOD OF VARIABLE LENGTH INFORMATION USING BLOCK CODE - A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance. | 08-21-2014 |

20100306627 | RECEIVING APPARATUS, RECEIVING METHOD, PROGRAM, AND RECEIVING SYSTEM - Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence. | 12-02-2010 |