# Using symbol reliability information (e.g., soft decision)

## Subclass of:

## 714 - Error detection/correction and fault detection/recovery

## 714699000 - PULSE OR DATA ERROR HANDLING

## 714746000 - Digital data error correction

## 714752000 - Forward correction by block code

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

714780000 | Using symbol reliability information (e.g., soft decision) | 70 |

20100058149 | DECODER OF ERROR CORRECTION CODES - In a method of decoding data symbols into codewords, reliability information of the data symbols is provided. A first group of symbols from a first set of groups of symbols is selected, wherein the first set of groups of symbols is defined by at least a first parity-check of a parity-check matrix of a linear block code which has been used to encode the data symbols. The selection is based on the reliability information. A second group of symbols from a second set of groups of symbols is selected, wherein the second set of groups of symbols is defined by at least a second parity-check of the parity-check matrix. The selection is based on the selected first group of symbols and the reliability information. At least a part of the codeword is composed on the basis of the first group of symbols and the second group of symbols. | 03-04-2010 |

20130117640 | Soft Information Generation for Memory Systems - Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition. | 05-09-2013 |

20100042905 | ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder. | 02-18-2010 |

20100042904 | BREAKING UNKNOWN TRAPPING SETS USING A DATABASE OF KNOWN TRAPPING SETS - In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values. | 02-18-2010 |

20100042903 | RECONFIGURABLE ADDER - In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums. | 02-18-2010 |

20100042902 | ERROR-FLOOR MITIGATION OF ERROR-CORRECTION CODES BY CHANGING THE DECODER ALPHABET - In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased. | 02-18-2010 |

20100042906 | ADJUSTING SOFT-OUTPUT VALUES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword. | 02-18-2010 |

20090158128 | DECODING DEVICE, DECODING METHOD, RECEIVING DEVICE, AND STORAGE MEDIUM REPRODUCING DEVICE - A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media. | 06-18-2009 |

20090158127 | DECODING APPARATUS AND DECODING METHOD - Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding. | 06-18-2009 |

20090307565 | METHOD AND APPARATUS FOR FAST ENCODING OF DATA SYMBOLS ACCORDING TO HALF-WEIGHT CODES - Efficient methods for encoding and decoding Half-Weight codes are disclosed and similar high density codes are disclosed. The efficient methods require at most 3·(k−1)+h/2+1 XORs of symbols to calculate h Half-Weight symbols from k source symbols, where h is of the order of log(k). | 12-10-2009 |

20130067297 | Systems and Methods for Non-Binary Decoding Biasing Control - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols. | 03-14-2013 |

20140068389 | OPTIMIZED SCHEME AND ARCHITECTURE OF HARD DRIVE QUEUE DESIGN - Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword. | 03-06-2014 |

20100077282 | True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations - True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis. | 03-25-2010 |

20100223534 | Code Block Reordering Prior to Forward Error Correction Decoding Based On Predicted Code Block Reliability - Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code. | 09-02-2010 |

20100169745 | SOFT OUTPUT DECODER, ITERATIVE DECODER, AND SOFT DECISION VALUE CALCULATING METHOD - A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder ( | 07-01-2010 |

20100083075 | Methods and Apparatus for Selective Data Retention Decoding in a Hard Disk Drive - Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment. | 04-01-2010 |

20090222711 | Generalized Multi-Threshold Decoder for Low-Density Parity Check Codes - Methods, apparatus, and systems are provided for error correction of a communication signal. A generalized multiple threshold scheme for iteratively decoding a received codeword may include generating a bit reliability based on a channel output reliability and an updated bit reliability from a previous decoding iteration, where the bit reliability is updated using a scaling factor and a comparison with a threshold. The threshold may have a plurality of threshold values during the iterative decoding. | 09-03-2009 |

20100088578 | Parity Bit Soft Estimation Method and Apparatus - The systematic and parity bits of a symbol are tightly coupled to each other based on the way in which the symbol is encoded. The relationship between the systematic and parity bits can be exploited to improve the accuracy of soft bit estimation for both the systematic bits and parity bits. In one embodiment, a received symbol is processed by demodulating the received symbol to determine an initial soft estimate of each systematic bit and corresponding one or more parity bits in the sequence. The systematic bit sequence is iteratively decoded to revise the soft estimate of the systematic bit. The initial soft estimate of the one or more parity bits associated with each systematic bit is revised based on the revised soft estimate of each systematic bit. The received symbol can be decoded or regenerated based on the revised soft estimate of each systematic bit and corresponding one or more parity bits. | 04-08-2010 |

20090254796 | Techniques for correcting errors and erasures using a single-shot generalized minimum distance key equation solver - A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations. | 10-08-2009 |

20090282319 | HIERARCHICAL DECODING APPARATUS - A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination. | 11-12-2009 |

20090292975 | METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING - Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information. | 11-26-2009 |

20100146372 | DECODING OF SERIAL CONCATENATED CODES USING ERASURE PATTERNS - A method of processing a received concatenated code codeword is disclosed, the concatenated code codeword comprising a plurality of inner code codewords and one or more outer code codewords, each inner code codeword comprising symbols, from each outer code codeword comprising one or more information symbols and one or more parity symbols, the parity symbols in each outer code codeword corresponding to the parity check equations of the outer code. The method comprises (i) decoding the received concatenated code codeword; (ii) erasing a subset of the received inner code codewords; and (iii) determining a replacement inner code codeword to replace each of the erased inner code codewords to provide a candidate concatenated code codeword. A preferred method further comprises (iv) erasing a further, different subset of the received inner code codewords; (v) determining further replacement inner code codewords to replace each of the thus erased inner code codewords to provide a further candidate concatenated code codeword; and (vi) determining the candidate concatenated code codeword having the highest correlation with the received vector of the decoded concatenated code codeword. A system for performing the method is also disclosed. | 06-10-2010 |

20120079355 | OPPORTUNISTIC DECODING IN MEMORY SYSTEMS - Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence. | 03-29-2012 |

20090094505 | HIGH SPEED TURBO CODES DECODER FOR 3G USING PIPELINED SISO LOG-MAP DECODERS ARCHITECTURE - A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing baseband signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3 | 04-09-2009 |

20090249170 | Decoding Method - A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of FEC encoded bits are decoded by using the quality level of bits to perform soft-decision convolution decoding on the stream of units of FEC bits, where the soft-decision convolution decoding produces, for block decoding, a stream of symbols made up of bits. Subsequences of units that are prone to erroneous soft-decision convolution decoding are detected by determining, for the sub-sequences whether the distribution of quality bits indicate the units are below a threshold level of correctness, and by comparing characteristics of that distribution to a given set of characteristics predetermined to be prone to result in incorrect decoding. | 10-01-2009 |

20080313526 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN A MOBILE COMMUNICATION SYSTEM - An apparatus and method for transmitting and receiving symbols in a mobile communication system, in which a multiplexer and burst mapper divides each of first and second group data blocks into a plurality of sub-blocks, the symbols including the first group data block and the second group data block, the second group data block having a different priority level from the first group data block, and maps a combination of one of the first group data sub-blocks and one of the second group data sub-blocks to each burst. A modulator maps a bit of the first group data sub-block and a bit of the second group data sub-block to a symbol according to a bit reliability pattern of modulation symbols in each burst. | 12-18-2008 |

20100185923 | DECODING OF RECURSIVE CONVOLUTIONAL CODES BY MEANS OF A DECODER FOR NON-RECURSIVE CONVOLUTIONAL CODES - Embodiments of the invention provide a decoder arrangement ( | 07-22-2010 |

20100162086 | SOFT DECISION DEVICE AND SOFT DECISION METHOD - A soft decision device and method for obtaining a soft decision value as a value expressing a probability as near the actual probability as possible by simple processing. The soft decision device and method are used to output a soft decision value for each bit of each symbol used for decoding the each symbol as a value corresponding to the function value obtained by applying a predetermined function for each bit to the sampled value of the each symbol according to the demodulated signal such that the probability distribution of the sampled value in each symbol point is the Gauss distribution. The function for each bit is approximated to a curve expressing the probability that each bit is 1 or 0 for the sampled value of each symbol of the demodulated signal and defined by using a quadratic function. | 06-24-2010 |

20100146371 | Modified Turbo-Decoding Message-Passing Algorithm for Low-Density Parity Check Codes - Apparatus and methods arc provided to decode signals from a communication channel to reconstruct transmitted information. Embodiments may include applying a plurality of decoders to a code, in which reliability values are provided to a decoder such that the decoder receives the reliability values determined by and provided from only one other decoder of the plurality of decoders. A valid codeword may be output from application of the plurality of decoders to the code. | 06-10-2010 |

20090222710 | SELECTIVELY APPLIED HYBRID MIN-SUM APPROXIMATION FOR CONSTRAINT NODE UPDATES OF LDPC DECODERS - In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation). | 09-03-2009 |

20080288849 | Apparatus for generating soft decision values and method thereof - According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value. | 11-20-2008 |

20110119566 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 05-19-2011 |

20090106630 | ITERATIVE DECODING IN A MESH NETWORK, CORRESPONDING METHOD AND SYSTEM - In the field of coding/decoding in telecommunications networks, an error correcting decoder and associated decoding method are adapted to a mesh network. | 04-23-2009 |

20090037795 | Denoising and Error Correction for Finite Input, General Output Channel - Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser. | 02-05-2009 |

20130132804 | Systems, Methods and Devices for Decoding Codewords Having Multiple Parity Segments - An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module. | 05-23-2013 |

20100332954 | Systems and Methods for Out of Order Y-Sample Memory Management - Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations. | 12-30-2010 |

20110041041 | COOPERATIVE SYMBOL LEVEL NETWORK CODING IN MULTI-CHANNEL WIRELESS NETWORKS - Disclosed is a new solution to maximize throughput in wireless networks even when unpredictable and time-varying error exist. The present invention adapts to take an advantage of a network coding at a symbol level in multi-channel wireless networks. By operating the network coding at the symbol level and using soft decision values, the present invention is able to exploit both time and cooperative diversity in realistic multi-channel wireless networks, to adapt to time-varying and bursty channel errors, and to efficiently collect as many correct symbols as possible at the receiver. | 02-17-2011 |

20080270871 | ERROR CORRECTION PROCESS AND MECHANISM - Performing soft error correction includes receiving a word at a soft correction engine ( | 10-30-2008 |

20110179339 | Method and Apparatus for Received Signal Processing in a Wireless Communication Receiver - According to one aspect of the teachings presented in this document, a wireless communication receiver implements a form of joint detection that is referred to as “fast joint detection” (FJD). A receiver that is specially adapted to carry out FJD processing provides an advantageous approach to joint detection processing wherein the number of computations needed to produce reliable soft bits, for subsequent turbo decoding and/or other processing, is significantly reduced. Further, the algorithms used in the implementation of FJD processing are particularly well suited for parallelization in dedicated signal processing hardware. Thus, while FJD processing is well implemented via programmable digital processors, it also suits applications where high-speed, dedicated signal processing hardware is needed or desired. | 07-21-2011 |

20100287450 | OPTICAL RECEIVING APPARATUS AND OPTICAL RECEIVING METHOD - An optical receiving apparatus includes: an A/D converting circuit; a received-signal demodulating circuit that demodulates a received digital signal from the A/D converting circuit into an m-bit received signal; a soft-decision-data generating circuit that generates n-bit (n≦m) soft-decision data based on the m-bit received signal; and an error correcting circuit that performs error correction based on the n-bit soft-decision data and outputs an error-corrected received signal. The soft-decision-data generating circuit generates soft-decision data of n bits (n=p+1) that corresponds to a determination result according to 2 | 11-11-2010 |

20110138258 | ENCODING DEVICE AND DECODING DEVICE - An encoding device and decoding device for improving an error floor while taking advantage of the features of a convolutional code capable of encoding/decoding an information sequence with an arbitrary length are disclosed. An error correction encoding section ( | 06-09-2011 |

20090132894 | Soft Output Bit Threshold Error Correction - A communications channel is provided that includes an encoder that receives user data and generates corresponding encoded symbols for transmission through a channel medium. A channel detector has an input coupled to receive an output signal from the channel medium and a reliability information output which produces reliability information regarding logic states of detected bits in the output signal. A binary reliability value is provide for each of the detected bits. The channel further includes a decoder having a reliability information input coupled to the reliability information output of the channel detector to generate corresponding user data words as a function of the binary reliability value. | 05-21-2009 |

20120005560 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful. | 01-05-2012 |

20110087951 | Detector for Multi-Level Modulated Signal and Detection Method Using the Same, and Iterative Receiver for Multi-Level Modulated Signal and Iteratively Receiving Method Using the Same - Provided are a detector for a multi-level modulated signal and a detection method using the same, and an iterative receiver for a multi-level modulated signal and an iteratively receiving method using the same. The detector includes: a channel estimator estimating a channel response of each of a plurality of bits included in at least one received signal based on multi-level modulation; a hard decision unit, for each bit, selecting at least one of a plurality of bits remaining by excluding the bit and performing a hard decision based on a pre-probability of the selected bit; and a reliability calculator calculating reliability of each of all the bits in the received signal based on the received signal from which the hard-decided bit component is cancelled and the estimated channel response. Accordingly, the computation amount according to detection can be reduced without the degradation of performance. | 04-14-2011 |

20120233526 | GENERATION OF SOFT BIT METRICS FOR DIFFERENTIALLY ENCODED QUADRATURE PHASE SHIFT KEYING (QPSK) - A computer implemented method for generating soft bit metric information of telecommunications systems employing differential encoding of data. | 09-13-2012 |

20140013190 | Iterative Decoding Device and Related Decoding Method - An iterative decoding device includes a decoder, a dual mode determination unit and a dual mode scaling unit. The decoder is utilized for receiving a set of soft information (SI) and iteratively decoding the set of SI and updating the set of SI accordingly to generate a set of updated SI. The dual mode determination unit is coupled to the decoder for generating a determination result according to the set of updated SI. The dual mode scaling unit is coupled to the dual mode determination unit and the decoder for scaling the set of updated SI according to the determination result to generate a set of scaled SI acting as an input of the decoder for next iteration. | 01-09-2014 |

20110131475 | METHOD FOR DETERMINING A COPY TO BE DECODED AND AN ASSOCIATED ERASURES VECTOR, CORRESPONDING STORAGE MEANS AND RECEIVER DEVICE - A method is proposed for determining an erasures vector associated with a data block to be decoded built out of received copies, and using levels of reliability of transmission associated with symbols contained in different copies of a same block of received pieces of data. | 06-02-2011 |

20110004810 | Method and System of Receiving Data with Enhanced Error Correction - A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s). | 01-06-2011 |

20110185264 | LDPC DECODING WITH ON THE FLY ERROR RECOVERY - It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder. | 07-28-2011 |

20090044080 | Closed Galois Field Combination - A method is provided for combining two or more input sequences in a communications system to increase a repetition period of the input sequences in a resource-efficient manner. The method includes a receiving step, a mapping step, and a generating step. The receiving step involves receiving a first number sequence and a second number sequence, each expressed in a Galois field GF[p | 02-12-2009 |

20120317462 | METHOD FOR CONTROLLING MESSAGE-PASSING ALGORITHM BASED DECODING OPERATION BY REFERRING TO STATISTICS DATA OF SYNDROMES OF EXECUTED ITERATIONS AND RELATED CONTROL APPARATUS THEREOF - A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data. | 12-13-2012 |

20100235718 | Decoding Techniques for Correcting Errors Using Soft Information - Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected. | 09-16-2010 |

20090172500 | APPLICATION OF A META-VITERBI ALGORITHM FOR COMMUNICATION SYSTEMS WITHOUT INTERSYMBOL INTERFERENCE - Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2 | 07-02-2009 |

20110320916 | METHOD OF LIST DECODING AND RELATIVE DECODER FOR LDPC CODES - A method is for generating, for each check node related to a parity check equation of a LDPC code, signals representing a first output table of corrected values of symbols of a word received through a communication channel and transmitted according to the LDPC code, and signals representing a second output table of the logarithm of the ratio between the respective probability of correctness of the values of same coordinates in the first output table and their corresponding maximum probability of correctness. The method is implemented by processing the components of a first input table of values of a Galois Field of symbols that may have been transmitted and of a second input table of corresponding probability of correctness of each value. | 12-29-2011 |

20140089767 | METHOD AND SYSTEM FOR GENERATION OF A TIE-BREAKING METRIC IN A LOW-DENSITY PARITY CHECK DATA ENCODING SYSTEM - The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol. | 03-27-2014 |

20080250300 | METHOD FOR DECODING DATA IN NON-VOLATILE STORAGE USING RELIABILITY METRICS BASED ON MULTIPLE READS - Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs. | 10-09-2008 |

20110010609 | System and Method for Achieving Higher Data Rates in Physical Layer Devices - A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse. | 01-13-2011 |

20110035647 | Broadband satellite system for the simultaneous reception of multiple channels using shared iterative decoder - Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output. | 02-10-2011 |

20130318422 | READ LEVEL ADJUSTMENT USING SOFT INFORMATION - A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level offset based on the error signal, and adjusting a read level in the flash memory by the determined read level offset. | 11-28-2013 |

20130198591 | Method and Apparatus for Soft Information Transfer between Constituent Processor Circuits in a Soft-Value Processing Apparatus - In one or more aspects, the present invention improves the efficiency of soft information transfer within a soft-value processing apparatus, by reducing in some sense the “amount” of soft information transferred between constituent processor circuits within the apparatus, without forfeiting or otherwise compromising the transfer of “valuable” soft information. In one example, the soft values produced by a constituent processor circuit are identified as being reliable or unreliable according to a reliability threshold. Some or all of the unreliable values are omitted from a soft value information transfer to another constituent processor circuit, or they are quantized for such transfer. The reduction in memory requirements for soft information transfer advantageously allows the use of lower power, less complex, and less expensive circuitry than would otherwise be required in the apparatus, which may be, as a non-limiting example, a Turbo receiver in a wireless communication device. | 08-01-2013 |

20100185924 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 07-22-2010 |

20100169746 | LOW-COMPLEXITY SOFT-DECISION DECODING OF ERROR-CORRECTION CODES - A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors. | 07-01-2010 |

20100153824 | SOFT-ERROR DETECTION FOR ELECTRONIC-CIRCUIT REGISTERS - In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low. | 06-17-2010 |

20110055667 | EFFICIENT SOFT VALUE GENERATION FOR CODED BITS IN A TURBO DECODER - Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums. | 03-03-2011 |

20140032996 | DECODING APPARATUS, STORAGE APPARATUS, AND DECODING METHOD - According to at least one embodiment, a decoding apparatus includes an error correcting module and a change module. The error correcting module decodes for correcting error of encoded data using a low-density party check code and likelihood information. The change module changes a value of the likelihood information if the value of the likelihood information is continuously smaller than a predetermined value. | 01-30-2014 |

20130326314 | NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD USING HARD AND SOFT DECISION DECODING - A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data. | 12-05-2013 |

20090006930 | Techniques For Generating Bit Reliability Information In The Post Processor - A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values. | 01-01-2009 |

20140173385 | Low Density Parity Check Decoder With Dynamic Scaling - A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder. | 06-19-2014 |

20130139038 | ERROR CORRECTING DECODING DEVICE AND ERROR CORRECTING DECODING METHOD - The error correcting decoding device of the present invention performs Low-Density Parity-Check (LDPC) decoding which accommodates a plurality of code rates while sharing circuits to suppress increase in circuit scale. If the set code rate is a second code rate which is a higher code rate than a first code rate, a column processing and row processing calculating unit ( | 05-30-2013 |

20110276861 | DEVICE, SYSTEM AND METHOD OF DECODING WIRELESS TRANSMISSIONS - Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed. | 11-10-2011 |