Class / Patent application number | Description | Number of patent applications / Date published |
714767000 | Code word for plural n-bit (n>1) storage units (e.g., x4 DRAM's) | 17 |
20090049365 | SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM - A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers. | 02-19-2009 |
20110107183 | INTERLEAVING SCHEME FOR AN LDPC CODED 16 APSK SYSTEM - An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use. | 05-05-2011 |
20110231735 | STACKED SEMICONDUCTOR MEMORY DEVICE AND RELATED ERROR-CORRECTION METHOD - A stacked semiconductor memory device comprises an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word. | 09-22-2011 |
20110239091 | MEMORY SYSTEM AND METHOD OF DATA WRITING AND READING IN MEMORY SYSTEMS - A memory system according to the embodiment comprises a p-adic number converter unit operative to convert δ-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D. | 09-29-2011 |
20120079352 | HIGH-SPEED MEMORY SYSTEM - The disclosed embodiments relate to a Flash-based memory module having high-speed serial communication. The Flash-based memory module comprises, among other things, a plurality of I/O modules, each configured to communicate with an external device over one or more external communication links, a plurality of Flash-based memory cards, each comprising a plurality of Flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the Flash-based memory cards and configured to allow each one of the I/O modules to communicate with the respective one of the Flash-based memory cards. Each I/O module is connected to each crossbar switching element by a high-speed serial communication link, and each crossbar switching element is connected to the respective one of the Flash-based memory cards by a plurality of parallel communication links. | 03-29-2012 |
20120159285 | STORAGE DRIVE WITH LDPC CODING - For storage drives with LDPC encoded data, read techniques are provided whereby an errantly read memory unit (e.g., faulty LDPC codeword) may be recovered. | 06-21-2012 |
20130346830 | ANTIPODAL-MAPPING-BASED ENCODERS AND DECODERS - Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements. | 12-26-2013 |
20140223261 | UNEQUAL BIT RELIABILITY INFORMATION STORAGE METHOD FOR COMMUNICATION AND STORAGE SYSTEMS - An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance | 08-07-2014 |
20140289587 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 09-25-2014 |
20140317472 | ENCODER, DECODER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided is a semiconductor device configured to encode input data into a codeword including M different symbols, each of which includes N | 10-23-2014 |
20140325315 | MEMORY MODULE BUFFER DATA STORAGE - A memory module ( | 10-30-2014 |
20150089326 | ADDRESS DETECTION CIRCUIT AND MEMORY INCLUDING THE SAME - An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units. | 03-26-2015 |
20150106677 | HANDLING ERRORS IN TERNARY CONTENT ADDRESSABLE MEMORIES - Receive a request to write a unit of data, having a first half of bits and a second half of bits, to an index of a ternary content addressable memory (TCAM). Generate a first error-correcting code (ECC) codeword for first bits of the first half of bits of the unit of data and first bits of the second half of bits of the unit of data. Generate a second error-correcting code (ECC) codeword for second bits of the first half of bits of the unit of data and second bits of the second half of bits of the unit of data. Store the first half of bits of the unit of data in the first row of the index. Store the second half of bits of the unit of data in the second row of the index. | 04-16-2015 |
20150143197 | Codes for Enhancing the Repeated Use of Flash Memory - A basic property of flash memory is that: a 0-bit can be changed into a 1-bit, but not vice-versa, which severely limits the possibilities of reusing storage space with new data. A family of new coding methods is presented that enables double use of the memory, effectively expanding the combined amount of stored data. This can then be used as a compression booster, adding an additional layer to, and improving the compression of some rewriting methods that are not context sensitive. | 05-21-2015 |
20150363260 | DATA BUS INVERSION USABLE IN A MEMORY SYSTEM - Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state. | 12-17-2015 |
20160170830 | MESSAGE STORAGE IN MEMORY BLOCKS USING CODEWORDS | 06-16-2016 |
20160203044 | SEMICONDUCOTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME | 07-14-2016 |