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Memory access

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714746000 - Digital data error correction

714752000 - Forward correction by block code

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714773000 Solid state memory 201
714764000 Error correct and restore 66
714769000 Dynamic data storage 60
714768000 Error correction code for memory address 35
714766000 Check bits stored in separate area of memory 27
714767000 Code word for plural n-bit (n>1) storage units (e.g., x4 DRAM's) 6
714765000 Error pointer 5
20090113272ERROR CORRECTION CODING IN FLASH MEMORY DEVICES - Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to ‘1’ state) and can be disabled by programming the indicator bit (e.g., bit set to a ‘0’ state).04-30-2009
20090292974METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING - Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.11-26-2009
20090164872PREDICTION AND PREVENTION OF UNCORRECTABLE MEMORY ERRORS - A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.06-25-2009
20080301529APPARATUS AND METHOD FOR DISTINGUISHING SINGLE BIT ERRORS IN MEMORY MODULES - An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.12-04-2008
20080301530APPARATUS AND METHOD FOR DISTINGUISHING TEMPORARY AND PERMANENT ERRORS IN MEMORY MODULES - An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.12-04-2008
714772000 Code word parallel access 2
20110179338LOSSY CODING OF SIGNALS - A method is described for packing variable-length entropy coded data into a fixed rate data stream along with resolution enhancement data, the method providing tightly constrained propagation of transmission channel errors and graceful degradation of signal resolution as entropy-coded data rate increases. An application to a multiband ADPCM audio codec is also described.07-21-2011
20120030544Accessing Memory for Data Decoding - A method comprises receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements. The method also comprises identifying each of the unique memory addresses as being included in one group of a plurality of address groups. Each address group substantially includes an equivalent number of unique addresses. The method also comprises, in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.02-02-2012
Entries
DocumentTitleDate
20110185259OVERWRITABLE NONVOLATILE MEMORY DEVICE AND RELATED DATA WRITE METHOD - A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region.07-28-2011
20130031442Multi-Dimensional Error Definition, Error Measurement, Error Analysis, Error Function Generation, Error Information Optimization, and Error Correction for Communications Systems - The present invention is related to multi-dimensional error definition, error measurement, error analysis, error function generation, error information optimization, and error correction for communication systems. Novel techniques are provided that can be applied to a myriad of applications for which an input to output transfer characteristic must be corrected or linearized. According to embodiments of the present invention, error can be described, processed, and geometrically interpreted. Compact formulations of error correction and calibration functions can be generated according to the present invention, which reduce memory requirements as well as computational time.01-31-2013
20090070655Method for Generating an ECC Code for a Memory Device - A method for generating an ECC for a flash memory device is provided. The flash memory device only supports flash memories with low-level ECC technology, such as SLC (single-level cell) flash memories. By using a controller with an ECC engine, the flash memory device can directly generate a correct ECC for itself when it reads data from flash memories with high-level ECC technology, such as MLC (multi-layer cell) flash memories. Thus the flash memory device can also support flash memories with high-level ECC technology and reduce the time of reading data.03-12-2009
20110191653QUASI-CYCLIC LDPC ENCODING AND DECODING FOR NON-INTEGER MULTIPLES OF CIRCULANT SIZE - In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data.08-04-2011
20090193316MEMORY SUBSYSTEMS WITH FAULT ISOLATION - An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of the data groupings in the lower 72 bits of each memory expander. A second memory module receives all of the data groupings in the upper 72 bits of each memory expander. A failure in any one or more bytes in an ECC word indicate failures in the computer memory system.07-30-2009
20130086452Sending a zero information gain formatted encoded data slice - A method begins by a dispersed storage (DS) processing module determining whether to send an encoded data slice of set of encoded data slices in accordance with a zero information gain (ZIG) format. When the encoded data slice is to be sent in accordance with the ZIG format, the method continues with the DS processing module selecting a partial encoding threshold number of encoded data slices of the set of encoded data slices, wherein the partial encoding threshold number of encoded data slices does not include the encoded data slice and generating a set of ZIG encoded data slices based on a ZIG function and the partial encoding threshold number of encoded data slices, wherein the set of ZIG encoded data slices represents recovery information of the encoded data slice. The method continues with the DS processing module outputting the set of ZIG encoded data slices.04-04-2013
20110202817NODE INFORMATION STORAGE METHOD AND SYSTEM FOR A LOW-DENSITY PARITY-CHECK DECODER - A receiver to receive a signal associated with a low-density parity-check (LDPC) code. The receiver includes a memory device, an address generator, and an LDPC decoder. The LDPC decoder includes a row designator and a position designator. The memory device stores data related to an LDPC decoding process. The address generator generates an access address to the stored data. The LDPC decoder performs the LDPC decoding process. The row designator designates a row from a parity-check matrix as a parent row and designates a plurality of corresponding rows from the parity-check matrix as child rows. The position designator designates an original position order of each parent non-zero element of 10 the parent row according to an actual position order of each parent non-zero element in the parent row. The actual position order includes a numerical order of the parent non-zero elements.08-18-2011
20120246543APPARATUS AND METHOD FOR FAST TAG HIT - A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by comparing the hamming distance against a threshold.09-27-2012
20100115377METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS - A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.05-06-2010
20100115376AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES - A method for storing data in a memory (05-06-2010
20130086451Reproducing data utilizing a zero information gain function - A method begins by a dispersed storage (DS) processing module receiving a zero information gain (ZIG) encoded data slice and a subset of encoded data slices of a set of encoded data slices. The method continues with the DS processing module generating a set of ZIG encoded data slices using a ZIG function and corresponding ones of the subset of encoded data slices, wherein the set of ZIG encoded data slices represents additional components of recovery information of a first encoded data slice. The method continues with the DS processing module recreating the first encoded data slice from the ZIG encoded data slice and the set of ZIG encoded data slices. The method continues with the DS processing module decoding the subset of encoded data slices and the first encoded data slice using a dispersed storage error coding function to reproduce data.04-04-2013
20130086449Sharing a Check Bit Memory Device Between Groups of Memory Devices - A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.04-04-2013
20130086450Encoding data utilizing a zero information gain function - A method begins by a dispersed storage (DS) processing module encoding data using a dispersed storage error coding function to produce a set of encoded data slices. The method continues with the DS processing module encoding a first encoded data slice of the set of encoded data slices using a zero information gain (ZIG) function based on a second encoded data slice of the set of encoded data slices to produce a ZIG encoded data slice. The method continues with the DS processing module outputting the ZIG encoded data slice and a subset of encoded data slices of the set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices and does not include the first or the second encoded data slice.04-04-2013
20130086447UPDATING DATA STORED IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module receiving a modified data object, wherein the modified data object is a modified version of a data object and the data object is divided into a plurality of data segments and stored in the DSN. The method continues with the DS processing module mapping portions of the modified data object to the plurality of data segments that includes creating a middle data segment of a second plurality of data segments based on a corresponding middle data segment of the plurality of data segments when the a portion of the portions corresponds to middle data of the modified data object. The method continues with the DS processing module encoding the middle data segment using a dispersed storage error coding function to produce an encoded data segment and overwriting the corresponding middle data segment with the encoded data segment in the DSN.04-04-2013
20130086448ACCESSING LARGE AMOUNTS OF DATA IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module obtaining a plurality of data objects for storage in a dispersed storage network (DSN) and determining one or more common data object aspects of a data object of the plurality of data objects. The method continues with the DS processing module disperse storage error encoding at least a portion of the data object to produce a set of encoded data slices and generating a set of DSN addresses for the set of encoded data slices, wherein each of the set of DSN addresses includes a field referencing the one or more common data object aspects. The method continues with the DS processing module outputting the set of encoded data slices for storage in the DSN based on the set of DSN addresses.04-04-2013
20120266046APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL SOLID-STATE STORAGE AS SINGLE-LEVEL CELL SOLID-STATE STORAGE - An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.10-18-2012
20130036339MEMORY DEVICE - According to the embodiments, a memory device includes a memory to which data is written using memory cells as a write unit and a controller which controls the memory. In response to a request to write data with a logical address to the memory from a host device, the controller requests the host device to transmit a segment of the write data with a size specified by the controller. The controller writes the write data with additional data to the memory. The write-data segment has a size determined to allow the combined size of the write-data segment and corresponding additional data to be the largest while smaller than the size of the write unit or has a multiple integral of the size.02-07-2013
20090187809INTEGRATED CIRCUIT INCLUDING AN ECC ERROR COUNTER - An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether the first signal is valid and a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.07-23-2009
20100042899DEINTERLEAVER - A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.02-18-2010
20090158123ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY - Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level06-18-2009
20090158122FORWARD ERROR CORRECTION OF AN ERROR ACKNOWLEDGEMENT COMMAND PROTOCOL - Embodiments of the invention are generally directed to systems, methods, and apparatuses for the forward error correction coding of an error acknowledgement command protocol. In some embodiments, a host sends commands to a memory device and monitors an error signal to determine whether the memory device received the commands without error. In some embodiments, if the host detects an error then it provides forward error correction code for an error acknowledge command. Other embodiments are described and claimed.06-18-2009
20100332944FACILITATING ERROR DETECTION AND CORRECTION AFTER A MEMORY COMPONENT FAILURE - Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C-2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed. If the failed memory component contains a data-bit column for the block of data, the system uses checkbits from the two checkbit columns to correct the data-bit column, and then stores the corrected data-bit column. Next, the system generates and stores new checkbits in a functioning memory component, wherein the new checkbits provide single-error-correction and double-error-detection for erroneous bits in the block of data, but do not provide for detection and correction of a failed memory component.12-30-2010
20100107038Cache controller and cache controlling method - A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.04-29-2010
20100107037MEMORY SYSTEM WITH ERROR CORRECTION AND METHOD OF OPERATION - A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.04-29-2010
20100107036ERROR CORRECTION IN MULTIPLE SEMICONDUCTOR MEMORY UNITS - Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the first memory unit.04-29-2010
20090125786Mechanism for Adjacent-Symbol Error Correction and Detection - According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.05-14-2009
20090125785Pipelined Data Relocation and Improved Chip Architectures - The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.05-14-2009
20090125783STORAGE APPARATUS, METHOD FOR ACCESSING DATA AND FOR MANAGING MEMORY BLOCK - A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data can be stored into the memory block in a block table according to the number of error correction bits in the memory block so that the sequence in which the memory block is used for storing data can be determined.05-14-2009
20130047054EXTENDED SINGLE-BIT ERROR CORRECTION AND MULTIPLE-BIT ERROR DETECTION - Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.02-21-2013
20130047055ERROR CORRECTION CODE TECHNIQUES FOR MATRICES WITH INTERLEAVED CODEWORDS - A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.02-21-2013
20090044074OFDM RECEIVING APPARATUS AND OFDM RECEIVING METHOD - An OFDM receiving apparatus has N sets of reception and demodulation units which input one segment broadcasting signals of ground digital broadcasting received with N sets of antennas and demodulate the signals; a buffer unit which includes N sets of buffers which hold temporarily N sets of demodulated data, which are demodulated in the N sets of reception and demodulation units, respectively, and reads the N sets of demodulated data, which are written in the N sets of buffers, in time division; and an error correction unit which inputs N sets of demodulated data read from the buffer unit in time division, performs error correction one by one, and in the process of the error correction, multiplexes the N sets of demodulated data, which have been error-corrected, in a period not used by one segment reception to output the data as one TS multiplex data.02-12-2009
20130073925ELECTRONIC DEVICE COMPRISING ERROR CORRECTION CODING DEVICE AND ELECTRONIC DEVICE COMPRISING ERROR CORRECTION DECODING DEVICE - An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from this remainder polynomial. This generator computes the remainder polynomial by dividing and inputting either a bit string comprising coefficients of the generator polynomial, or a bit string comprising coefficients of the generator polynomial and a bit string comprising coefficients of the generator polynomial, and dividing a minimal unit multiple times based on either a division width of the user polynomial or a division width of the user polynomial and the generator polynomial, and outputs a bit string comprising the coefficient of this remainder polynomial.03-21-2013
20130073924DATA STORAGE DEVICE AND METHOD TO CORRECT BIT VALUES USING MULTIPLE READ VOLTAGES - A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.03-21-2013
20130061114FREEZING-BASED LDPC DECODER AND METHOD - A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.03-07-2013
20130061115ERROR-CORRECTING CODE PROCESSING METHOD AND DEVICE - An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.03-07-2013
20100088575LOW DENSITY PARITY CODE (LDPC) DECODING FOR MEMORY WITH MULTIPLE LOG LIKELIHOOD RATIO (LLR) DECODERS - Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the first decoder. Probability values such as logarithmic likelihood ratio (LLR) values may be clipped in the second decoder. This approach can overcome trapping sets while exhibiting low complexity and high performance. Further, it can be implemented on existing decoders such as those used in current memory devices.04-08-2010
20080320368Error Detection and Correction Circuit and Semiconductor Memory - Input data (12-25-2008
20120226960RETRIEVAL OF ENCODED DATA SLICES AND ENCODED INSTRUCTION SLICES BY A COMPUTING DEVICE - A computing device includes a central processing unit (CPU) and a memory system module. The CPU includes a data dispersed storage error coding (DSEC) module operable to DSEC decode a set of encoded ingress data slices to recapture ingress data and DSEC encode egress data to produce a set of encoded egress data slices, an instruction DSEC module operable to DSEC decode a set of encoded instruction slices to recapture an instruction, and an arithmetic logic unit (ALU) operable to, execute the instruction on the ingress data and execute the instruction to produce the egress data. The memory system module is operable to coordinate retrieval of the set of encoded ingress data slices from memory, coordinate retrieval of the set of encoded instruction slices from the memory, and coordinate storage of the set of encoded egress data slices in the memory.09-06-2012
20120117445DATA PROTECTION METHOD FOR DAMAGED MEMORY CELLS - A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.05-10-2012
20120117444 Method Of Storing Blocks Of Data In A Plurality Of Memory Devices In A Redundant Manner, A Memory Controller And A Memory System - A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method.05-10-2012
20110022932VARIABLE SECTOR-COUNT ECC - Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.01-27-2011
20110022930ERROR CORRECTION CIRCUIT AND ERROR CORRECTION METHOD - An error correction circuit 01-27-2011
20110022929Error correcting apparatus, method of controlling memory of error correcting apparatus, and optical disc recording/reproducing apparatus - An error correcting apparatus includes a memory for storing therein second block data at an interval of a time difference while it uses a part of a storage area of first block data having multiple pieces of frame data each having data having a predetermined length as one unit, and an error correcting portion configured to subject the first block data and the second block data each read out from the memory to error correction.01-27-2011
20110022928CONTROLLER WITH ERROR CORRECTION FUNCTION, STORAGE DEVICE WITH ERROR CORRECTION FUNCTION, AND SYSTEM WITH ERROR CORRECTION FUNCTION - The invention is intended to curtail the circuit scale of the error correction circuit of a flash memory. The invention relates to a controller with error correction function capable of controlling writing and reading of data in a plurality of memories, including a buffer memory, an error correction circuit, and a plurality of interface modules provided individually corresponding to each one of the plurality of memories, for exchanging data with the memories, in which the plurality of interface modules have a plurality of syndrome generation function parts for receiving sector data from the memories and error correction codes corresponding to the sector data, and generating syndromes on the basis of the received sector data and error correction codes, the buffer memory.01-27-2011
20110022927COMPACT DECODING OF PUNCTURED CODES - k information bits are encoded according to a code with which is associated a parity check matrix H that has n columns. The entire resulting codeword is stored in a storage medium. At least n′01-27-2011
20090006929Erased Sector Detection Mechanisms - The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted bits is under the ECC correction limit. This method allows the storage system to become tolerant to erased sectors corruption, as such sectors can be used for further data storage if the system can correct this error later in the written data by ECC correction means.01-01-2009
20110035646NONVOLATILE RANDOM ACCESS MEMORY AND NONVOLATILE MEMORY SYSTEM - A nonvolatile random access memory includes: a nonvolatile storage area that is randomly accessible and includes a data area to store data and an error-correcting-code area to store an error correcting code, the data area including at least one data area to which a data area unit size is assigned, the error-correcting-code area including at least one error-correcting-code area to which an error-correcting-code-area unit size is assigned; and a nonvolatile storage area controller to set a data size used when the at least one data area is accessed, as the data area unit size. The nonvolatile storage area controller manages the data area and the error-correcting-code area based on the set data area unit size and assigns the at least one error-correcting-code area with the error-correcting-code-area unit size to the at least one data area with the data area unit size based on the data area unit size.02-10-2011
20110041037FLASH-based Memory System with Static or Variable Length Page Stripes including Data Protection Information and Auxiliary Protection Stripes - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.02-17-2011
20100031123UNIFIED MEMORY ARCHITECTURE FOR RECORDING APPLICATIONS - An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.02-04-2010
20110264986Decoding Circuit and Encoding Circuit - A decoding circuit including a data buffer comprises a plurality of storage elements for storing data symbols, a processing circuit comprising a plurality of inputs and outputs, wherein the processing circuitry is configured to process data symbols received via the plurality of inputs and outputs. First and second decoding parameters are determined by a decoding rule and wherein the first and the second decoding parameters are not changed throughout the decoding process.10-27-2011
20110283163Method and System for Identifying Errors in Code - A method for identifying errors in code is provided. The method may include rebuilding object dependencies from a heap dump, calculating memory usage of each object, identifying top consumers of memory by object class, analyzing how much memory each class consumes with respect to how much other classes consume, building a corpus of data that may be used in a progressive machine learning algorithm, and identifying suspect classes. Additionally, the suspect classes and the memory usage statistics of the suspect classes may then be used as an identifying signature of the associated out of memory error. The identifying signature of the associated out of memory error may then be used to compare with the signatures of other out of memory occurrences for identifying duplicate error occurrences.11-17-2011
20100269017NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.10-21-2010
20110302475Advanced Bitwise Operations and Apparatus in a Multi-Level System with Nonvolatile Memory - A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.12-08-2011
20110289384MEMORY SYSTEM WITH PAGE-BASED ITERATIVE DECODING STRUCTURE AND PAGE-BASED ITERATIVE DECODING METHOD THEREOF - A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.11-24-2011
20110289381MEMORY SYSTEM THAT PROVIDES GUARANTEED COMPONENT-FAILURE CORRECTION WITH DOUBLE-ERROR CORRECTION - The disclosed embodiments relate to a memory system that provides guaranteed component-failure correction and double-error correction. During operation, the memory system accesses a block of data, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row checkbits for each of the R rows, (2) an inner-checkbit column containing R inner checkbits, and (3) C-2 data-bit columns containing databits. In addition, each column is stored in a different memory component, and the checkbits are generated from the databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. Next, the system calculates a row syndrome and an inner syndrome for the block of data, wherein the inner syndrome that results from any two-bit error in the same row is unique. If the row syndrome and the inner syndrome are both non-zero, the system determines from the row syndrome and the inner syndrome whether errors in the block of data are associated with a failed memory component. If not, and if exactly two bits in the row syndrome are one, the system assumes that there exists a single-bit error in each of the two rows which have a row syndrome of one, and compares the calculated inner syndrome against inner syndromes for all possible combinations of one-bit errors occurring in each of the two rows. Then, if the comparison matches a given inner syndrome, the system corrects the two bits associated with the given inner syndrome.11-24-2011
20110289383RETRIEVING DATA FROM A DISPERSED STORAGE NETWORK IN ACCORDANCE WITH A RETRIEVAL THRESHOLD - A method begins by a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN), wherein the set of encoded data slices represents data encoded using a dispersed storage error encoding function having a pillar width of “n”, a decode threshold of “k”, and an encoding ratio of n−k>k and wherein the retrieval threshold is in accordance with the encoding ratio. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.11-24-2011
20110289382Programmable LDPC code decoder and decoding method thereof - A programmable LDPC (Low-Density Parity-Check) code decoder and decoding method thereof is disclosed. By combining at least one programmable switch and at least one memory unit to decode any quasi-cyclic-based parity check matrix, one can set the switch state of the programmable switch to dynamically adjust the size of the decoding matrix and determine the locations of 1's and 0's in the decoding matrix. The mechanism helps improving the usability and flexibility of the decoding matrix.11-24-2011
20110289380METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE - A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.11-24-2011
20080209304Convolution-Encoded RAID with Trellis-Decode-Rebuild - A Redundant Array of Independent Devices uses convolution encoding to provide redundancy of the striped data written to the devices. No parity is utilized in the convolution encoding process. Trellis decoding is used for both reading the data from the RAID and for rebuilding missing encoded data from one or more failed devices, based on a minimal, and preferably zero, Hamming distance for selecting the connected path through the trellis diagram.08-28-2008
20110302476Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.12-08-2011
20110219285SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.09-08-2011
20100023841MEMORY SYSTEM, SENSE AMPLIFIER, USE, AND METHOD FOR ERROR DETECTION BY MEANS OF PARITY BITS OF A BLOCK CODE - A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.01-28-2010
20100169740ACCELERATING PHASE CHANGE MEMORY WRITES - In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.07-01-2010
20100269019DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 10-21-2010
20090150751MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF - A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.06-11-2009
20120110414Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction - A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.05-03-2012
20110078542TURBO DECODING DEVICE AND COMMUNICATION DEVICE - A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit selects by which of the first bank configuration and the second bank configuration the memory unit functions in accordance with a communication method of a coded signal and accesses the memory unit in accordance with the selected bank configuration.03-31-2011
20100281340ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES - Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.11-04-2010
20130219244STORAGE DEVICE - A nonvolatile memory is configured with blocks as deletion units, each block having several pages that are configured as write units. A controller for the nonvolatile memory includes an error correcting circuit, which detects and corrects an error in data read out of a page in one of the blocks of the nonvolatile memory, the page being referenced by a logical address. The controller also determines an error occurrence when the error cannot be corrected. An error block table is provided to store the logical address where the error occurred, and a physical address corresponding to the logical address.08-22-2013
20100083073Data processing apparatus, memory controlling circuit, and memory controlling method - A data processing apparatus includes a memory, an additional bit generating unit which generates an additional bit to be added to write expectation values, on a basis of the write expectation values to be written respectively to designated addresses in the memory, the additional bit and the write expectation values being supplied to the memory as write data and stored respectively in memory cells at the addresses, and a write state judging unit which reads stored data retained in the memory cells at the addresses and judges a write state of the memory cells.04-01-2010
20100088574DATA STORAGE SYSTEM AND DEVICE WITH RANDOMIZER/DE-RANDOMIZER - A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.04-08-2010
20090177947METHOD FOR APPENDING DATA TO TAPE MEDIUM, AND APPARATUS EMPLOYING THE SAME - An information recording apparatus includes a writing system for writing the datasets to the recording medium, so that each of the datasets can be identified from a certain number indicating an order that each of the datasets was sequentially written to the recording medium, and from the number of writing operations (WP) carried out for a dataset of the certain number, the writing system writing a first dataset; the writing system being configured for substantially appending a second dataset onto the first dataset, the second dataset having the same certain number as the first dataset, and for setting a value obtained by incrementing the WP of the first dataset as the WP of the second dataset. A writing control system controls, in the case where an error occurs at the time of the appending, the appending on the first dataset, in a position shifted forward by a predetermined distance from the position of the first dataset on the recording medium, by setting the value obtained by incrementing the WP of the first dataset as the WP for the second dataset, wherein the predetermined distance is a distance with which error correction of the first dataset is avoided by appending the second dataset onto the first dataset so that the second dataset overwrites a part of the first dataset.07-09-2009
20090282316Memory Access in Low-Density Parity Check Decoders - Low Density Parity Check (LDPC) decoder circuitry in which memory resources are realized as single-port memory. The decoder circuitry includes a single port memory for storing log-likelihood ratio (LLR) estimates of input node data states for individual rows of a parity check matrix. The decoder circuitry also includes multiple instances of single-port column sum memories, which store updated LLR estimates for each input node. In each case, the memory resources include logic circuitry that executes at least one write cycle and one read cycle to the memory within each decoder cycle. Because the decoder cycle time is much longer than the necessary memory cycle time, particularly in LDPC decoding, data can be written to and read from single-port memory resources in ample time for the decoding operation.11-12-2009
20090292969Adjustable read reference for non-volatile memory - In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.11-26-2009
20100287447MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION - Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.11-11-2010
20110271166PIPELINE ARCHITECTURE FOR MAXIMUM A POSTERIORI (MAP) DECODERS - The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.11-03-2011
20110271165SIGNAL LINE TO INDICATE PROGRAM-FAIL IN MEMORY - Subject matter disclosed herein relates to a memory device and a method of operating same.11-03-2011
20120297270Programming Schemes for Multi-Level Analog Memory Cells - A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.11-22-2012
20100131827MEMORY DEVICE WITH INTERNAL SIGNAP PROCESSING UNIT - A method for operating a memory (05-27-2010
20100287446Low Latency Read Operation for Managed Non-Volatile Memory - In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller.11-11-2010
20090055713ECC CONTROL CIRCUITS, MULTI-CHANNEL MEMORY SYSTEMS INCLUDING THE SAME, AND RELATED METHODS OF OPERATION - An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.02-26-2009
20090049364NONVOLATILE MEMORY DEVICE, SYSTEM, AND METHOD PROVIDING FAST PROGRAM AND READ OPERATIONS - Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.02-19-2009
20100095186REPROGRAMMING NON VOLATILE MEMORY PORTIONS - A system and a method for reprogramming a non volatile memory (NVM) portion, the method includes: receiving an initial content of an NVM portion; wherein the initial content differs from an erase content of the NVM portion; processing the previously programmed content in response to input content that should be represented by an initial content of the NVM portion; wherein the processing is characterized by a write limitation that prevents a non-erase value of a bit to be changed to an erase value; wherein the processing comprises at least one out of skip value based encoding, generating error correction information and error correction code based encoding; and writing the processed content of the NVM portion to the NVM portion.04-15-2010
20090119567SEMICONDUCTOR MEMORY, OPERATING METHOD OF SEMICONDUCTOR MEMORY, AND SYSTEM - In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.05-07-2009
20120144267DATA READING METHOD, MEMORY STORAGE APPARATUS, AND CONTROLLER THEREOF - A data reading method for a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical pages. The data reading method includes grouping the physical pages into a plurality of physical page groups and configuring a corresponding threshold voltage set for each of the physical page groups. The data reading method also includes respectively reading data from the physical pages of the physical page groups by using the corresponding threshold voltage sets. The data reading method further includes when data read from one of the physical pages of one of the physical page groups cannot be corrected by using an error checking and correcting (ECC) circuit, updating the threshold voltage set corresponding to the physical page group.06-07-2012
20080209303Error Detection/Correction Method - A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.08-28-2008
20120272122EFFICIENT RE-READ OPERATIONS IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.10-25-2012
20120272121IMAGE PROCESSING APPARATUS AND CONTROL METHOD - An image processing apparatus and a method for controlling an image processing apparatus are disclosed. The method includes: primarily processing a first thread from among a plurality of threads for a preset process; generating and storing a first error correction code for data recorded in a stack area of a random access memory (RAM) corresponding to the first thread when a primary process terminates; processing a second thread which is different from the first thread from among the plurality of threads; determining whether the data of the stack area is valid on the basis of the stored first error correction code at a point of time when the process for the second thread terminates and a secondary process for the first thread begins; and secondarily processing the first thread by restoring the data having an error in the stack area in response to a determination that the data of the stack area is invalid.10-25-2012
20110126080DATA CODING FOR IMPROVED ECC EFFICIENCY - Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.05-26-2011
20110126079MULTI-CHANNEL MEMORY APPARATUS AND METHOD THEREOF - A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.05-26-2011
20090158124DATA STORAGE APPARATUS AND DATA STORAGE METHOD - In the ordinary operation mode, a data storage apparatus writes data into a first flash memory, while writing ECC data, which is used for correcting the data written in the first flash memory, into a second flash memory. When there is no remaining storage space in the first flash memory, the data storage apparatus deletes existing ECC data previously written in the second flash memory and writes ordinary data into the second flash memory. This arrangement enhances the reliability of data and enables effective use of the original storage space in the system of data storage with multiple storage areas.06-18-2009
20120084628RAM SINGLE EVENT UPSET (SEU) METHOD TO CORRECT ERRORS - An error detection and correction (EDAC) circuit mitigates the effect of single event upsets (SEU) events in a redundant memory system. The EDAC circuit includes a first input for receiving first data and parity information stored by a first memory device and a second input for receiving second data and parity information stored by a second memory device. First parity check logic calculates parity for the received first data and parity information. Second parity check logic calculates parity for the received second data and parity information. Bit comparison logic detects differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic selects either the first data or the second data for provision to a data bus.04-05-2012
20090125784MEMORY SYSTEM - A memory system has a plurality of operation modes corresponding to current drawn and accessibility. The system includes a nonvolatile memory which stores a transition log of an operation mode, and a controller which, whenever accessing a predetermined amount of data of the nonvolatile memory in the same operation mode, adds the operation mode to the transition log, and determines a present operation mode by using the transition log.05-14-2009
20090183052SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.07-16-2009
20090164869MEMORY ARCHITECTURE AND CONFIGURATION METHOD THEREOF - A memory architecture and a configuration method thereof are provided. In the memory configuration method, a data to be stored in the memory and a corresponding error correction code (ECC) are first provided. When the data is written into the memory, the ECC is stored next to the corresponding data, such that the ECC and the corresponding data can be adjoined with each other in the memory. As a result, when the data is read from the memory, the data and the corresponding ECC can be obtained in turn, so as to achieve the purpose of checking the correctness of the data with a smaller buffer, and the hardware cost of the buffer can also be reduced.06-25-2009
20090177946Memory Initialization Time Reduction - A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.07-09-2009
20090144600Efficient re-read operations from memory devices - A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC.06-04-2009
20090024902MULTI-CHANNEL ERROR CORRECTION CODER ARCHITECTURE USING EMBEDDED MEMORY - A memory system includes a plurality of memory devices; and a memory controller having a plurality of communication channels for communicating data with the plurality of memory devices. The memory controller includes an error correction encoder that is adapted to encode data to be communicated from the memory controller via the plurality of communication channels, and/or an error correction decoder that is adapted to detect and correct errors in data communicated to the memory controller via the plurality of communication channels.01-22-2009
20110225475LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit (09-15-2011
20090199074PARAMETER ESTIMATION BASED ON ERROR CORRECTION CODE PARITY CHECK EQUATIONS - A method for operating a memory, which includes analog memory cells, includes encoding data with an Error Correction Code (ECC) that is representable by a plurality of equations. The encoded data is stored in a group of the analog memory cells by writing respective input storage values to the memory cells in the group. Multiple sets of output storage values are read from the memory cells in the group using one or more different, respective read parameters for each set. Numbers of the equations, which are satisfied by the respective sets of the output storage values, are determined. A preferred setting of the read parameters is identified responsively to the respective numbers of the satisfied equations. The memory is operated on using the preferred setting of the read parameters.08-06-2009
20110145678DATA LINE STORAGE AND TRANSMISSION UTILIZING BOTH ERROR CORRECTING CODE AND SYNCHRONIZATION INFORMATION - Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.06-16-2011
20090241009Encoding and/or decoding memory devices and methods thereof - Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.09-24-2009
20120079350METHOD AND APPARATUS FOR CALCULATING ERROR CORRECTION CODES FOR SELECTIVE DATA UPDATES - The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error correction code bits formed from a plurality of data bits in response to changes in a first subset of the data bits. The first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits.03-29-2012
20120079349METHOD AND APPARATUS FOR MULTI-BIT UPSET PROTECTION - Techniques for detecting for a change to information in a line of data of a data storage device. In an embodiment, a line of data includes a first set of bits and a second set of bits, each associated with distinct reference parity evaluations. Respective update parity values are determined for the first bit set and the second bit set, each update parity value for comparison to a corresponding one of the reference parity evaluations. A change to the information in the line of data may be detected based on the comparison of reference parity values to update parity values.03-29-2012
20120079348DATA WITH APPENDED CRC AND RESIDUE VALUE AND ENCODER/DECODER FOR SAME - A semiconductor chip is described having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between an instruction execution core and a memory controller; and, iii) an interconnect path that resides between a cache and a memory controller. The ECC decoder circuitry has an input register to receive data, CRC values associated with the data and residue information associated with the data.03-29-2012
20090100315METHODS AND APPARATUS FOR PROVIDING ERROR CORRECTION TO UNWRITTEN PAGES AND FOR IDENTIFYING UNWRITTEN PAGES IN FLASH MEMORY - Provided are methods for error correction coding (ECC) for flash memory pages which have been erased but have not been programmed. In one method, each ECC code word is bitwise inverted before being programmed into a page, and bitwise inverted again after being read back from the page before entering the decoder. Thus an unwritten page, whose bits are all ones when random errors are absent, appears to the decoder as all zeros, which form a valid code word(s) in linear block codes. In another method, in both page programming and page read, the parity section of each ECC code word is bitwise XORed with the complement of a parity calculated from a message whose bits are all ones. Thus an unwritten page appears to the decoder as a valid ECC code word(s) when random errors are absent. Further provided is an apparatus for determining after a page read whether or not the read page has been programmed by comparing the number of read code word symbols which do not have the default erased value and the maximum number of symbol errors correctable by the ECC.04-16-2009
20110231732ERROR CORRECTING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE SYSTEM USING THE SAME - An error correcting method for a memory chip is provided. The memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased. The error correcting method includes sequentially writing a plurality of data into the physical pages of a first physical block and generating a parity information according to the data. The error correcting method further includes writing the parity information into one of the physical pages of the first physical block following the data and correcting the data in the first physical block according to the parity information. Accordingly, the parity information can be used for correcting error bits in the data when an error checking and correcting circuit can not correct the error bits. Thereby, the error correcting ability is enhanced.09-22-2011
20110231733ADJUSTING DATA DISPERSAL IN A DISPERSED STORAGE NETWORK - A method begins by a processing module determining a performance based indication regarding storage of a data segment as a set of encoded data slices and comparing the performance based indication with a performance threshold. When the performance based indication compares unfavorably with the performance threshold, the method continues with the processing module decoding the set of encoded data slices to reproduce the data segment, adjusting error coding dispersal storage function parameters based on the unfavorable comparison of the performance based indication with the performance threshold to produce performance adjusted error coding dispersal storage function parameters, encoding the reproduced data segment in accordance with the performance adjusted error coding dispersal storage function parameters to produce a second set of encoded data slices, and selecting a storage set of encoded data slices from the set of encoded data slices and the second set of encoded data slices.09-22-2011
20090204871NON-VOLATILE MEMORY WITH ERROR DETECTION - Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.08-13-2009
20090210771SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.08-20-2009
20120198309CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES - Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.08-02-2012
20090249167Semiconductor memory device - A semiconductor memory device includes a data storage area wherein a plurality of data cells, respectively storing one bit of data, is arranged in a lattice form, a redundant data storage area that stores one bit parity data, the one bit parity data corresponding respectively to a line of data read out of the data storage area as a data group, a first switch section that receives a data group read out from the data storage area and a parity data bit, and a composite unit that receives an output of the first switch section and that generates correction data for the read data group, as based upon defect position information of the data storage area. The first switch section is selectively controlled to provide the parity data bit associated with the read data group as an input into the composite unit based on the defect position information.10-01-2009
20090249168STORAGE DEVICE - A storage device includes: a storage medium; an auxiliary memory; and a controller for: determining an error correcting code length corresponding to an error rate of a data write area and/or an error correcting code write area of the storage medium; generating an error correcting code on the basis of the data and the determined error correcting code length; storing the generated error correcting code in the error correcting code write area and storing the data in the data write area; and storing a part of the error correcting code in the auxiliary memory if the generated error correcting code has a greater data length than that of the error correcting code write area, so that the part of the error correcting code overflowed from the error correcting code write area is stored in the auxiliary memory.10-01-2009
20100275101DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.10-28-2010
20130219246Method and Apparatus for Detecting Free Page and a Method and Apparatus for Decoding Error Correction Code Using the Method and Apparatus for Detecting Free Page - A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.08-22-2013
20130219245CURRENT MODE ANALOG BELIEF PROPAGATION - An analog belief propagation system uses current mode implementations of storage elements and circuit implementations of at least some nodes of a factor graph using current representations. The system mitigates or avoids effects of non-linearities and approximations in storage and processing elements of the system, for instance, by using storage cells that reproduce current values and using factor circuits that separate control sections and signal path sections of the circuits.08-22-2013
20100153820MEMORY WITH GUARD VALUE DEPENDENT ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed.06-17-2010
20100153819Decoding Method and System for Low-Density Parity Check Code - A decoding method for LDPC code includes steps of obtaining a set of parity-check matrices of a set of block codes; obtaining an identical parity-check matrix from the set of parity-check matrices; dividing the identical parity-check matrix into an odd identical parity-check matrix and an even identical parity-check matrix, wherein the odd identical parity-check matrix being composed of odd rows of the identical parity-check matrix, and the even identical parity-check matrix being composed of even rows of the identical parity-check matrix; and decoding the set of block codes basing on the odd identical parity-check matrix and the even identical parity-check matrix.06-17-2010
20100153818MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.06-17-2010
20100162080STORAGE APPARATUS HAVING NONVOLATILE STORAGE MODULE - According to one embodiment, a storage apparatus includes a first nonvolatile storage module, a second nonvolatile storage module, and an error checking and correction module. The first nonvolatile storage module undergoes a destructive read when data is read from it. The second nonvolatile storage module stores the address data representing the storage location in the first nonvolatile storage module at which data to be read is stored. The error checking and correction module checks for and corrects an error in the data stored at the storage location in the first nonvolatile storage module which is represented by the address data stored. The error checking and correction module writes the corrected data back into the first nonvolatile storage module.06-24-2010
20100162081NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a nonvolatile memory device comprises performing a read operation to read data stored in a first memory cell block including first unit groups; detecting a second unit group from among the first unit groups, the second unit group having a number of error bits included in the read data, which is greater than a set number of bits and equal to or smaller than a maximum allowable number of bits which can be corrected through an error checking and correction (ECC) processing; and after the second unit group is detected, performing a copyback operation for moving the data, that are stored in the first memory cell block, to a second memory cell block.06-24-2010
20100162082CONTROL DEVICE, STORAGE APPARATUS AND CONTROLLING METHOD - A control device operable under a power supplied from a main power source, the control apparatus includes a memory for storing data with an error detection code, the data being used for execution of processing, a judging section for judging whether an error in the data stored in the memory by the power from a sub power source is detected using the error detection code after the power from the main power source to the memory has been resumed. The control apparatus includes a processing control section for continuing execution of the processing using the data stored in the memory if it has been judged that no error in the data stored in the memory is detected by the judging section, and executing a recovery processing if it has been judged that an error in the data stored in the memory is detected.06-24-2010
20100185921METHOD AND SYSTEM FOR IN-PLACE UPDATING CONTENT STORED IN A STORAGE DEVICE - Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.07-22-2010
20090292973Memory device and method of storing data - Memory devices and/or methods of storing memory data bits may be provided. A memory device may include a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it may be possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.11-26-2009
20120198310CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES - This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.08-02-2012
20100169741ERROR CORRECTION CODE FOR UNIDIRECTIONAL MEMORY - A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.07-01-2010
20100169739Poison bit error checking code scheme - In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.07-01-2010
20100262890ERROR CORRECTION FOR MEMORY - Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.10-14-2010
20100192043INTERRUPTION CRITERIA FOR BLOCK DECODING - While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified.07-29-2010
20100192042READING A FLASH MEMORY BY CONSTRAINED DECODING - To read memory cells that have been programmed to store an ECC codeword, with each cell storing a respective plurality of bits of the codeword, a respective value of an operational parameter such as a threshold voltage of each cell is measured. Each bit is assigned a respective metric, such as a LLR estimate of the bit, based at least in part on the respective value of the operational parameter of the bit's cell. The metrics are decoded with reference both to the ECC and to mutual constraints of the metrics within each cell that are independent of the ECC.07-29-2010
20100192041MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.07-29-2010
20100218071WRITING A SPECIAL SYMBOL TO A MEMORY TO INDICATE THE ABSENCE OF A DATA SIGNAL - A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.08-26-2010
20120198311UTILIZING A DISPERSED STORAGE NETWORK ACCESS TOKEN MODULE TO ACCESS A DISPERSED STORAGE NETWORK MEMORY - A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.08-02-2012
20100241928Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection - A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.09-23-2010
20100235715APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL SOLID-STATE STORAGE AS SINGLE-LEVEL CELL SOLID-STATE STORAGE - An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.09-16-2010
20100235714RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the difference of the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array.09-16-2010
20100235716DUAL PORTED REPLICATED DATA CACHE - A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.09-16-2010
20100251071REDUNDANT CODE GENERATION METHOD AND DEVICE, DATA RESTORATION METHOD AND DEVICE, AND RAID STORAGE DEVICE - A redundant code generation method includes: dividing original data into data strings; dividing each data string into a number of bit strings that accords with an extended Galois field operation; storing each of the bit string in a different memory area of a memory; and executing an exclusive OR operation among vectors, which are extracted from the respective bit strings stored in the memory, according to an operational expression to compute bit strings that make up redundant code data strings without carrying out a bit shift operation within the vectors. A predetermined plural number of bits is taken as a data unit and the number of bits as elements constituting each vector is equal to the data unit. The operational expression includes a companion matrix of a primitive polynomial of the Galois field and defined the generation of the redundant code data strings.09-30-2010
20100235713NON-VOLATILE MEMORY GENERATING READ RECLAIM SIGNAL AND MEMORY SYSTEM - A non-volatile memory device includes a memory cell array including memory blocks, an ECC circuit receiving read data from the memory cell array and detecting error bits, wherein the ECC circuit is capable of detecting and correcting a maximum number of error bits, a counter counting detected error bits and generating an error-possible data indication when the counted error bits exceed a minimum error threshold, wherein the minimum error threshold is less than the maximum number of error bits, and a read reclaim indicator receiving the error-possible data indication and generating read reclaim indication for the memory block storing the read data.09-16-2010
20100218072MEMORY DEVICE - An exemplary memory device has at least one memory chip that stores data and error correcting information. An error detecting circuit in the memory chip performs a calculation on the data and error correcting information to obtain error detection information indicating the locations of bit errors in the data. The uncorrected data and the error detection information are output from the memory chip. The uncorrected data and error detection information may also be output from the memory device, or the memory device may include a memory controller chip with an error correcting circuit that uses the error detection information to correct the bit errors and outputs corrected data from the memory device.08-26-2010
20100211851DATA STORAGE SYSTEM WITH NON-VOLATILE MEMORY FOR ERROR CORRECTION - The present disclosure provides a data storage system with non-volatile memory for error correction. In one example, a data storage system is provided and includes a first data storage device comprising a first non-volatile data storage medium and a second data storage device that comprises a second non-volatile data storage medium. The system also includes a controller configured to store data to the first data storage device. The controller is configured to selectively generate error correction information for selected portions of the data based on at least one attribute associated with the data and store the error correction information in the second data storage device.08-19-2010
20100251072DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM - A RAID system is provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.09-30-2010
20110113304METHOD FOR DECODING A SUCCESSION OF BLOCKS ENCODED WITH AN ERROR CORRECTION CODE AND CORRELATED BY A TRANSMISSION CHANNEL - A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.05-12-2011
20110066921System and Method for Responding to Error Detection - Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.03-17-2011
20100269020LDPC DECODER - A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.10-21-2010
20100269018Method for preventing IP address cheating in dynamica address allocation - Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.10-21-2010
20100269016MULTIPLE-LEVEL MEMORY CELLS AND ERROR DETECTION - Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.10-21-2010
20090319868READING A FLASH MEMORY BY JOINT DECODING AND CELL VOLTAGE DISTRIBUTION TRACKING - To read a plurality of memory cells, each cell is assigned to a respective cell population. A respective value of an operational parameter of each cell is measured. Each cell is assigned an a-priori metric based at least in part on one or more CVD parameter values of the cell's population. The a-priori metrics are decoded. Based at least in part on the resulting a-posteriori metrics, the CVD parameter values are corrected, without repeating the measurements of the cell operational parameter values. The operational parameter values are indicative of bit patterns stored in the cells, and the correction of the CVD parameter values is constrained by requiring the bit patterns collectively to be a valid codeword.12-24-2009
20090319869Failure tolerant data storage - A method for storing data across a plurality of N storage devices S12-24-2009
20090319867MEMORY SYSTEM AND MEMORY ACCESS METHOD - A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.12-24-2009
20110131471TECHNIQUES FOR DETECTING AND CORRECTING ERRORS IN A MEMORY DEVICE - A technique for detecting and correcting errors in a memory device, in accordance with one embodiment, includes a data storage area arranged in a plurality of blocks, wherein each block contains a plurality of words. The memory device also includes an error detection/correction storage area for storing error detection/correction bytes corresponding to each word in each block and error detection words corresponding to each block.06-02-2011
20100223530SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - Provided are a semiconductor memory device and a data processing method thereof. The semiconductor memory device includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data a plurality of memory cells. The memory controller rearranges data by various operations such as a modulation code operation and processes the data according to an ECC operation to reduce the interference between the memory cells.09-02-2010
20120144269ERROR DETECTION FOR MULTI-BIT MEMORY - Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.06-07-2012
20120144268ACCESS CONTROL APPARATUS, STORAGE APPARATUS, AND METHOD - An access control apparatus for controlling an access to a storage device, the access control apparatus includes a measuring unit configured to measure the time to erase data stored in the storage device, and a determination unit configured to determine a data size of an error correcting code added to data stored in the storage device in accordance with the time measured by the measuring unit. The access control apparatus includes a generation unit configured to generate the error correcting code having the data size determined by the determination unit, and an access controller configured to write the data and the error correcting code generated by the generation unit into the storage device.06-07-2012
20090106628SAFE COMMAND EXECUTION AND ERROR RECOVERY FOR STORAGE DEVICES - Techniques for execution of commands securely within a storage device are disclosed. Integrity of a command interpreter is verified before allowing it to execute commands within the storage device. The integrity of the commands can also be checked to safeguard against various threats including, for example, malicious attacks, unintentional errors and defects that can adversely affect stored content and execution. Error recovery techniques can be used to reconstruct the command interpreter and/or commands that are found to be defective. In addition, secure techniques can be used to obtain trusted versions of the command interpreter and/or commands from an authenticated external source.04-23-2009
20110113303METHOD AND APPARATUSES FOR CUSTOMIZABLE ERROR CORRECTION OF MEMORY - Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data.05-12-2011
20090070656MEMORY SYSTEM WITH ERROR CORRECTION DECODER ARCHITECTURE HAVING REDUCED LATENCY AND INCREASED THROUGHPUT - A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.03-12-2009
20130013978DETERMINING SECTOR STATUS IN A MEMORY DEVICE - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.01-10-2013
20100306621ENCODING AND DECODING DATA - The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols S12-02-2010
20130139031LOW DENSITY PARITY CHECK CODEC - The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.05-30-2013
20100332943METHOD AND DEVICE FOR SELECTIVELY REFRESHING A REGION OF A NON-VOLATILE MEMORY OF A DATA STORAGE DEVICE - A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non-volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region.12-30-2010
20100332945FACILITATING PROBABILISTIC ERROR DETECTION AND CORRECTION AFTER A MEMORY COMPONENT FAILURE - Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X12-30-2010
20100332942Memory controller for NAND memory using forward error correction - A memory controller 12-30-2010
20100332948DISK ARRAY APPARATUS, A DISK ARRAY APPARATUS CONTROL METHOD AND A PROGRAM FOR A DISK ARRAY APPARATUS - A disk array apparatus includes a plurality of magnetic disks, and a RAID controller that generates redundancy data for host data received from a host apparatus by a primitive polynomial of Galois extension field, generates a redundancy code for the host data and the redundancy data, the redundancy code is a cyclic code calculated by a generating polynomial identical to the primitive polynomial, and writes the host data and the redundancy data to the plurality of magnetic disks.12-30-2010
20100332946METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE FOR IMPLEMENTING THE SAME - A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.12-30-2010
20100332947STORAGE CONTROL DEVICE AND STORAGE CONTROL METHOD - A storage control apparatus includes a storage unit having a plurality of blocks for storing data, each of the plurality of blocks being detected for data error by an error check code (ECC), a processor to execute a process to at least, modify an ECC stored in one of the storage unit, detect data-reading error in at least one block in the storage unit based on the modified ECC, and determine the number of detected blocks in the storage unit.12-30-2010
20110022931MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided.01-27-2011
20120246542SELECTIVE CHECKBIT MODIFICATION FOR ERROR CORRECTION - Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.09-27-2012
20080320367APPARATUS FOR ACCESSING AND TRANSFERRING OPTICAL DATA - An apparatus for accessing and transferring optical data has a memory supporting the page-mode function, an accessing device used to access an error correction block from the optical storage medium and store it into the memory to make the portion of data in the same column of the error correction block stored in a particular locality greater than the portion of data in the same row of the error correction block stored in the particular locality, and an error correction decoder used to access the data of the error correction block to perform the error correction process. The apparatus uses the feature of the DRAM, such as page-mode junction, and the data arrangement of the memory to improve the access efficiency of the memory. The apparatus can thus increase the access speed of the error correction decoder and improve the accessing efficiency.12-25-2008
20110035645DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals.02-10-2011
20130151924DATA SYSTEM FOR INTERFACING WITH A REMOTE DATA STORAGE FACILITY USING COMPRESSIVE SENSING AND ASSOCIATED METHODS - A data handling system includes a compressive sensing unit that receives a source date file. A sparseness module compressive sensing unit generates a sparse source data file by inducing sparseness into the source data file. A measurement module within the compressive sensing unit generates a compressed sensed source data file from the sparse source data file and based on a sensing matrix. The compressed sensed source data file is to be transmitted to a remote data storage facility for storage. A recovery unit generates the source data file from the compressed sensed source data file retrieved from the remote data storage facility and based upon the sensing matrix.06-13-2013
20090063933LCPC DECODING METHODS AND APPARATUS - A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.03-05-2009
20110055662NESTED DISTRIBUTED STORAGE UNIT AND APPLICATIONS THEREOF - A method for execution by a DS storage unit begins with the DS storage unit receiving an encoded slice of a plurality of encoded slices, wherein the plurality of encoded slices was generated from a data segment using an error encoding function. The method continues with the DS storage unit determining whether the encoded slice is to be sub-sliced using a sub-slicing encoding function. The method continues with the DS storage unit generating a plurality of encoded sub-slices from the encoded slices using the encoded sub-slicing encoding function when the encoded slice is to be sub-sliced. The method continues with the DS storage unit outputting the plurality of encoded sub-slices to a plurality of DS storage units.03-03-2011
20110055661METHOD AND APPARATUS FOR NESTED DISBURSED STORAGE - A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.03-03-2011
20110055663Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves - Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function 03-03-2011
20100031122Serially Concatenated Convolutional Code Decoder with a Constrained Permutation Table - An SCCC decoding system is provided. The system is comprised of an outer decoder module (02-04-2010
20100131826ESTIMATION OF NON-LINEAR DISTORTION IN MEMORY DEVICES - A method for operating a memory (05-27-2010
20100131825Memory Device with Error Correction Capability and Efficient Partial Word Write Operation - A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.05-27-2010
20090327837NAND error management - Techniques to manage various errors in memory such as, e.g., NAND memory in electronic devices are disclosed. In some embodiments, erase, read, and program error handling errors are managed.12-31-2009
20100070830ERROR DETECTION AND LOCATION CIRCUITRY FOR CONFIGURATION RANDOM-ACCESS MEMORY - Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.03-18-2010
20100037121LOW POWER LAYERED DECODING FOR LOW DENSITY PARITY CHECK DECODERS - The disclosed subject matter provides low power layered LDPC decoders and related systems and methods. Exemplary embodiments of the disclosed subject matter can achieve significant reduction in memory access of the associated memories by bypassing the associated memories depending on the decoding algorithm (e.g., code rate) and the characteristic of the LDPC parity check matrix, thereby providing significant reductions power consumption of LDPC decoders. According to various embodiment, an optimal decoding order can be determined and scheduled to maximize the power reduction available by bypassing the associated memories. In addition, various algorithms are disclosed that determine optimal search orders under various constraints. According to the disclosed subject matter, particular embodiments can further reduce power consumption by employing the disclosed thresholding to further reduce memory access. Additionally, various modifications are provided, which achieve a wide range of performance and computational overhead trade-offs according to system design considerations.02-11-2010
20100037122Memory Controller for Reducing Time to Initialize Main Memory - In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending an first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.02-11-2010
20090217134INTEGRATED APPARATUS FOR MULTI-STANDARD OPTICAL STORAGE MEDIA - An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error correction code (ECC) engine for encoding or decoding the CD/DVD data stream, the HDDVD data stream and the BD data stream. Therein, the ECC engine further has a syndrome/parity generator to encode the data stream or to obtain the syndrome information from the data stream; and an erasure generator to obtain the possible error position information from the data stream. Thereby, the complexity and cost of the integrated apparatus can be reduced.08-27-2009
20100070829Error checking and correction overlap ranges - A method to write data with error checking and correction overlap ranges is disclosed. The method generally includes the steps of (A) receiving plurality of input numbers in a plurality of input signals, (B) generating a plurality of error correction codes by separately operating on each of a plurality of unique pairs of the input numbers, wherein each of the error correction codes is configured to correct at least one error in a corresponding one of the unique pairs and (C) storing the input numbers and the error correction codes in a memory.03-18-2010
20100058144MEMORY SYSTEM WITH ECC-UNIT AND FURTHER PROCESSING ARRANGEMENT - A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors.03-04-2010
20110107181DATA DISTRIBUTION UTILIZING UNIQUE WRITE PARAMETERS IN A DISPERSED STORAGE SYSTEM - A method begins by a processing module receiving a plurality of record requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the processing module generating a list of requesting device identities corresponding to the plurality of requests and storing the plurality of sets of encoded data slices and the list of requesting device identities in a dispersed storage network memory. The method continues with the processing module receiving a playback request from a device identified in the list of requesting device identities, generating a unique retrieval matrix for the device, and outputting a unique plurality of sets of encoded data slices from the plurality of sets of encoded data slices in accordance with the unique retrieval matrix.05-05-2011
20100241929Semiconductor Memory Device for Performing Additional ECC Correction According to Cell Pattern and Electronic System Including the Same - A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented.09-23-2010
20110154160SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.06-23-2011
20110078540INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS - To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.03-31-2011
20110083060MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME - A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.04-07-2011
20120304038ERROR RECOVERY STORAGE ALONG A MEMORY STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.11-29-2012
20110078541STORAGE DEVICE AND DATA PROCESS METHOD - A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased.03-31-2011
20110072332Method for Copying Data in Reprogrammable Non-Volatile Memory - The present invention presents methods for improving data relocation operations. In one aspect, rather than check the quality of the data based on its associated error correction code (ECC) in every relocation operation, it is determined whether to check ECC based on predetermined selection criteria, and if ECC checking is not selected, causing the memory to perform an on-chip copy the data from a first location to a second location. If ECC checking is selected, the data is transferred to the controller and checked; when an error is found, a correction operation is performed and when no error is found, an on-chip copy is performed. The predetermined selection criteria may comprise a sampling mechanism, which may be random based or deterministic. In another aspect, data transfer flags are introduced to indicate data has been corrected and should be transferred back to the memory. A further aspect considers the header and user data separately if each has a distinct associated ECC.03-24-2011
20110072331MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME - A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.03-24-2011
20110060966DATA PROGRAMMING METHOD AND SYSTEM THEREOF - A data programming method and a system thereof are provided to program an original data into a memory. In the method, the original data complying with a first data arrangement rule is converted into an intermediate data complying with a second data arrangement rule, wherein the second arrangement rule corresponds to a type of the memory. Next, the intermediate data is analyzed to obtain at least one failure area which causes program disturb, and the content of the at least one failure area is replaced by a corresponding adjustment code. The replaced intermediate data is encoded, and a corresponding encoding information is generated. After the encoded intermediate data and the encoding information are both converted into a non-failure data complying with the first data arrangement rule, the non-failure data is programmed into the memory.03-10-2011
20110029841SEMICONDUCTOR MEMORY SYSTEM HAVING ECC CIRCUIT AND CONTROLLING METHOD THEREOF - A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.02-03-2011
20090024901APPARATUS AND METHOD FOR DECODING BURSTS OF CODED INFORMATION - A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.01-22-2009
20110029842MEMORY CONTROLLER UTILIZING DISTRIBUTED STORAGE - A memory controller comprises at least a memory control processing module and/or a distributed storage processing module. A method begins by the memory control processing module receiving a memory access request regarding a data segment. The method continues with the memory control processing module interpreting the memory access request to determine whether an error coding dispersal function of the data segment is applicable. The method continues with the memory control processing module sending the memory access request to the distributed storage processing module when the error coding dispersal function is applicable. The method continues with the distributed storage processing module performing the error coding dispersal function on the data segment to produce an error coded processed data segment. The method continues with the distributed storage processing module sending the error coded processed data segment to the memory control processing module.02-03-2011
20110029840Erasure Coded Storage Aggregation in Data Centers - Embodiments of erasure coded storage aggregation are disclosed. The erasure coded storage aggregation includes storing a data file as erasure coded fragments in a plurality of nodes of one or more data centers. The erasure coded storage aggregation further includes monitoring an access frequency of the data file. Based on the comparison between the access frequency and a predetermined threshold, the data file is either reconstructed from the erasure coded fragments and stored in a storage node or retained as erasure coded fragments in the plurality of nodes of the one or more data centers.02-03-2011
20110016371SEMICONDUCTOR STORAGE DEVICE AND METHOD OF OPERATING THE SAME - Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 01-20-2011
20110258514OVERLAPPING ERROR CORRECTION OPERATIONS - Systems and methods of overlapping error correction operations are disclosed. A method at an encoder device includes receiving data bits to be encoded including a first bit, a second bit, and a third bit. A first encode operation to encode a first group of the data bits is initiated to generate a first codeword. The first group of the data bits includes the first bit and the second bit, but not the third bit. A second encode operation to encode a second group of the data bits is initiated to generate a second codeword. The second group of the data bits includes the second bit and the third bit, but not the first bit.10-20-2011
20120204081Iterative Decoder - An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.08-09-2012
20110161782N-WAY PARALLEL TURBO DECODER ARCHITECTURE - Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.06-30-2011
20120204080Utilization of non-systematic (207, 187) Reed-Solomon coding in mobile/hand-held digital television receivers - Non-systematic (207, 187) Reed-Solomon codewords contain valuable information concerning the correctness of the outer convolutional coding of the serial concatenated convolutional coding, (SCCC) used for transmitting M/H-service data. An M/H receiver can decode the non-systematic (207, 187) Reed-Solomon coded MHE packets before and during turbo decoding of the SCCC. The decoding results are used to influence the soft decisions concerning bits of the SCCC that arise during SCCC decoding procedures. The decoding results can sometimes correct errors in the outer convolutional coding of the SCCC. The decoding results can be employed to stop the iterative SCCC decoding procedures sometimes before reaching a prescribed maximum number of iterations.08-09-2012
20080320366METHODS OF READING NONVOLATILE MEMORY - In a nonvolatile memory system, first raw data is obtained from stored data using a first set of reading parameters. Subsequently, the first raw data is transferred to an ECC circuit where it is decoded. While the first raw data is being transferred and decoded, second raw data is obtained from the same stored data using a second set of reading parameters.12-25-2008
20110179337MEMORY UTILIZATION METHOD FOR LOW DENSITY PARITY CHECK CODE, LOW DENSITY PARITY CHECK CODE DECODING METHOD AND DECODING APPARATUS THEREOF - A memory utilization method of low density parity check code (LDPC), a LDPC decoding method and a decoding apparatus thereof are provided, applicable for a decoding process in a wireless receiver. The memory utilization method of LDPC includes the following steps. First, variable node processes (VNPs) or check node processes (CNPs) required to be executed at a same time stage are determined. Next, the VNPs or the CNPs executed at the same time stage are allocated in different VNP groups or different CNP groups. Further, a folding factor of memory units is determined according to a desired data throughput. Then, according to the folding factor and the allocated VNP groups or the allocated CNP groups, the memory units are connected serially as a plurality of parallel processing memory modules.07-21-2011
20110047439SOFT ERROR RATE PROTECTION FOR MEMORIES - Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.02-24-2011
20120311405CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD - A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.12-06-2012
20120311404LOW DENSITY PARITY CHECK DECODER - An error correction code decoder comprising a computational memory array having at least a variable node section and a check node section, said computational memory array comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and each cell implementing one node; and a controller to instruct said computational memory to perform said operations and to write the results of computations on a block of variable nodes into its associated set of blocks of check nodes and to write the results of computations on a block of check nodes into its associated set of blocks of variable nodes.12-06-2012
20120311403PRIORITIZED DELETING OF SLICES STORED IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module monitoring storage of data, wherein the data is encoded using a dispersed storage error coding function to produce a plurality of sets of encoded data slices and is stored as the plurality of sets of encoded data slices. The method continues with the DS processing module determining analysis priority of the data in accordance with an analysis prioritization protocol. When the analysis priority of the data compares unfavorably to a first priority threshold, the method continues with the DS processing module issuing a command to delete an encoded data slice from each set of at least some of the plurality of sets of encoded data slices.12-06-2012
20120311402DATA READING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE - A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.12-06-2012
20120311401MULTIPORT MEMORY ELEMENT CIRCUITRY - Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.12-06-2012
20110055660High-Reliability Memory - A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.03-03-2011
20110055659Method and System of Dynamic Data Storage for Error Correction in a Memory Device - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined.03-03-2011
20100306622MEMORY SYSTEM AND DATA TRANSFER METHOD - A memory system includes a nonvolatile memory configured to store data, a first buffer configured to temporarily store data from the nonvolatile memory, a correction circuit configured to correct an error of data from the first buffer, a second buffer configured to temporarily store data from the correction circuit, a bus configured to receive data from the second buffer, a command sequence unit configured to issue a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer, and a command decode unit configured to decode the command and to generate a control signal for controlling the data transfer.12-02-2010
20110258515Memory Having an ECC System - An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.10-20-2011
20110016370MEMORY APPARATUS AND OPERATION METHOD THEREOF - A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded.01-20-2011
20110264985SERIAL CONCATENATION OF INTERLEAVED CONVOLUTIONAL CODES FORMING TURBO-LIKE CODES - A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.10-27-2011
20100287445System to Improve Memory Reliability and Associated Methods - A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.11-11-2010
20100293438System to Improve Error Correction Using Variable Latency and Associated Methods - A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.11-18-2010
20100293436System for Error Control Coding for Memories of Different Types and Associated Methods - A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.11-18-2010
20100293439APPARATUS, SYSTEM, AND METHOD FOR RECONFIGURING AN ARRAY TO OPERATE WITH LESS STORAGE ELEMENTS - An apparatus, system, and method are disclosed for reconfiguring an array of solid-state storage elements protected using parity data. The storage element error module determines that one or more storage elements are unavailable to store data (“unavailable storage elements”). The storage element resides in an array with N number of storage elements storing a first ECC chunk and P number of storage elements storing first parity data. The reconfigure data read module reads data from storage elements other than the unavailable storage elements. The data regeneration module uses the first parity data to regenerate missing data from the first ECC chunk. The data reconfiguration module creates a second ECC chunk. The new configuration storage module stores a portion of the second ECC chunk and associated second parity data on (N+P)−Z number of storage elements, wherein 1≦Z≦P.11-18-2010
20100293437System to Improve Memory Failure Management and Associated Methods - A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.11-18-2010
20110138251MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.06-09-2011
20110029839Systems and Methods for Utilizing Circulant Parity in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.02-03-2011
20100122147MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE - A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.05-13-2010
20100122146ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.05-13-2010
20110093764MEMORY MODULE ON WHICH REGULAR CHIPS AND ERROR CORRECTION CHIPS ARE MOUNTED - Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.04-21-2011
20110145679Validating Data Using Processor Instructions - In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.06-16-2011
20110138252MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.06-09-2011
20120151298MEMORY WITH SELECTIVELY WRITABLE ERROR CORRECTION CODES AND VALIDITY BITS - Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.06-14-2012
20110185261SEMICONDUCTOR MEMORY DEVICE - A memory device includes an error detection and correction system with an error correcting code over GF(207-28-2011
20090300465STATISTICAL TRACKING FOR FLASH MEMORY - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data.12-03-2009
20090292972Error correction apparatus, method thereof and memory device comprising the apparatus - An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.11-26-2009
20090292971Data recovery techniques - Techniques are described that include reading a portion of a memory and determining whether there is any uncorrectable codeword. Due to time varying errors present during a read operation, the uncorrectable codeword may become read as a correctable codeword at another time. If any uncorrectable codeword is present in the portion, the portion can be re-read to determine whether any uncorrectable codeword is instead correctable. Prior to re-reading the portion, a reference level used to determine whether a logic zero or one is stored can be adjusted. Adjusting the reference level can allow an uncorrectable codeword to become a correctable codeword.11-26-2009
20090292970Using error information from nearby locations to recover uncorrectable data in non-volatile memory - In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.11-26-2009
20110154161FORWARD ERROR CORRECTION (FEC) ENCODING AND DECODING METHOD OF VARIABLE LENGTH PACKET BASED ON THREE-DIMENSIONAL STORAGE APPARATUS - Provided is a Forward Error Correction (FEC) encoding method of a variable-length packet using a three-dimensional (3D) storage apparatus. In the FEC encoding method, an FEC coding may be performed to calculate a corresponding parity packet while an input data packet is imaginarily connected to the 3D storage apparatus having a predetermined storage width and data area height to be arranged, the calculated parity packet may be stored and arranged in a vertical direction and a depth direction of the 3D storage apparatus, and an expansion data packet including both information for restoration of a data packet and the data packet may be transmitted together with the parity packet.06-23-2011
20100023840ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM - A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.01-28-2010
20100023839Memory system and memory error cause specifying method - Provided is a memory system that can specify a cause of an error. According to the memory system, during writing, when write data is looped back, and the write data is an error, the error has occurred between first processing units (01-28-2010
20100017682Error correction code striping - A method is disclosed which decreases the amount of error correction code data required to detect and correct errors in digital data while still maintaining a specified ability to correct errors in large groups of contiguous data. The present invention accomplishes this by placing distance either in space or in time between bytes grouped mathematically for error correction code calculations. An error affecting contiguous bytes, like scratches or other defects in digital storage media, or certain types of interference in either wired or wireless digital communications, would affect many error correction code groups, but would only affect one byte from each group. The error can easily be corrected using only a one dimensional error correction code, removing the need for a two dimensional product error correction code and the additional data overhead that the column ECC data necessarily adds to the block.01-21-2010
20110307761MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION - For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.12-15-2011
20090172497DATA PROCESSING SYSTEM AND METHOD FOR PROCESSING OPTICAL INFORMATION - Provided is a data processing system for recording holographic optical information. The data processing system includes: a data interface constructing a data page by using data transmitted from a host information device; a memory storing data transmitted from the data interface; an encoder ECC-encoding data that is stored in the memory; and a modulator modulating the encoded data so as to record optical information. Accordingly, it is possible to efficiently transmit data when recording and reproducing holographic optical information.07-02-2009
20120210193MEMORY AND METHOD FOR CHECKING READING ERRORS THEREOF - A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.08-16-2012
20110167319ERROR CORRECTION IN A STACKED MEMORY - Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.07-07-2011
20120023384SYSTEM AND METHOD OF DISTRIBUTIVE ECC PROCESSING - Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.01-26-2012
20120023385Method for adding redundancy data to a distributed data storage system and corresponding device. - The invention proposes a method and device for adding redundancy data in a distributed data storage system. Among others, the invention allows to keep impact on network resources low through the use of coordinated regenerating codes according to the invention.01-26-2012
20120159284SEMICONDUCTOR MEMORY DEVICE CAPABLE OF TRANSFERRING VARIOUS TYPES OF DATA - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer unit, an error correction unit, a data transfer unit, a memory unit, a data input/output unit, a data bus, and a control unit. The control unit controls a first operating mode in which the memory unit is used and a second operating mode in which the memory unit is not used. In the second operating mode, the data transfer unit transfers the data supplied to the input/output unit through the data bus, to the data buffer unit, transfers the data transferred to the data buffer, to the error correction unit and transfers parity data generated in the error correction unit, to the buffer unit.06-21-2012
20120159283LOW OVERHEAD ERROR CORRECTING CODE PROTECTION FOR STORED INFORMATION - Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values.06-21-2012
20120072804DATA READ-OUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READING IN SEMICONDUCTOR MEMORY DEVICE - A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.03-22-2012
20120072803SEMICONDUCTOR STORAGE DEVICE, MEMORY CONTROL DEVICE, AND CONTROL METHOD OF SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.03-22-2012
20110107182DISPERSED STORAGE UNIT SOLICITATION METHOD AND APPARATUS - A method begins by a dispersed storage processing module obtaining data for storage. The method continues with the dispersed storage processing module soliciting dispersed storage (DS) units to store encoded data slices of the data. The method continues with the dispersed storage processing module receiving favorable responses from a set of DS units. The method continues with the dispersed storage processing module encoding the data in accordance with an error coding dispersal storage function and in accordance with the favorable responses.05-05-2011
20110107179METHOD AND APPARATUS FOR ERROR CORRECTION ON A MOBILE DEVICE - A method and apparatus for distributing dynamically reconfigurable content to a mobile device is provided. One embodiment of a method for encoding a data stream to enable error correction by a receiver of the data stream includes storing a block of the data stream in a first memory array, processing the first memory array to produce a second memory array, inverting the second memory array, and storing the second memory array, as inverted, as a third memory array.05-05-2011
20110107180INTENTIONALLY INTRODUCED STORAGE DEVIATIONS IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a first request to store a program. The method continues with the processing module determining first error coding dispersal storage function parameters and encoding a data segment of the program. The method continues with the processing module determining whether a second request to store the program is received. The method continues with the processing module encoding a second data segment of the program in accordance with the first error coding dispersal storage function parameters when the second request is not received. The method continues with the processing module changing the first error coding dispersal storage function parameters based on the another request to produce second error coding dispersal storage function parameters when the second request is received. The method continues with the processing module encoding the second data segment in accordance with the second error coding dispersal storage function parameters.05-05-2011
20100095187FILE SERVER FOR REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) SYSTEM - A redundant array of independent disks system includes a first storage array with a first target processing module and a first plurality of storage devices. A second storage array includes a second target processing module and a second plurality of storage devices. A data processing module receives a plurality of data blocks for storage in one or more of the first and second plurality of storage devices. The data processing module assigns a first data block of the plurality of data blocks to the first target processing module and a second data block of the plurality of data blocks to the second target processing module. The first and second target processing modules concurrently generate first and second error checking and correcting data based on the first data block, respectively.04-15-2010
20110099459SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory array, an error correction code circuit, and a timing control signal generator configured to, based on a first timing control signal used to control a timing at which data to be input to the error correction code circuit is transferred to the error correction code circuit, generate a second timing control signal used to control a timing at which data output from the error correction code circuit is transferred to another circuit. The timing control signal generator includes a circuit which is the same as or corresponds to at least a portion of the error correction code circuit, and is configured to delay a timing of the first timing control signal by a period of time corresponding to a delay time of the error correction code circuit, and output the second timing control signal, depending on the delayed timing.04-28-2011
20110099458ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT - The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.04-28-2011
20120124449METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS - Subject matter disclosed herein relates to read and write processes of a memory device.05-17-2012
20090132890Anamorphic Codes - The error tolerance of an array of m storage units is increased by using a technique referred to as “dodging.” A plurality of k stripes are stored across the array of storage units in which each stripe has n+r elements that correspond to a symmetric code having a minimum Hamming distance d=r+1. Each respective element of a stripe is stored on a different storage unit. An element is selected when a difference between a minimum distance of the donor stripe and a minimum distance of a recipient stripe is greater or equal to 2. The selected element is also stored on a storage unit having no elements of the recipient stripe. A lost element of the recipient stripe is then rebuilt on the selected element.05-21-2009
20090132889MEMORY CONTROLLER SUPPORTING RATE-COMPATIBLE PUNCTURED CODES - Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.05-21-2009
20120317458MEMORY CONTROLLER AND NON-VOLATILE STORAGE DEVICE - A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.12-13-2012
20120131418MEMORY DEVICE - According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.05-24-2012
20120131419MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION - Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.05-24-2012
20100205508Redundant Data in Storage Medium - A data storage medium may have data stored on one physical portion of the medium and error correction and recovery data stored on a second physical portion of the medium. In one embodiment, a write once, read many medium may be written with data and the remaining capacity of the medium may be filled with error correction and recovery data. If a portion of the main data is corrupted, the error correction and recovery data may be used to recreate the corrupted data. The error correction and recovery data may be created to fill the unused capacity of the medium by prioritizing and selectively backing up the data when the data use more than half of the medium's capacity, or may create one or more redundant copies of the data if the data consume less than half of the medium's capacity, for example.08-12-2010
20110185260Storage of data in data stores having some faulty storage locations - Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.07-28-2011
20110185258SELECTING STORAGE FACILITIES AND DISPERSAL PARAMETERS IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data storage request that includes metadata and data. The method continues with the processing module determining a base-line set of error coding dispersal storage function parameters based on the metadata. The method continues with the processing module identifying candidate dispersed storage (DS) units based on the base-line set of error coding dispersal storage function parameters. The method continues with the processing module selecting DS units of the candidate DS units based on the metadata to produce selected DS units. The method continues with the processing module dispersed storage error encoding the data in accordance with at least a representation of the base-line set of error coding dispersal storage function parameters to produce a set of encoded data slices. The method continues with the processing module sending the set of encoded data slices to the selected DS units for storage therein.07-28-2011
20110185257SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR - A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.07-28-2011
20120137193DISC RECORDING MEDIUM, DISK DRIVE APPARATUS, REPRODUCTION METHOD, AND DISK MANUFACTURING METHOD - A recording and reproducing area and a reproduction-only area are formed by wobbling a groove formed in a spiral fashion to form a track to be tracked on a disk. The recording and reproducing area has address information recorded by wobbling of the groove and information recorded and reproduced by phase change marks on the track formed by the groove where the address information is recorded. The reproduction-only area has prerecorded information recorded by wobbling of the groove.05-31-2012
20120254695DYNAMIC ELECTRONIC CORRECTION CODE FEEDBACK TO EXTEND MEMORY DEVICE LIFETIME - Unrecoverable electronic correction code (ECC) errors in memory storage devices are usually preceded by recoverable ECC errors. A memory storage device controller is provided notice of the recoverable errors and associated information. The memory storage device controller can cause the data having the recoverable information to be rewritten on the memory storage device. Rewriting the data on the memory storage device (often in a different location) normally reduces the probability of encountering data with unrecoverable data errors.10-04-2012
20120254687PRE-FETCHING DATA SEGMENTS STORED IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data segment retrieval request regarding a data segment, which is stored in a dispersed storage network (DSN) memory. The method continues with the processing module processing the data segment retrieval request, determining pre-fetch segment buffering information, and when the pre-fetch segment buffering information indicates pre-fetching one or more other data segments, generating one or more pre-fetch segment retrieval requests for the one or more other data segments, receiving, one or more sets of at least a decode threshold number of encoded data slices, decoding, in accordance with a dispersed storage error coding function, the one or more sets of at least a decode threshold number of encoded data slices to reproduce the one or more other data segments, and updating a pre-fetch segment buffer with the one or more other data segments.10-04-2012
20120254693ENCODING A DATA WORD FOR WRITING THE ENCODED DATA WORD IN A MULTI-LEVEL SOLID STATE MEMORY - A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ε [1, . . . , q−1], depending on a state of the N cells.10-04-2012
20120254696EFFICIENT RE-READ OPERATIONS IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.10-04-2012
20120317459SYSTEMS AND METHODS FOR OPERATING ON A STORAGE DEVICE USING A LIFE-CYCLE DEPENDENT CODING SCHEME - Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.12-13-2012
20120216096Memory Device and Memory System - A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.08-23-2012
20110209031Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices - Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.08-25-2011
20100281341NON-VOLATILE MEMORY MANAGEMENT METHOD - A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.11-04-2010
20100275100DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD - A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by b10-28-2010
20120254697METHOD AND APPARATUS FOR DISPERSED STORAGE MEMORY DEVICE SELECTION - A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.10-04-2012
20120254690UTILIZING LOCAL MEMORY AND DISPERSED STORAGE MEMORY TO ACCESS ENCODED DATA SLICES - A method begins by a processing module encoding data utilizing a dispersed storage error coding function to produce a set of encoded data slices, wherein the dispersed storage error coding function includes a decode threshold parameter and a pillar width parameter. The method continues with the processing module storing a number of encoded data slices of the set of encoded data slices in a local memory, wherein the number is based on the decode threshold parameter and is less than the pillar width parameter, and outputting remaining encoded data slices of the set of encoded data slices to dispersed storage network (DSN) memory.10-04-2012
20120254691ADJUSTING A DISPERSAL PARAMETER OF DISPERSEDLY STORED DATA - A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust the pillar width parameter based one or more memory performance characteristics. When the pillar width parameter is to be decreased, the method continues with the processing module identifying one or more pillars within a memory to delete to produce one or more identified pillars, identifying encoded data slices of one or more of the data files stored in the one or more identified pillars to produce identified encoded data slices, and deleting the identified encoded data slices.10-04-2012
20120254689UPDATING ERROR RECOVERY INFORMATION IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module updating an encoded data slice of a set of encoded data slices to produce an updated encoded data slice and sending the updated encoded data slice to a first DS unit of a set of DS units. The method continues with the first DS unit storing the updated encoded data slice and generating partial error recovery information to produce a collection of partial error recovery information. The method continues with the first DS unit outputting the collection of partial error recovery information for storage in at least some of the set of DS units. The method continues with one of the at least some of the set of DS units updating error recovery information of an encoded data slice based on a corresponding one of the collection of partial error recovery information.10-04-2012
20120221924APPARATUS, SYSTEM, AND METHOD FOR DETECTING AND REPLACING FAILED DATA STORAGE - An apparatus, system, and method are disclosed for detecting and replacing failed data storage. A read module reads data from an array of memory devices. The array includes two or more memory devices and one or more extra memory devices storing parity information from the memory devices. An ECC module determines, using an error correcting code (“ECC”), if one or more errors exist in tested data and if the errors are correctable using the ECC. The tested data includes data read by the read module. An isolation module selects a memory device in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with replacement data and available data wherein the tested data includes the available data combined with the replacement data.08-30-2012
20120221923MEMORY SYSTEM AND MEMORY MODULE CONTROL METHOD - A memory system includes a memory module of first to eighth semiconductor memories of an n-bit input/output type; and a memory control unit configured to generate three n-bit error detection and correction codes based on four n-bit data received from an external system, respectively store the four n-bit data in the first to fourth semiconductor memories, and respectively store the three n-bit error detection and correction code in the fifth to seventh semiconductor memories. When reading the four n-bit data stored in the first to fourth semiconductor memories, the memory control unit executes error detection to every two of the four n-bit data read from the first to fourth semiconductor memories based on the three n-bit error detection and correction code stored in the fifth to seventh semiconductor memories and executes error correction to one n-bit data related to an error, of the four n-bit data.08-30-2012
20120084627DATA RECOVERY USING OUTER CODEWORDS STORED IN VOLATILE MEMORY - Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.04-05-2012
20120260146DATA STORAGE DEVICE RELATED METHOD OF OPERATION - A method is provided for operating a data storage device comprising a storage medium and a controller configured to control operations of the storage medium. The method comprises determining whether a read-requested data strip is an error data strip, reading a plurality of data strips in a stripe comprising the read-requested data strip when the read-requested data strip is the error data strip, outputting a data strip recovered using the other data strip except the error data strip among the plurality of data strips, and writing the recovered data strip and the other data strips into the storage medium.10-11-2012
20120226959ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES - Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.09-06-2012
20120226961EFFICIENT REDUNDANT MEMORY UNIT ARRAY - A method of storing data is disclosed. A set of data blocks, including a plurality of proper subsets of data blocks, is stored. A plurality of first-level parity blocks is generated, wherein each first-level parity block is generated from a corresponding proper subset of data blocks within the plurality of proper subsets of data blocks without reference to other data blocks not in the corresponding proper subset. A second-level parity block is generated, wherein the second level parity block is generated from a plurality of data blocks included in at least two of the plurality of proper subsets of data blocks, and wherein recovery of a lost block in a given proper subset of data blocks is possible without reference to any data blocks not in the given proper subset.09-06-2012
20090019340NON-SYSTEMATIC CODED ERROR CORRECTION - Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.01-15-2009
20120260147Efficient Readout from Analog Memory Cells Using Data Compression - A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed.10-11-2012
20080301525DATA REFRESH APPARATUS AND DATA REFRESH METHOD - According to one embodiment, a data refresh apparatus which refreshes data stored in a storage device having storage areas, comprises an error detector configured to detect a number of errors of data stored in a storage area of the storage device, an error correction unit configured to execute an error correction for the data stored in the storage area and generate corrected data, a refresh unit configured to write the corrected data to one of the storage areas, and a refresh controller configured to control an operation cycle of the refresh unit according to a number of times of write operations with respect to the storage area.12-04-2008
20110004806DATA RECEIVING CIRCUIT AND DATA PROCESSING METHOD - A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.01-06-2011
20110004805Semiconductor Memory Device Capable of Reducing Current in PASR Mode - A semiconductor memory device capable of reducing current consumption in a partial-array self-refresh (PASR) mode includes a plurality of banks and at least one parity bank. A specific area to be self-refreshed is individually selected from each of some banks selected out of the plurality of banks to perform a self-refresh operation. Data of the specific area to be self-refreshed is verified using an error correction code (ECC) stored in the parity bank.01-06-2011
20100100794Method and controller for data access in a flash memory - A method for controlling access to data in a Flash is provided, including steps as follows: outputting at least one main data block to a buffer area of the Flash continuously, the buffer area of the Flash being adapted to buffer data to be inputted to a storage area of the Flash; generating and buffering checksum data for each main data block while outputting the at least one main data block; and outputting the buffered checksum data of the at least one main data block to the buffer area of the Flash. Another method for controlling access to data in the Flash, apparatuses corresponding to the methods and methods for controlling data access by a controller are also provided. The efficiency of data access in the Flash is raised.04-22-2010
20120266045MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.10-18-2012
20110131470MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.06-02-2011
20120240010Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.09-20-2012
20120266047ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY - Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level10-18-2012
20120266044NETWORK-CODING-BASED DISTRIBUTED FILE SYSTEM - A network-coding-based distributed file system (NCFS) is disclosed. The NCFS may include a file system layer, a disk layer, and a coding layer. The file system layer may be configured to receive a request, for an operation on data within a data block, to specify the data block to be accessed in a storage node of a plurality of storage nodes. The disk layer may provide an interface to the file system to provide access the plurality of storage nodes via a network. The coding layer may be connected between the file system layer and the disk layer, to encode and/or decode functions of fault-tolerant storage schemes based on a class of maximum distance separable (MDS) codes. Additional apparatus, systems, and methods are disclosed.10-18-2012
20120266043SEMICONDUCTOR MEMORY DEVICE - The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.10-18-2012
20120324312SELECTIVE MASKING FOR ERROR CORRECTION - Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The data processing device employs multiple-mapped or multi-port memory, whereby different memory addresses can be associated with the same memory location. To generate the ECC checkbits the data processing device selects a mask for each write access based on the write address and determines the ECC checkbits based on the write data, the write address, and the mask.12-20-2012
20120324313ENCODING A DATA WORD FOR WRITING THE ENCODED DATA WORD IN A MULTI-LEVEL SOLID STATE MEMORY - A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ε [1, . . . , q-1], depending on a state of the N cells.12-20-2012
20110239090Storage apparatus and fault diagnosis method - In a storage apparatus: a write-address counter outputs a write address; an input-data inverter inverts input data to be inputted into a storage unit; an input-data selector selects one of the input data and the inverted input data on the basis of one or more first bits constituting the write address, and writes the one of the input data and the inverted input data in the storage unit on the basis of one or more second bits constituting the write address; a read-address counter outputs the read address; an output-data inverter inverts output data outputted from the storage unit on the basis of one or more third bits constituting the read address; and an output-data selector selects and outputs one of the output data and the inverted output data on the basis of one or more fourth bits constituting the read address.09-29-2011
20110239089Methods and Apparatus for Soft Data Generation for Memory Devices Using Decoder Performance Feedback - Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.09-29-2011
20120131417CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY - Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.05-24-2012
20120278682ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.11-01-2012
20120278681SELECTIVE ERROR DETECTION AND ERROR CORRECTION FOR A MEMORY INTERFACE - Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.11-01-2012
20120278683DATA DISTRIBUTION UTILIZING UNIQUE WRITE PARAMETERS IN A DISPERSED STORAGE SYSTEM - A method begins by a processing module receiving a plurality of record requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the processing module generating a list of requesting device identities corresponding to the plurality of requests and storing the plurality of sets of encoded data slices and the list of requesting device identities in a dispersed storage network memory. The method continues with the processing module receiving a playback request from a device identified in the list of requesting device identities, generating a unique retrieval matrix for the device, and outputting a unique plurality of sets of encoded data slices from the plurality of sets of encoded data slices in accordance with the unique retrieval matrix.11-01-2012
20110276857DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF - A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.11-10-2011
20120096330ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS - A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.04-19-2012
20120096329METHOD OF, AND APPARATUS FOR, DETECTION AND CORRECTION OF SILENT DATA CORRUPTION - There is provided a method of writing data to a sector of a storage device, the sector comprising a data field and a protection information field and having identifying information identifying the location of said sector. The method comprises providing data to be written to an intended sector, generating, for said intended sector, a message comprising the data and the identifying information of said intended sector and performing, on said message, error correcting encoding to generate a codeword. The codeword comprises the message and parity information generated from said error correcting coding. The data can then be written to the data field of the sector, and the parity information can be written to said protection information field of the sector.04-19-2012
20110307760METHOD AND APPARATUS FOR PARALLEL PROCESSING IN A GIGABIT LDPC DECODER - A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-density parity check (LDPC) decoder associated with the receive path circuitry for decoding the encoded received signal. The LDPC decoder further comprises a memory for storing a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a −1 value; and a plurality of processing elements for performing LDPC layered decoding, wherein at least one processing element is operable to process in the same cycle a first row and a second row of the parity check H matrix.12-15-2011
20110320913RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT - Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.12-29-2011
20120102380SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY SYSTEM, AND ERASURE CORRECTION METHOD - A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.04-26-2012
20120102379SYSTEM AND METHOD OF INTERLEAVING DATA ACCORDING TO AN ADJUSTABLE PARAMETER - A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.04-26-2012
20100199148System and Method for Constructing Multi-Write Error Correcting Code - An embodiment of the invention relates to a memory device and a related method. In an embodiment, a check matrix for an error-correcting code is formed so that sets of input data bits can be written, wherein each set of input data bits generates one set of error-correcting code bits that can be written independently of each other and in an arbitrary order. An error-correcting code is thereby produced without the need to erase or copy any existing, originally written bit upon presentation of new input data.08-05-2010
20100192044QC-LDPC CODE DECODER AND CORRESPONDING DECODING METHOD - An efficient general QC-LDPC code decoder includes a general-purpose processor for distributing the storage space of the data memory block, and establishing an index for data addressing; a data memory block for storing the information used during decoding; a hardware accelerator for conducting part or all of the information processing operations including parity check, check node updating and variable node updating. A corresponding QC-LDPC code decoding method includes initializing the variable node information and performing parity check on the check matrix row block by row block; updating the check node row block by row block and updating the variable node column block by column block if any check equation is not met.07-29-2010
20130013977ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES - Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.01-10-2013
20130019143Memory Device And Method Of Storing Data With Error Correction Using Codewords - Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.01-17-2013
20130019141Min-Sum Based Non-Binary LDPC DecoderAANM Wang; Chung-LiAACI San JoseAAST CAAACO USAAGP Wang; Chung-Li San Jose CA USAANM LI; ZongwangAACI San JoseAAST CAAACO USAAGP LI; Zongwang San Jose CA USAANM Yang; ShaohuaAACI San JoseAAST CAAACO USAAGP Yang; Shaohua San Jose CA US - Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors.01-17-2013
20130019142MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOFAANM Teo; Wei-ChenAACI Miaoli CountyAACO TWAAGP Teo; Wei-Chen Miaoli County TWAANM Yang; Pi-ChiAACI Miaoli CountyAACO TWAAGP Yang; Pi-Chi Miaoli County TW - A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device having an error checking and correcting (ECC) circuit and a rewritable non-volatile memory chip is coupled to a host system. The method includes determining whether write data to be written into the rewritable non-volatile memory chip belongs to a specific type. The method also includes generating at least one first type ECC code with a first length by the ECC circuit according to the write data if the write data belongs to the specific type. The method further includes generating at least one second type ECC code with a second length by the ECC circuit according to the write data if the write data does not belong to the specific type. In which, the first length is longer than the second length.01-17-2013
20130024743SYSTEMS AND METHODS OF STORING DATA - A method of reading data in a data storage device with a controller and a memory includes generating, in the memory, a set of bits corresponding to a particular storage element of the memory. The set of bits indicates a group of threshold voltage intervals. A threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group. At least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group. The method also includes sending the set of bits to the controller. The set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure.01-24-2013
20130024745MEMORY-EFFICIENT LDPC DECODING - To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.01-24-2013
20130024744NONVOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A nonvolatile semiconductor memory outputs the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.01-24-2013
20130173989MEMORY SYSTEM CONTROLLER HAVING SEED CONTROLLER USING MULTIPLE PARAMETERS - In a memory system, a memory controller includes a randomizer and a seed controller. The seed controller provides a seed to the randomizer and includes; a first register block performing a first cyclic shift operation using a first parameter related to the nonvolatile memory device, a second register block performing a second cyclic shift operation using a second parameter related to the nonvolatile memory device, and a seed generating block generating the seed from the first and second cyclic shift results.07-04-2013
20130173990HIGH-THROUGHPUT ITERATIVE DECODING'S DEFECT SCAN IN RETRY MODE OF STORAGE SYSTEM CHANNEL - The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword.07-04-2013
20130173991Facilitating Error Detection And Recovery In A Memory System - The disclosed embodiments relate to a system for accessing a data word in a memory. During operation, the system receives a request to access a data word, wherein the request includes a physical address for the data word. Next, the system translates the physical address into a mapped address, wherein the translation process spreads out the data words and intersperses groups of consecutive error information between groups of consecutive data words. Finally, the system uses the mapped address to access the data word and corresponding error information for the data word from the memory.07-04-2013
20110246857MEMORY SYSTEM AND METHOD - A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.10-06-2011
20110246856Systems and Methods for Efficient Data Storage - Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.10-06-2011
20080222491FLASH MEMORY SYSTEM FOR IMPROVING READ PERFORMANCE AND READ METHOD THEREOF - A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation.09-11-2008
20080222490METHOD, APPARATUS, AND SYSTEM FOR DYNAMIC ECC CODE RATE ADJUSTMENT - A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.09-11-2008
20130179750SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.07-11-2013
20130179749METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page.07-11-2013
20130179751MEMORY DEVICE WITH ECC HISTORY TABLE - A method of reading data from a memory device is disclosed. The method comprises accessing preexisting data from a location in the memory device in response to a read command and identifying an error in the preexisting data. The identified error is corrected for transmission as corrected data. Error information representing the identified error is stored while the pre-existing data is retained in the location of the memory device in uncorrected form.07-11-2013
20120254694REDUNDANT STORAGE IN NON-VOLATILE MEMORY BY STORING REDUNDANCY INFORMATION IN VOLATILE MEMORY - A method for data storage includes storing two or more data items in a non-volatile memory. Redundancy information is calculated over the data items, and the redundancy information is stored in a volatile memory. Upon a failure to retrieve a data item from the non-volatile memory, the data item is reconstructed from remaining data items stored in the non-volatile memory and from the redundancy information stored in the volatile memory.10-04-2012
20120254692UTILIZING A LOCAL AREA NETWORK MEMORY AND A DISPERSED STORAGE NETWORK MEMORY TO ACCESS DATA - A method begins by a processing module encoding data based on a decode threshold parameter and a pillar width parameter to produce a set of encoded data slices and selecting a local area network (LAN) pillar width value of encoded data slices of the set of encoded data slices for storage in LAN available memories, wherein the LAN pillar width value is based on the decode threshold parameter, the pillar width parameter, and quantities of the LAN available memories. The method continues with the processing module selecting a wide area network (WAN) pillar width value of encoded data slices of the set of encode data slices for storage in a dispersed storage network (DSN) memory of a wide area network, wherein the WAN pillar width value is based on the decode threshold parameter and the pillar width parameter.10-04-2012
20120254688APPENDING DATA TO EXISTING DATA STORED IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a request to store data in dispersed storage network (DSN) memory and determining whether the data is to be appended to existing data. When the data is to be appended, the method continues with the processing module encoding, using an append dispersed storage error coding function, the data to produce a set of encoded append data slices, generating a set of append commands, wherein an append command of the set of append commands includes an encoded append data slice of the set of encoded append data slices and identity of one of a set of dispersed storage (DS) units, and outputting at least a write threshold number of the set of append commands to at least a write threshold number of the set of DS units.10-04-2012
20120254686NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES AND ERROR CORRECTION METHODS - An error correction unit is an area in a page where the error bit count is low, and an error correction unit is an area in a page where the error bit count is high. The error correction unit includes a user data area, a first redundancy area, and a second redundancy area. The error correction unit includes a user data area, a first redundancy area, and a second redundancy area. Errors in the user data areas are corrected with a first set of redundant bits stored in the first redundancy areas, respectively. A second set of redundant bits for correcting errors in the user data area within the high-error bit count page is stored in the second redundancy area within the low-error bit count page and the second redundancy area within the high-error bit count page in a distributed manner.10-04-2012
20130097471ERROR CORRECTION IN A STACKED MEMORY - Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.04-18-2013
20130097472Systems and Methods for Out of Order Y-Sample Memory Management - Systems and methods for out of order memory management.04-18-2013
20110314355ACCESSING DATA STORED IN A DISPERSED STORAGE MEMORY - A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.12-22-2011
20130104002MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.04-25-2013
20110276858MEMORY SYSTEM - A memory system comprises an encoding processing circuit 11-10-2011
20130145232Computing Core Application Access Utilizing Dispersed Storage - A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to store a data result from a processing module and determines whether to store the data result in an error encoded format. When the memory controller determines to store the data result in the error encoded format, it facilitates encoding the data result in accordance with a dispersed storage error coding function to produce one or more sets of encoded data slices. The memory controller then determines where to store the one or more sets of encoded data slices and provides the one or more sets of encoded data slices to one or more identified memories for storage.06-06-2013
20110219286DECODING DEVICE, DATA COMMUNICATION APPARATUS HAVING THE DECODER DEVICE, AND DATA MEMORY - A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.09-08-2011
20110219284NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.09-08-2011
20080201626POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE - The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.08-21-2008
20130145231Data Encoder and Decoder Using Memory-Specific Parity-Check Matrix - An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.06-06-2013
20110252289ADJUSTING STORAGE DEVICE PARAMETERS BASED ON RELIABILITY SENSING - In general, this disclosure is directed to techniques for adjusting storage device parameters based on reliability sensing. According to one aspect, a method includes retrieving a codeword from a plurality of data blocks within a storage device, wherein each of the data blocks stores a respective portion of the codeword, generating a detected value for a bit within a first portion of the codeword based on information related to a reliability of a data block associated with the first portion, and performing error correction on a second portion of the codeword based on the detected value for the bit within the first portion of the codeword. According to another aspect, a method includes obtaining information related to a reliability of a data block within a storage device, and adjusting a data capacity for the storage device based on the information related to the reliability of the data block.10-13-2011
20110239088NON-REGULAR PARITY DISTRIBUTION DETECTION VIA METADATA TAG - This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.09-29-2011
20130151925Distributed Computing in a Distributed Storage and Task Network - A method begins by a dispersed storage (DS) processing module selecting a set of distributed storage and task (DST) execution units for executing a task and determining dispersed storage error coding parameters for data. The method continues with the DS processing module dispersed storage error encoding the data in accordance with the parameters to produce a plurality of encoded data blocks and grouping the plurality of encoded data blocks into a plurality of encoded data block groupings. The method continues with the DS processing module partitioning the task into a set of partial tasks, outputting at least some of the plurality of encoded data block groupings to the set of DST execution units, and outputting the set of partial tasks to the set of DST execution units for execution of the set of partial tasks on the at least some of plurality of encoded data block groupings.06-13-2013
20130151926Storing Data in a Distributed Storage Network - A method begins by a dispersed storage (DS) processing module mapping a set of data partitions to a set of storage regions. For each data partition, the method continues with the DS processing module segmenting the data partition into a plurality of data segments and designating a first data segment. The method continues with the DS processing module generating data storage mapping information. The method continues with the DS processing module encoding the data storage mapping information to produce at least one set of encoded mapping information slices and for each data partition, encoding the plurality of data segments to produce a plurality of sets of encoded data slices. The method continues with the DS processing module outputting the at least one set of encoded mapping information slices and, for each data partition, the plurality of sets of encoded data slices to the DSN for storage therein.06-13-2013
20130151927Executing Partial Tasks in a Distributed Storage and Task Network - A method begins by a dispersed storage (DS) processing module receiving a partial task regarding an encoded data block grouping. The method continues with the DS processing module performing the partial task on the encoded data block grouping to produce a partial task result and determining subsequent treatment of the partial task result. When the subsequent treatment includes storage of the partial task result, the method continues with the DS processing module determining a manner in which the partial task result is to be stored. When the manner in which the partial task result is to be stored is dispersed storage, the method continues with the DS processing module dispersed storage error encoding the partial task result to produce one or more sets of encoded partial task result blocks and outputting the one or more sets of encoded partial task result blocks to a set of DST execution units.06-13-2013
20130151928Transforming Data in a Distributed Storage and Task Network - A method begins by a dispersed storage (DS) processing module determining whether at least a portion of temporarily stored data is to be stored long-term, wherein the temporarily stored data is stored in a set of distributed storage and task (DST) units in accordance with a computational-orientated dispersed storage error coding function. When the at least a portion of the temporarily stored data is to be stored long-term, the method continues with the DS processing module identifying one or more DST storing the at least a portion of the temporarily stored data, recovering the at least a portion of the temporarily stored data, dispersed storage error encoding the at least a portion of the temporarily stored data in a pre-dispersed storage error encoded format into a plurality of sets of encoded data slices, and storing the plurality of sets of encoded data slices in the set of DST units.06-13-2013
20100299576System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods - A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.11-25-2010
20120284586Controller of Memory Device and Method for Operating the Same - A controller of a memory device which accesses a memory of the memory device having a data storage area and a data correction area. The controller includes a mode selection unit When the memory works with a first operation voltage, the mode selection unit selects a first mode of the controller, and the controller writes input data into the data storage area to serve as storage data and reads the storage data from the data storage area. When the memory works with a second operation voltage, the mode selection unit selects a second mode of the controller, and the controller performs a correction function to encode the input data to generate encoded input data, writes the encoded input data into the data storage area and the data correction area to respectively serve as the storage data and correction data, and reads and decodes the storage data and the correction data.11-08-2012
20130159813MEMORY CONTROLLER ECC - Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.06-20-2013
20110314356VERIFYING INTEGRITY OF DATA STORED IN A DISPERSED STORAGE MEMORY - A method for verifying integrity of data stored in dispersed storage memory begins by a processing module retrieving integrity information of the data that is stored as a set of forward error correction (FEC) encoded words in the dispersed storage memory and continues with the processing module receiving FEC encoded words of the set of FEC encoded words from the dispersed storage memory to produce received FEC encoded words and decoding a unique subset of the received FEC encoded words to produce recovered data. The method continues with the processing module generating recovered integrity information from the recovered data and comparing the recovered integrity information with the integrity information. The method continues with the processing module indicating that at least one of the received FEC encoded words of the unique subset of the received FEC encoded words is corrupt when the recovered integrity information compares unfavorably with the integrity information.12-22-2011
20120290896MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY CONTROLLER - A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.11-15-2012
20120005557VIRTUAL COPY AND VIRTUAL WRITE OF DATA IN A STORAGE DEVICE - A storage device with a memory and a controller, and a method of copying data on a storage device are provided to perform virtual copy and virtual write of data in a storage device without physically storing data in the storage device. The controller includes, or incorporates with an executable module that handles a command to copy data from a source logical address to a destination logical address, where the source logical memory address data is already associated with a first physical memory address storing the data.01-05-2012
20120017136SYSTEMS AND METHODS FOR ENCODING INFORMATION FOR STORAGE IN AN ELECTRONIC MEMORY AND FOR DECODING ENCODED INFORMATION RETRIEVED FROM AN ELECTRONIC MEMORY - Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the encoded information. One embodiment of the present invention encodes k information bits and writes the encoded k information bits to an electronic memory, the method comprising systematically encoding the k information bits to produce a vector codeword, with additional parity bits so that the codeword is resilient to bit-transition errors that may occur during storage of the codeword in, and retrieval of the codeword from, the electronic memory, ensuring that the codeword does not violate a weight constraint, and writing the codeword to the electronic memory.01-19-2012
20130198586DATA STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS AND DATA STORAGE METHOD IN THE SAME - According to one embodiment, a data storage control apparatus includes an interface module and a controller. The interface module receives first data, in specific units, from a host and stores the data in a buffer memory. The controller generates second data from the first data stored in the buffer memory, and performs a control to write the second data to a nonvolatile storage medium. The controller generates the second data of a second format having the same size as the first format of the data stored in an ordinary recording area provided at the nonvolatile storage medium, and including a plurality of units of the first data and invalid data. The controller further performs a control to write the second data in a save area provided on the nonvolatile storage medium.08-01-2013
20130198588IDENTIFYING A POTENTIALLY COMPROMISED ENCODED DATA SLICE - A method begins by a dispersed storage (DS) processing module selecting a data segment and verifying integrity values of encoded data slices generated by encoding the data segment. When integrity values of a decode threshold number of encoded data slices are affirmatively verified, the method continues with the DS processing module verifying an integrity value of the data segment. When the integrity value of the data segment is affirmatively verified, the method continues with the DS processing module generating a new set of encoded data slices. The method continues with the DS processing module verifying concurrency of the set of encoded data slices with the new set of encoded data slices and for each encoded data slice having a negative concurrency verification, flagging the encoded data slice as being potentially compromised.08-01-2013
20130198585METHOD OF, AND APPARATUS FOR, IMPROVED DATA INTEGRITY - There is provided a method of writing data to a data sector of a storage device. The data sector has at least one parity sector associated therewith, each sector being configured to include a data field and a data integrity field. The data integrity field including a guard field, an application field and a reference field. The method includes providing data to be written to an intended sector; generating, for the intended sector, version information for the sector; generating a version vector based on the version information for the data sector; and writing the data to the data field of the data sector; writing the version information to the application field of the data sector; and writing the version vector to the application field of the parity sector.08-01-2013
20130198587MEMORY BUFFER PERFORMING ERROR CORRECTION CODING (ECC) - A memory system includes a semiconductor memory device, a memory controller for controlling the semiconductor memory device, and a memory buffer connected between the semiconductor memory device and the memory controller. The memory buffer is configured to perform error correction coding (ECC) on first data that is received from the memory controller to be stored in the semiconductor memory device and to perform ECC on second data read from the semiconductor memory device.08-01-2013
20120066567DATA PROCESSING SYSTEM HAVING END-TO-END ERROR CORRECTION AND METHOD THEREFOR - In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.03-15-2012
20120066566ACCESSING MEMORY DURING PARALLEL TURBO DECODING - A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.03-15-2012
20130205181PARTIAL-MAXIMUM DISTANCE SEPARABLE (PMDS) ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.08-08-2013
20130205182APPARATUS AND METHOD FOR A DUAL MODE STANDARD AND LAYERED BELIEF PROPAGATION LDPC DECODER - An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g′( )_lbd calculator.08-08-2013
20120304037OUTER CODE ERROR CORRECTION - Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.11-29-2012
20130091404MEMORY CONTROLLER AND STORAGE DEVICE - According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.04-11-2013
20130091403PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL - The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*G04-11-2013
20130212447Non-Binary LDPC Decoder with Low Latency Scheduling - Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.08-15-2013
20130212448SYSTEM AND METHOD OF SENDING CORRECTION DATA TO A BUFFER OF A NON-VOLATILE MEMORY - A method includes receiving data from a buffer of a non-volatile memory. An error correction coding (ECC) operation is initiated to correct bit errors in the data. Correction data is sent to the buffer to correct the bit errors in the data.08-15-2013

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