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Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714746000 - Digital data error correction

714752000 - Forward correction by block code

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DocumentTitleDate
20080282130DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital broadcasting system and a data processing method are disclosed. Herein, additional encoding is performed on mobile service data, which are then transmitted, thereby providing robustness in the processed mobile service data, so that the mobile service data can respond more strongly against fast and frequent channel changes. The data processing method of a digital broadcast transmitting system includes the steps of forming a RS frame by grouping a plurality of mobile service data bytes that is being inputted, and performing error correction encoding in RS frame units, forming a super frame by grouping a plurality of the error correction encoded RS frame, performing row permutation in super frame units, and dividing the super frame back to RS frames, and dividing the RS frame into a plurality of data groups.11-13-2008
20130031441SYSTEM AND METHOD FOR WIRELESS COMMUNICATION OF UNCOMPRESSED VIDEO HAVING A COMPOSITE FRAME FORMAT - A system and method for efficiently communicating uncompressed video and for efficiently communicating corresponding acknowledgements in a system for wireless communication of uncompressed video are disclosed. In one embodiment, the method includes aggregating multiple subpackets of different types of data into a composite packet. The different types of data may include video, audio, control data, extraneous data files, and others. A robust composite packet configuration can provide for more flexible and more efficient transmission of data on the high rate channel as well as more efficient transmission of acknowledgements on the low rate channel.01-31-2013
20130031440CHECKSUM USING SUMS OF PERMUTATION SUB-MATRICES - A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.01-31-2013
20130031439SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM HAVING THE SAME - A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.01-31-2013
20090024900CYCLIC REDUNDANCY CHECKING IN LANE-BASED COMMUNICATIONS - Various embodiments provide a system and method for cyclic redundancy checking in lane-based data communications. A particular embodiment provides a data stream receiver to receive an input data stream having a plurality of data lanes, and a lane-based CRC generator to generate a set of CRC values, each CRC value of the set of CRC values corresponding to a different data lane of the plurality of data lanes; and generate an aggregated CRC value from the set of CRC values.01-22-2009
20110191652MEMORY READ-CHANNEL WITH SELECTIVE TRANSMISSION OF ERROR CORRECTION DATA - A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.08-04-2011
20090193315System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel - A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.07-30-2009
20080263427System and Method for Optical Disc Encoding/Decoding - The invention provides for an optical disc encoding and decoding system in which in an encode mode the system is arranged to encode Long Distance Code (LDC) clusters from user data and including error correction means for applying error correction to LDC blocks, and interleaving means arranged to form the LDC clusters by interleaving the LDC blocks, wherein the error correction means comprises a plurality of buffers at least one of which is arranged to retrieve data from a SDRAM of the system and to calculate syndromes and at least another of which is arranged to insert parity bytes in the data prior to return to the SDRAM and wherein while the said another of which buffers stores data and calculates syndromes, the said one of which buffers is arranged to insert parity bytes into the data it previously stored, the interleaving means comprising a plurality of buffers arranged for burst access for retrieving data from the SDRAM of the system.10-23-2008
20110202816Distributed processing LDPC (Low Density Parity Check) decoder - Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).08-18-2011
20110202815ERROR DETECTION AND CORRECTION SYSTEM - An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.08-18-2011
20120246540MEMORY CONTROLLER, DEVICES INCLUDING THE SAME, AND OPERATING METHOD THEREOF - An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.09-27-2012
20100077281AUTOMATIC DATA RECOVERY CIRCUIT AND DATA ERROR DETECTION CIRCUIT - An automatic data recovery circuit includes a register, an error detection unit and a data recovery unit. The register stores a register data including an input data and a remainder data generated by a cyclic redundancy check calculation on the input data using a predefined generation polynomial. The error detection unit performs a modular calculation on the register data stored in the register using the predefined generation polynomial to generate an error detection signal indicating whether an error is detected in the register data stored in the register. The data recovery unit recovers the input data when an error is detected in the input data based on the error detection signal and a comparison data generated by comparing the input data stored in the register with a reference voltage using a capacitor.03-25-2010
20100077280SEMICONDUCTOR RECORDING DEVICE - The present invention intends to provide a semiconductor recording device that is able to continuously record data and has high reliability even in a case where writing errors frequently occur. When data to be written is recorded as an error correction code (ECC) in a plurality of physical blocks constituting a nonvolatile memory and a writing error occurred, a time interval between the writing error that occurred immediately before and the present writing error is detected. Then, when the time interval is within a first reference time, an error position management unit registers a writing error occurrence block number and block numbers grouped with the writing error occurrence block in the ECC. Then, the writing error registered in the error position management unit is read at a predetermined timing, and the error is corrected on the basis of the ECC and the corrected data is rewritten. In this manner, since overflow of a buffer memory of the host apparatus can be avoided, real-time recording can be realized even in the case where the writing errors frequently occurred.03-25-2010
20100115374DATA RECOVERY SCHEME - A method of recovering data in a line signal which is predicted to be subjected to repetitive noise impulses, the line signal comprising a series of data frames, the method comprising the steps of: predicting a group comprising one or more frames in said line signal which are expected to be corrupted by a noise signal; blanking said group of one or more frames which are predicted to be corrupted; determining the preceding and succeeding frames adjacent to said group; and including in each said group or more frames one or more parity blocks wherein if said noise signal deviates from its predicted timing interval or duration and corrupts the data carried in one or more of said frames adjacent to said group, the corrupted data is recovered using one or more of said parity blocks of said group of blanked frames and the other one of said adjacent frames.05-06-2010
20130080854ADDRESS ERROR DETECTION - Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.03-28-2013
20090172496TECHNIQUE FOR MEMORY IMPRINT RELIABILITY IMPROVEMENT - One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.07-02-2009
20090158119PARITY ERROR CORRECTION FOR BAND-LIMITED DIGITAL SIGNALS - An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each of the M test samples being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is especially applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples.06-18-2009
20100107035APPARATUS AND METHOD FOR DETECTING AN END POINT OF AN INFORMATION FRAME04-29-2010
20090125782MEMORY SYSTEM AND RELATED METHOD USING SOFTWARE-DEFINED RADIO WITH WRITE-PROTECTED, NON-VOLATILE MEMORY - A software-defined radio includes a radio circuit and an executable radio software system operable with the radio circuit and conforming to the software communications architecture (SCA) specification and defining an operating environment that allows a waveform application to operate with the radio circuit for transmitting and receiving voice and data. A write-protected non-volatile memory is operable with the radio circuit and executable radio software system and has a write enable controlled by a non-driver program such that a wear leveling correction sequence is deferred.05-14-2009
20120166912INTERLEAVING PARITY BITS INTO USER BITS TO GUARANTEE RUN-LENGTH CONSTRAINT - RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.06-28-2012
20120166911DATA STORAGE APPARATUS AND APPARATUS AND METHOD FOR CONTROLLING NONVOLATILE MEMORIES - According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.06-28-2012
20120166910DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A method is provided for performing a write operation in a data storage device comprising a storage medium, a processing unit, and a buffer memory storing data to be transferred to the storage medium under control of the processing unit. The method comprises aggregating data in the buffer memory as a strip group comprising multiple data strips, transferring data strips in at least one strip group to the storage medium, calculating a parity strip based on the transferred data strips of the at least one strip group without additional access to the buffer memory, and transferring the parity strip to the storage medium.06-28-2012
20130047053Systems and Methods for Noise Injection Driven Parameter Selection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.02-21-2013
20090044072BROADCASTING RECEIVER AND BROADCAST SIGNAL PROCESSING METHOD - A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.02-12-2009
20090044071Error Correcting Device - The data error correcting device is provided with: a error correction means which performs an error correction process on a time-series of bits of input data, and produces corrected data and parameters showing an error sensing status at the time of correction; an estimated data producing means which responds to an instruction for data estimation, and produces estimated data configured of a time-series of bits resulting from adjustment of a time-series of bits of input data; and a control means which produces a data estimation instruction based on information included in the corrected data and parameters, and supplies the estimated data to the error correction means instead of the input data.02-12-2009
20090319864METHOD AND APPARATUS FOR DYNAMICALLY CONFIGURABLE MULTI LEVEL ERROR CORRECTION - An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.12-24-2009
20080301523Method of Improving the Interative Decoding of Codes - Disclosed is a method of improving iterative decoding of short codes within a demodulator. The vector of metrics of the bits considered at the output of the demodulator is decoded. The value of the check code of the CRC of the decoded word is compared with a predetermined value. If the value of the CRC is considered to form an acceptable message for the decoding step, the decoded word is transmitted to the recipient. If the value of the CRC is incompatible with a correctly decoded message, then the parameters for iterative decoding of the initial message are modified that were received from the demodulator and executing at least one new iterative decoding step with these new parameters.12-04-2008
20120192033STORAGE APPARATUS, METHOD FOR ACCESSING DATA AND FOR MANAGING MEMORY BLOCK - A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data can be stored into the memory block in a block table according to the number of error correction bits in the memory block so that the sequence in which the memory block is used for storing data is determined.07-26-2012
20120192032DATA STORAGE APPARATUS, MEMORY CONTROL APPARATUS AND METHOD FOR CONTROLLING FLASH MEMORIES - According to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.07-26-2012
20130073923FAST AND RELIABLE WIRELESS COMMUNICATION - A communication system that provides fast and reliable communications. The system is suitable for use in connection with wireless computing devices in which transmission errors may occur because of channel conditions, such as interference. Channel conditions causing transmission errors may be bursty and transient such that the errors temporarily overwhelm an error control code. By combining data received for multiple transmission attempts of a packet that fail error checking or that pass error checking with low reliability, a reliable representation of the packet may be quickly constructed. Though, combining may be omitted when a transmission attempt is received that passes error checking with high reliability.03-21-2013
20130073922METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF ITERATIVE DECODERS ON CHANNELS WITH MEMORY - Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.03-21-2013
20130073921ERROR CORRECTION DEVICE, ERROR CORRECTION METHOD, AND PROCESSOR - An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.03-21-2013
20130061113METHOD OF CORRECTING ERRORS AND MEMORY DEVICE USING THE SAME - A method of correcting errors includes receiving a codeword including main data and parity data stored in a memory cell array to perform an error check and correction (ECC) decoding on the codeword and selectively performing an error correction on the codeword based on a result of the ECC decoding using asymmetry of error occurrence of the main data.03-07-2013
20130061110DATA VERIFICATION USING CHECKSUM SIDEFILE - For facilitating data verification using a checksum in conjunction with a sidefile by a processor device in a computing environment, first block signatures having a first size are calculated for first blocks of a first volume stored on a storage device. The first block signatures are stored to a sidefile. Second block signatures having a second size different from the first size are calculated for second blocks of a second volume stored on the storage device. The second block signatures are stored to the sidefile.03-07-2013
20130061112Multi-Level LDPC Layer Decoder - Various embodiments of the present invention provide methods and apparatuses for multi-level layer decoding of non-binary LDPC codes. For example, an apparatus is disclosed for layer decoding of multi-level low density parity check encoded data. The apparatus includes a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix. The apparatus also includes a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder. The low density parity check decoder is also operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met.03-07-2013
20130061111SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST - The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.03-07-2013
20120226957CONTROLLER, DATA STORAGE DEVICE AND PROGRAM PRODUCT - According to an embodiment of a controller, a bit string manipulating unit manipulates a bit string of manipulation target data based on a predetermined rule. A special data setting unit generates a magic number based on a special data setting request from a host interface, obtains an error detecting code for the magic number, and sends the magic number and the error detecting code as manipulation target data to the bit string manipulating unit to obtain a manipulated manipulation target data. The special data setting unit also extracts logical block address information from the special data setting request, and instructs an access unit to write the magic number in the manipulated manipulation target data to a user data storage area and to write the error detecting code in the manipulated manipulation target data to a redundant area in a storage area located by the logical block address information.09-06-2012
20090031191Wyner-Ziv Coding Based on TCQ and LDPC Codes - An encoder employs a trellis coded quantization (TCQ) unit and a compression unit. The TCQ uses a set of polynomials that have been selected to maximize granular gain. The TCQ unit operates on a block of samples from a source. The compression unit compresses bit planes of the TCQ output, using parity check matrices of corresponding LDPC codes, to obtain corresponding syndromes. The parity check matrices are selected so their compression performance approaches close to the limit for Slepian-Wolf coding. A decoder employs a decoding unit and an estimation unit. The decoding unit decodes the syndromes using side information to produce an estimate for the TCQ output. The side information is correlated with the source. The estimation unit estimates the block of source samples using the estimated TCQ output and the side information. Trellis coded vector quantization may be used as an alternative to TCQ.01-29-2009
20090031190TURBO DECODING SYSTEM, TRANSMISSION POWER CONTROL METHOD AND CDMA MOBILE COMMUNICATION TERMINAL - There are provided a turbo decoding system of a CDMA mobile communication terminal, a transmission power control method, and a CDMA mobile communication terminal in which interference in the other users is suppressed by not increasing the transmission power of a base station to a value over the necessary value and excessive repetitive processing is prevented in the turbo decoding section to reduce consumption power.01-29-2009
20090031192CHANNEL ENCODING APPARATUS AND METHOD - A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.01-29-2009
20120117443DATA PROCESSING DEVICE AND METHOD USING ERROR DETECTION CODE, METHOD OF COMPENSATING FOR DATA SKEW, AND SEMICONDUCTOR DEVICE HAVING THE DATA PROCESSING DEVICE - A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial.05-10-2012
20120198305METHODS AND APPARATUS FOR FAST SYNCHRONIZATION USING QUASI-CYCLIC LOW-DENSITY PARITY-CHECK (QC-LDPC) CODES - For use in a wireless communication network, a transmitter is configured to encode information. The transmitter includes a cyclic redundancy check (CRC) encoder configured to encode a physical broadcast channel (PBCH) message using a cyclic redundancy check. The transmitter also includes a timing dependent cyclic shift block configured to encode information in the PBCH message. The transmitter further includes a quasi-cyclic low-density parity-check (QC-LDPC) encoder configured to encode the PBCH message using a QC-LDPC.08-02-2012
20090254791DATA STORAGE SYSTEM - The present invention is directed to an archival data storage system. The archival data storage system includes write once and read many (WORM) capability, data redundancy, error correction, and access control. The combination of these capabilities enable the archival storage system to be secure, error proof, and reliable. Additionally, to provide fast data access time, solid state storage devices are used in place of conventional tape drive. Solid state storage devices such as, for example, flash memory devices are fast, versatile and reliable.10-08-2009
20120272120Non-Volatile Memory and Method with Post-Write Read and Adaptive Re-Write to Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.10-25-2012
20120233523Programmable Data Storage Management - A method and system for managing storage of one or more data blocks in a programmable data storage device is provided. A data storage controller partitions each of multiple data blocks into multiple sub data blocks comprising a number of bits based on one or more index value descriptors. The data storage controller generates transition vectors from each of the sub data blocks by applying one or more transition functions. The data storage controller encodes one of the transition vectors for each sub data block for obtaining a residual sub data block comprising a reduced number of bits, thereby resulting in increased bit space. The data storage controller generates a composite data block by merging each residual sub data block. The composite data block is configurable for writing to one or more regions in the programmable data storage device free from a disturbance caused by write operations to other regions.09-13-2012
20090013238Multi-code LDPC (Low Density Parity Check) decoder - Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.01-08-2009
20090013237DISTRIBUTED PROCESSING LDPC (LOW DENSITY PARITY CHECK) DECODER - Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).01-08-2009
20130166988MULTI-PHASE ECC ENCODING USING ALGEBRAIC CODES - A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.06-27-2013
20130166989VEHICLE DATA ABNORMALITY DETERMINATION DEVICE - Disclosed is a vehicle data abnormality determination device including a storage unit for pre-storing a 2-byte remainder term which is a result of a CRC arithmetic operation on a target area for arithmetic operations in a predetermined memory area, and an arithmetic operation unit for performing a CRC arithmetic operation while including the 2-byte remainder term in this CRC arithmetic operation. Because when performing the CRC arithmetic operation, the vehicle data abnormality determination device performs the CRC arithmetic operation while including the 2-byte remainder term in this CRC arithmetic operation after performing an arithmetic operation on the target area, the vehicle data abnormality determination device always makes the computed result be zero when the data has not been falsified, and can detect whether or not the data has been falsified easily and properly.06-27-2013
20110072329DTV TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST SIGNAL - A DTV transmitting system includes a first pre-processor for coding first enhanced data having a high priority for forward error correction (FEC) at a first coding rate and expanding the first enhanced data at a first expansion rate, and a second pre-processor for coding second enhanced data having a low priority for FEC at a second coding rate and expanding the second enhanced data at a second expansion rate. The receiving system further includes a data formatter for generating enhanced data packets, a multiplexer for multiplexing the enhanced data packets with main data packets, an RS encoder for RS-coding the multiplexed data packets, and a data interleaver for interleaving the RS-coded data packets and outputting a group of interleaved data packets having a head, a body, and a tail.03-24-2011
20090063931Methods and architectures for layered decoding of LDPC codes with minimum latency - An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.03-05-2009
20110283162ENCODING METHOD, DECODING METHOD, CODER AND DECODER - An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n−1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using equation 1 as a g-th (g=0, 1, . . . q−1) parity check polynomial to satisfy 0:11-17-2011
20090006924FAST DECODING METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE - A fast decoding method for low density parity check (LDPC) code obtains a block from the information received by a digital communication system, and computes the information of a bit node and a check node by a simplified method, and determine the actual value of the bit node from the logarithm likelihood ratio (LLR) estimated value of each bit node. The simplified method of the invention provides a more effective simplified circuit and a faster computation speed than the traditional functions while maintaining the same error code rate as that before the simplification.01-01-2009
20100269015DATA STORAGE DEVICE - A data storage device may include an interface that is arranged and configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller may be arranged and configured to receive a read metadata command for a specified one of the memory devices from the host using the interface, read metadata from the specified memory device and communicate the metadata to the host using the interface.10-21-2010
20090158120HIERARCHICAL CRC SCHEME - A hierarchical cyclic redundancy check (CRC) is provided that enables CRC appending and detection. A message that includes a first message portion and a second message portion is transmitted to two or more receivers. The receivers are not aware of the first message portion. One of the receivers can be aware of the second message portion of the message. Each portion of the message can be encoded with a CRC in order to provide protection. The receiver that is aware of the second message portion is provided a higher level of cyclic redundancy check (CRC) protection than the receivers that are not aware of the second message portions.06-18-2009
20100281338Digital Broadcasting System and Error Correction Method Thereof - A digital broadcasting system comprising of a digital broadcasting station, a set of digital broadcast receivers, and a switched network, wherein the digital broadcasting station transmits a digital signal to the set of digital broadcast receivers, and the digital broadcast receivers exchange error correction information with each other using the network to compensate errors in local receptions of the digital signal at each digital broadcast receiver location.11-04-2010
20110173514DATA PROTOCOL - A method of transmitting data according to a data transmission protocol wherein the data is transmitted as a plurality of data frames and each data frame includes an error checking field comprising at least two sub-fields, the data of the first sub-field being formed by a first error checking method performed on data of the frame and the data of the second sub-field being formed by a second error checking method performed on the said data of the frame, the first and second methods being such that the data of the first sub-field has different error checking properties from those of the data of the second sub-field.07-14-2011
20110302474Ensuring a Most Recent Version of Data is Recovered From a Memory - Method and apparatus for ensuring a most recent version of data is retrieved from a memory, such as a non-volatile flash memory array. In accordance with various embodiments, a controller is adapted to sequentially store different versions of an addressable data block having a selected logical address in different locations within a memory. The controller assigns a revision indication value to each said version, with at least two of said stored versions concurrently sharing the same revision indication value. In some embodiments, the revision indication value constitutes a repeating cyclical sequence count that is appended to each block, or logically combined with a code value and stored with each block. The total number of counts in the sequence is less than the total number of versions resident in the memory.12-08-2011
20120110411Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection - A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.05-03-2012
20090210770METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR END TO END ERROR CHECKING IN ETHERNET - A method for network protocol error correction comprising, generating a data packet including a cycle redundancy check (CRC) field, an end to end error field that remains unchanged as the data packet is sent over a network, for use in performing error detection in one or more field of the data packet, and a flag field associated with the end to end field to indicate that the end to end error field contains error correction data, and sending the data packet over a network via an Ethernet protocol.08-20-2009
20080307287SYSTEMS AND METHODS FOR RECOVERY FROM HARDWARE ACCESS ERRORS - Systems, methods and media for recovering from a data scan error are disclosed. In one embodiment, a service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.12-11-2008
20110289377SYSTEMS AND METHODS FOR SECURE INTERRUPT HANDLING - The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests.11-24-2011
20120017134DTV TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST SIGNAL - A television transmitting system includes an encoder, a data randomizing and expanding unit, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizing and expanding unit randomizes the error-detection-coded data and expands the randomized data. The group formatter forms a group of enhanced data having one or more data regions and inserts the expanded enhanced data into at least one of the regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter generates enhanced data packets.01-19-2012
20090276684MULTI-ANTENNA CONFIGURATION SIGNALING IN WIRELESS COMMUNICATION SYSTEM - A wireless communication infrastructure entity (11-05-2009
20100287442Method for secure data transfer - A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.11-11-2010
20100005365ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS - A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.01-07-2010
20100005367PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.01-07-2010
20090177945POLARIZATION MODE DISPERSION COMPENSATION USING BCJR EQUALIZER AND ITERATIVE LDPC DECODING - A turbo equalizer includes a Bahl-Cocke-Jelinek-Raviv (BCJR) equalizer configured to receive a transmitted signal and partially cancel inter-symbol interference (ISI) due to polarization-mode dispersion (PMD). A low-density parity check (LDPC) decoder is coupled to the BCJR equalizer to receive channel bit reliabilities therefrom. The LDPC decoder iteratively provides extrinsic soft information feedback to the BCJR equalizer to compensate for PMD.07-09-2009
20090044073BROADCAST RECEIVER AND METHOD OF PROCESSING DATA - A broadcast receiver and a method of processing data are disclosed. The broadcast receiver includes a signal receiving unit, a RS frame decoder, a decoding unit, a text-to-speech (TTS) module, a voice output unit, and a control unit. The signal receiving unit receives broadcast signal multiplexed mobile broadcast service data including text information and main broadcast service data. The RS frame decoder performs decoding on the RS frame, thereby correcting errors occurred in the corresponding mobile broadcast service data. The decoding unit decodes the text information included in the error-corrected mobile broadcast service data. The text-to-speech (TTS) module converts the text information to a voice signal. The voice output unit outputs the converted voice signal. The control unit controls the voice output unit.02-12-2009
20100269014SINGLE XOR OPERATION WEAVER RECONSTRUCTION OF A FAILED DRIVE OF A RAID - Several methods and apparatus to single XOR operation weaver reconstruction of a failed drive of a raid are disclosed. A failed drive of the drive group implemented in a WEAVER code with an (n,t,t) layout is determined. A set of scatter/gather lists is produced from a number of the other drives of the drive group. A scatter/gather list is created by modifying a pointer data of the set of scatter/gather lists. An additional scatter/gather list is generated from the set of scatter/gather lists. A single XOR operation is performed on the data segment, the parity segment, the additional data segment and the additional parity segment to form a resulting scatter/gather list including a resulting data segment and a resulting parity segment. The resulting data segment and the resulting parity segment are written as sequenced in the resulting scatter/gather list to a replacement drive.10-21-2010
20090150750METHOD AND APPARATUS FOR HARQ ENCODING WITH LOW MEMORY REQUIREMENT - An apparatus and method for hybrid automatic repeat request (HARQ) encoding comprising re-encoding a subpacket from a plurality of subpackets to obtain a codeword; maintaining a set of state variables for each of the plurality of subpackets; initializing the set of state variables at HARQ transmit start; updating the set of state variables at HARQ transmit end; and using the set of updated state variables to determine a portion of the codeword to be transmitted.06-11-2009
20090150749DIGITAL DATA CODING AND RECORDING APPARATUS, AND METHOD OF USING THE SAME - A method of preparing data for a storage device includes writing unencoded main data to a memory buffer; reading the unencoded main data from the memory buffer; encoding the read main data; scrambling the encoded main data to provide address and parity information; writing the address and parity information, but not the encoded main data, to the memory buffer; reading the address and parity information and the unencoded main data from the memory buffer; and scrambling the unencoded main data.06-11-2009
20090150748Data Storage and Replay Apparatus - A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.06-11-2009
20120110413METHOD FOR CODING AND DECODING DIGITAL DATA, PARTICULARLY DATA PROCESSED IN A MICROPROCESSOR UNIT - The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series.05-03-2012
20120110412DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcasting system and a method for controlling the same are disclosed. A method for controlling a digital broadcast receiving system includes the steps of receiving a broadcast signal having mobile service data and main service data multiplexed therein, extracting transmission parameter channel (TPC) signaling information and fast information channel (FIC) signaling information from a data group within the received mobile service data, by using the extracted fast information channel (FIC) signaling information, acquiring a program table describing virtual channel information and service of an ensemble, the ensemble being a virtual channel group of the received mobile service data, by using the acquired program table, detecting a descriptor defining basic information required for accessing the received service, and, by using the detected descriptor, controlling the receiving system to enable access to the corresponding service.05-03-2012
20110197108MEMORY CARD AND MEMORY CONTROLLER - A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.08-11-2011
20100125773DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcast receiving system and a method for controlling the same are disclosed. The method includes the steps of receiving a broadcast signal having mobile service data and main service data multiplexed therein, extracting transmission parameter channel (TPC) signaling information and fast information channel (FIC) signaling information from a data group within the received mobile service data, wherein the FIC signaling information includes a current/next (C/N) indicator, and wherein the TPC signaling information includes FIC version information, and detecting ensemble configuration information of a current MH frame.05-20-2010
20100125772ERROR CORRECTING CONTROLLER, FLASH MEMORY CHIP SYSTEM, AND ERROR CORRECTING METHOD THEREOF - An error correcting controller for connecting an old host controller having an old error correcting function with a new flash memory which requires a new error correcting function is provided. When the old host controller needs to write data into the new flash memory, the error correcting controller generates a new error correcting code according to the new error correcting function for the data. Then, when the old host controller needs to read the data from the new flash memory, the error correcting controller performs an error correcting procedure according to the new error correcting code and transmits information to the old host controller according to the result of the error correcting procedure and the old error correcting function. Accordingly, it is possible to allow the old host controller to access the new flash memory without changing the architecture of the old host controller.05-20-2010
20100281339FORWARD ERROR CORRECTION MEDIA ACCESS CONTROL SYSTEM - This disclosure relates to method, device and system for compensating for information not received in a communication system. An encoded signal is created from a source signal using a forward error correction technique. A first predetermined part of the encoded signal is transmitted. A second predetermined part of the encoded signal is transmitted. Transmission of the second predetermined part of the encoded signal is terminated after a determination of a successful decoding of the encoded signal is made.11-04-2010
20120036412LOW DELAY AND AREA EFFICIENT SOFT ERROR CORRECTION IN ARBITRATION LOGIC - There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.02-09-2012
20090307562METHOD OF MATCHING CODEWORD SIZE AND TRANSMITTER THEREFOR IN MOBILE COMMUNICATIONS SYSTEM - The present invention relates to a method and a transmitter for matching a size of codeword encoded by low density parity check (LDPC) code to a size of a transmission channel and in a mobile communication system. A method of adjusting a codeword size in a communication system supporting an LDPC coding scheme, comprises steps of encoding source data by using a parity check matrix, and adjusting a size of the encoded codeword to be matched to a size of a transmission channel which is determined in accordance with a capacity of the transmission channel, the size of the encoded codeword being adjusted using information associated with column weights of the parity check matrix.12-10-2009
20110138250TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed06-09-2011
20120240009METHOD AND APPARATUS FOR TRANSMITTING UPLINK DATA IN A WIRELESS ACCESS SYSTEM - A method of transmitting data in a wireless access system includes: calculating a number C of code blocks using a size B of an input bit sequence, a maximum size Z of the code blocks, and a size L of a cyclic redundancy check (CRC) which is to be attached to each of the code blocks; calculating a size B′ of a modified input bit sequence using the number C, the size L, and the size B; obtaining a size K of each of the code blocks using the size B′ and the number C; segmenting the input bit sequence to have the number C of the code blocks and the obtained size K of each of the code blocks; generating the code blocks by attaching the CRC to each of the segmented input bit sequences; and channel-coding the code blocks.09-20-2012
20120240008ENCODER AND STORAGE APPARATUS - According to an embodiment, an encoder has a storage and a generator. The storage stores information indicative of a generator matrix corresponding to a partial parity check matrix in a rank-deficient parity check matrix including a lower triangular matrix and one or more cyclic matrices or zero matrices, the partial parity check matrix including rows different from rows of the lower triangular matrix. The generator carries out semi-systematic coding using the generator matrix to generate a portion of code word. The generator matrix has a cyclic matrix portion with one or more cyclic matrices and a non-cyclic matrix portion with rows number of which is equal to a degree of rank deficiency in the partial parity check matrix.09-20-2012
20120240007LDPC DECODING FOR SOLID STATE STORAGE DEVICES - A solid state storage device includes a flash memory and a controller configured to store data in the flash memory via a plurality of channels. The stored data is encoded using a low-density parity-check code. Hard-decision decoders are configured to decode encoded data received from the flash memory via respective channels of the plurality of channels using the low-density parity-check code and to provide decoded data to the controller in response to one or more read commands from the controller. A soft-decision decoder is configured to decode the encoded data received from the flash memory using the low-density parity-check code and to provide the decoded data to the controller in response to one of the plurality of hard-decision decoders failing to decode the encoded data. The encoded data is obtained by the soft-decision decoder using a plurality of read-retry operations.09-20-2012
20090249164METHOD FOR SERIAL ASYNCHRONOUS TRANSMISSION OF DATA IN AN ARRAGEMENT FOR THE MONITORING, CONTROLLING, AND REGULATING AN OPERATIONAL CONTROL FACILITY OF BUILDING - In a method for the serial, asynchronous and character-by-character data transmission of a data stream having multiple data words Z to Z, an additional parity data word D is generated and transmitted. The parity data word D is generated such that in a data block formed from the data words Z to Z and the additional parity word D a pre-determined parity is produced, wherein for calculating the parity different bit positions, and thus varying priorities are selected each in the data words adjacent to each other in the data stream. Further, the vertical parity is generated and transmitted for the parity data word, and for each data word Z to Z. The method substantially increases the probability that transmission errors of various origins are detected in a receiver.10-01-2009
20110173515DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcasting system and a data processing method are disclosed. A receiver receives a broadcast signal including mobile service data and main service data. A known data detector detects known data from the broadcast signal. An equalizer performs channel equalization on the mobile service data received by means of the detected known data. An RS frame decoder acquires an RS frame from the channel-equalized mobile service data. A management processor extracts a Generic Stream Encapsulation (GSE) packet from a GSE Base Band (BB) constructing one row of the RS frame, and calculates an IP datagram from the extracted GSE packet. A presentation processor displays broadcast data using data contained in the calculated IP datagram.07-14-2011
20120144265APPARATUS AND METHOD FOR INDICATING A PACKET ERROR IN AN AUDIO AND VIDEO COMMUNICATION SYSTEM - An apparatus and method are provided for indicating an error of a transport packet in an audio and video communication system. The method includes receiving a frame including a transport packet, attempting Forward Error Correction (FEC) on the frame, and setting a value of an error indicating field in the transport packet according to a result of the FEC. The error indicating field includes at least one of a first flag indicating a presence or absence of an error in the transport packet, a second flag indicating a success or failure of the FEC, and a third flag indicating detection or non-detection of a Cyclic Redundancy Check (CRC).06-07-2012
20110173513REFERENCE CELLS FOR SPIN TORQUE BASED MEMORY DEVICE - A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.07-14-2011
20120297269OUTER CODING FRAMEWORK - The subject matter disclosed herein provides an outer coding framework for minimizing the error rate of packets. In one aspect, the method may include determining, based on a cyclic redundancy check, a first erasure table including zero or more erasures; determining a second erasure table; using the first erasure table to locate errors in a frame of packets, when the zero or more erasures of the first erasure table do not exceed a threshold of erasures; and using the second erasure table to locate errors in the frame of packets, when the one or more erasures of the first erasure table do exceed the threshold of erasures. The frame may include the one or more rows encoded using the outer code. The block that is read may be provided to enable an inner code to encode the block before transmission. Related systems, apparatus, methods, and/or articles are also described.11-22-2012
20110209029Low complexity error correction using cyclic redundancy check (CRC) - Low complexity error correction using cyclic redundancy check (CRC). Communications between at communication devices, sometimes including at least one redundant transmission from a transmitter to a receiver, undergo low complexity error correction. CRC may be employed in conjunction with using any desired type of ECC or using uncoded modulation. Based on CRC determined bit-errors, as few as a singular syndrome associated with a singular bit-error or a linear combination of syndromes associated with two or more singular bit-errors within two or more received signal sequences are employed to perform error correction of the received signal. Real time combinations of multiple syndromes associated with respective single bit-errors (that may themselves be calculated off-line) are employed in accordance with error correction. In addition to CRC, any ECC may be employed including convolutional code, RS code, turbo code, TCM code, TTCM code, LDPC code, or BCH code.08-25-2011
20110209028CODEWORD REMAPPING SCHEMES FOR NON-VOLATILE MEMORIES - Systems and methods are disclosed for remapping codewords for storage in a non-volatile memory, such as flash memory. In some embodiments, a controller that manages the non-volatile memory may prepare codeword using a suitable error correcting code. The controller can store a first portion of the codeword in a lower page of the non-volatile memory may store a second portion of the codeword in an upper page of the non-volatile memory. Because upper and lower pages may have different resiliencies to error-causing phenomena, remapping codewords in this manner may even out the bit error rates of the codewords (which would otherwise have a more bimodal distribution).08-25-2011
20100287444DIGITAL BROADCASTING SYSTEM AND DATA PROCESSING METHOD - A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.11-11-2010
20100293434NON-VOLATILE MEMORY WITH BI-DIRECTIONAL ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some embodiments, multiple multi-level parity cells are used to represent parity values stored in codewords of an NVM device. Other embodiments may be described and claimed.11-18-2010
20080244360Non-Volatile Memory with Soft Bit Data Transmission for Error Correction Control - Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.10-02-2008
20080250297METHOD AND SYSTEM FOR CALCULATING CRC - The invention relates to a method and system for calculating CRC. Firstly, a Partial CRC is calculated directly according to a segment of a message. Then, a First Code comprising the Partial CRC appended with a plurality of zero-bytes is generated. Finally, the Adjusted CRC is calculated according to the First Code. Therefore, the method and system of the invention can derive an Adjusted CRC directly from each segment of a message. After all segments of a message are received, all the derived Adjusted CRCs are merged to obtain a Final CRC of the message. The method and system of the invention can be quickly prototyped and implemented to various systems due to its simplicity.10-09-2008
20080276151METHOD AND APPARATUS FOR DECODING A LDPC CODE - In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved.11-06-2008
20080235559Strengthening parity check bit protection for array-like LDPC codes - An LDPC parity check matrix originated using an array code provides more protection against errors for parity bits 1 through 1-p, which can, during decoding, allow faster convergence to a higher LLR value for those bits as well as higher overall reliability of other parity check bits. The present parity check matrix provides an upper triangular sub-matrix (H09-25-2008
20080282131ERROR DETECTION CODE GENERATING METHOD AND ERROR DETECTION CODE GENERATOR - In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver.11-13-2008
20080288848Latency by offsetting cyclic redundancy code lanes from data lanes - Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving latency by offsetting cyclic redundancy check lanes from data. In some embodiments, a memory device includes a memory array to provide read data bits and a cyclic redundancy code (CRC) generator to generate CRC bits corresponding to the read data bits. In addition, the memory device may include a transmit framing unit to transmit the read data bits and the CRC bits to a host, wherein the transmit framing unit includes logic to offset the transmission of the CRC bits from the transmission of the read data bits based, at least in part, on an offset value. Other embodiments are described and claimed.11-20-2008
20080307288Data coding apparatus and methods - Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.12-11-2008
20100005366CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY - A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.01-07-2010
20080313525Error detection for multi-bit memory - Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.12-18-2008
20090031189METHOD AND SYSTEM FOR FORMING A FORMATTED CONTENT STREAM AND USING A CYCLIC REDUNDANCY CHECK - A communication system 01-29-2009
20110209030SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME - A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.08-25-2011
20090164867High Speed Memory Error Detection and Correction Using Interleaved (8,4) LBCs - Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.06-25-2009
20130191698HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.07-25-2013
20110219283SIGNAL QUALITY MEASUREMENT SYSTEM - This disclosure relates to method, device and system for measuring signal quality in a communication system. An access point receives an uplink signal from a transmitter. The uplink signal contains a data portion and a result of a hash function. The uplink signal is received at a time based on a slot start time and a random timing offset and is received while a portion of a second signal is received from a second transmitter. The access point measures a noncoherent energy metric for the uplink signal. The access point computes a local result of the hash function using the data portion. The uplink signal is then discarded if the result of the hash function matches the local result of the hash function but the noncoherent energy metric is below a threshold value.09-08-2011
20090183051Memory System with Cyclic Redundancy Check - A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum.07-16-2009
20090164868Method and apparatus for buffering an encoded signal for a turbo decoder - A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.06-25-2009
20090055708ROBUST ERROR CORRECTION ENCODING/DECODING APPARATUS AND METHOD OF DIGITAL DUAL-STREAM BROADCAST RECEPTION/TRANSMISSION SYSTEM - An error correction encoding and/or decoding apparatus and method of a digital dual-stream broadcast transmission and/or reception system. An error correction encoding apparatus includes a TRS encoding part to apply the transversal encoding to normal data packets and robust data packets and to append parity packets to the normal data packet and robust data packet, a randomization unit to randomize the data packets and the parity packets according to a predetermined pattern, an RS encoding unit to append parities to the randomized data packets and parity packets, a packet format unit to split the data packets and the parity packets into normal data and robust data and to process the normal and robust data, and a system control unit to control the packet format unit. Accordingly, a robust error correction encoding apparatus can be provided for the digital dual-stream broadcast transmission system to which Transversal Reed-Solomon (TRS) encoding is applied.02-26-2009
20090055707FORWARD ERROR CORRECTION SCHEME FOR HIGH RATE DATA EXCHANGE IN A WIRELESS SYSTEM - A transmitter/receiver system for high data transfer in a wireless communication system includes a physical layer processor that comprises an FEC coder, a demultiplexer and a plurality of modem processors. The FEC coder applies error correction codes to the high data rate signal. Thereafter, the demultiplexer distributes portions of the coded high data rate signal to the modem processors. Each modem processor processes its respective portion of the coded signal for transmission in an independent channel.02-26-2009
20090055710DIGITAL BROADCAST TRANSMITTER/RECEIVER HAVING IMPROVED RECEIVING PERFORMANCE AND SIGNAL PROCESSING METHOD THEREOF - A digital broadcast transmitter/receiver, and a signal processing method thereof, includes a randomizer randomizing a dual transport stream which includes a normal data packet and a robust data packet and into which stuff bytes are inserted, a stuff-byte exchanger replacing the stuff bytes of the randomized data with known data, a first RS encoder performing RS-encoding of data output from the stuff-byte exchanger, a packet formatter performing an interleaving of the robust packet of the data output from the first RS encoder and reformatting the packet, an interleaver interleaving data output from the packet formatter, a trellis encoder performing a trellis encoding of interleaved data, a second RS encoder changing a parity by performing an RS encoding of the robust data of the trellis-encoded data, and a modulator modulating data output from the trellis encoder and RF up-converting the modulated data.02-26-2009
20090259915Structured low-density parity-check (ldpc) code - The invention introduces an apparatus, method and system that allow coding matrices to be expanded to accommodate various information packet sizes and support for various code rates; additionally the invention defines a number of coding matrices particularly suited to the methodology. The invention enables high throughput implementations, allows achieving low latency, and offers other numerous implementation benefits. At the same time, the new parity part of the matrix preserves the simple (recursive) encoding feature.10-15-2009
20090006923COMBINED GROUP ECC PROTECTION AND SUBGROUP PARITY PROTECTION - A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.01-01-2009
20090024899System and Method for Providing Data Integrity in a Non-Volatile Memory System - An invention is provided for ensuring data integrity in a non-volatile memory system, including boot block data integrity during Power On Reset. The invention includes loading data into a buffer, such as a flash buffer, and generating an error detection code for the data utilizing a check code generator located in the memory controller. The error detection code is compared to a previously stored error detection code associated with the data. Then, when the error detection code is different from the previously stored error detection code, a correction pattern is calculated and applied to the data directly in the buffer for the non-volatile memory.01-22-2009
20090199073ENCODING DEVICE, DECODING DEVICE, ENCODING/DECODING DEVICE, AND RECORDING/REPRODUCING DEVICE - An error correction device error corrects without increasing in circuit scale. An encoder, includes: a first ECC encoder which interleaves a data string into n (n≧2) blocks of data strings at every m (m≧2) bits, and adds the error correction code parity; a parity encoder which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder, which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated.08-06-2009
20090199072METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR TRANSMISSION OF BIT SENSITIVE INFORMATION - A method for communication between a geologic downhole measurement device and a receiver is provided. The method includes: receiving a bit sensitive data stream representing at least one property of at least one of a geologic formation and a borehole; grouping the data stream into at least one data block; and coding the data block with a forward error correction code. A system and computer program product for communication between a geologic downhole measurement device and a receiver are also provided.08-06-2009
20090049363Simplified LDPC Encoding for Digital Communications - Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.02-19-2009
20110145676DATA ERROR CORRECTION DEVICE AND METHODS THEREOF - A method and device for error detection includes performing error detection for each data word received in a burst access to a memory. When no error is detected, the data words are written to a cache and indicated as valid data. In response to detecting an error in a data word, the error is corrected and the corrected data written to the cache without indicating the data as valid. In addition, the location of the detected error, indicating the data symbol associated with the error, is recorded in an error vector. The error vectors associated with each data word in the burst access are compared to determine whether a detected error was properly corrected.06-16-2011
20090063932Information processing device and method - In an information processing device, error detection information is generated from additional information and a header is generated from error detection information. An encoded header is then generated by appending a header-error correction code to the header and encoded additional information is generated by appending an information-error correction code to the additional information. Finally, an information-appended image is generated by integratedly appending the encoded header and the encoded additional information to the target image.03-05-2009
20090055706METHOD AND APPARATUS FOR FLASH MEMORY ERROR CORRECTION - Error correction method and a flash memory device are provided. In the flash memory device, a memory array comprises a main area for data storage, and a spare area for storage of parities associated with the stored data. An erasure table maintains an erasure list indicating addresses of defects in the memory array where data storage is unavailable. A processor performs error correction on the stored data based on the parities and the erasure list to output a corrected output.02-26-2009
20120079346SIMULATED ERROR CAUSING APPARATUS - An information bit and a redundant bit at addresses of memory determined by a random number are both read without receiving error detection or error correction, the bit at a bit position determined by a random number is inverted, and the bit-inverted data is written to the same address of the same memory. The number of bits (one bit, two or more bits, etc.) to be inverted is set appropriately on the basis of what types of errors are to be caused in a simulated manner.03-29-2012
20120079347DATA CODING APPARATUS AND METHODS - Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.03-29-2012
20090070653METHOD OF TRANSMITTING DATA - A method of transmitting data in a wireless access system is disclosed. The method includes various processes of obtaining the number of code blocks in consideration of an error detection code which is to be attached to each code block, calculating the size of the code blocks, segmenting input data, and channel-coding the code blocks, thereby efficiently transmitting data.03-12-2009
20110231730MASS STORAGE DEVICE AND METHOD FOR OFFLINE BACKGROUND SCRUBBING OF SOLID-STATE MEMORY DEVICES - A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device.09-22-2011
20090210768EXCEPTION CONDITION HANDLING AT A CHANNEL SUBSYSTEM IN AN I/O PROCESSING SYSTEM - A computer program product, apparatus, and method for handling exception condition feedback at a channel subsystem of an I/O processing system using data from a control unit are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes sending a command message to the control unit, and receiving a response message in response to the command message. The response message includes exception condition feedback identifying a termination reason code in response to unsuccessful execution of at least one command in the command message. The method also includes interrupting a CPU in the I/O processing system, and reporting status associated with the exception condition feedback to the CPU in an interrupt response block.08-20-2009
20110029838Device and Method for Transmission, Device and Method for Reception, and Program - The present invention relates to a device and a method for transmission, a device and a method for reception, and a program that make it possible to obtain an undetected error probability characteristic close to a limit value in a system using a CRC for a plurality of pieces of data having different code lengths. A generator polynomial for header data which generator polynomial is used when a CRC coding process is performed on header data and a generator polynomial for sub-header data which generator polynomial is used when the CRC coding process is performed on sub-header data are set in a transmitting device 02-03-2011
20120144266DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN THE DIGITAL BROADCASTING SYSTEM - A digital broadcast transmitting and a method of processing broadcast data in a digital broadcast transmitting system are disclosed. The method includes randomizing mobile service data; RS encoding and CRC encoding the randomized mobile service data to build an RS frame; dividing the built RS frame into L (L>1) number of portions and adding K bytes (K≧0) of dummy data to one of the portions; encoding data in the portions at a code rate of 1/H (H>1); first interleaving the encoded data; mapping the first interleaved data into data groups and adding known data sequences and transmission parameters to each of the data groups, deinterleaving data of the data groups; second interleaving the deinterleaved data; and transmitting a transmission frame including the second interleaved data.06-07-2012
20090106627Digital information reproduction method - An optical disc using super-resolution effects that achieves higher-density recording exceeding the optical resolution suffers from the signal-quality degradation caused by the normal resolution component included in the reproduction signal. To address this problem, a data reproduction method is provided. In the method, characteristic error patterns are identified and parity check codes in conformity with run-length limited coding are used to carry out efficient and reliable error correction. Error patterns caused by the normal resolution crosstalk are localized in the leading edges of a mark following a long space and in the trailing edges of a long mark. Whether an error exists in the data is determined by use of the parity check codes. When an error occurs, a pattern in which an error is most likely to occur is selected from the above-mentioned patterns by taking account of the edge shift direction, and then the error therein is corrected.04-23-2009
20090249165Event Cleanup Processing For Improving The Performance Of Sequence-Based Decoders - The invention relates to improving the performance of sequence-based soft-output decoders using event cleanup processing, wherein combinations of potential error events are evaluated using an error detection code (EDC) to select events that produce a modified set of decisions that has no EDC detectable errors. The event cleanup method and associated event cleanup decoder enable to significantly improve the error rate performance of sequence-based decoders and/or significantly improve decoding efficiency compared to other known error cleanup methods.10-01-2009
20090210769MULTIPLE CRC INSERTION IN AN OUTPUT DATA STREAM - A computer program product, apparatus, and method for inserting multiple CRCs in an output data stream from a channel subsystem to a control unit are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a message to transmit from the channel subsystem to the control unit. The method also includes determining a first CRC insertion position, and receiving a first CRC calculated over a first block of data in the message. The method additionally includes inserting the first calculated CRC at the first CRC insertion position, and determining a second CRC insertion position. The method further includes receiving a second CRC calculated over a second block of data in the message, and inserting the second calculated CRC at the second CRC insertion position.08-20-2009
20090222707Semiconductor memory device having capability of stable initial operation - A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.09-03-2009
20090254792HYBRID DECODING USING MULTIPLE TURBO DECODERS IN PARALLEL - A method and receiver for Turbo decoding a received Turbo encoded bitstream with a first channel decoder which uses a first Turbo decoding algorithm to produce a first decoded bitstream and a first error measure, and a second channel decoder which uses a second Turbo decoding algorithm to produce a second decoded bitstream and a second error measure. The decoders are operable in parallel. A selector is arranged to select, for further processing in the receiver, the decoded bitstream and the error measure from the decoder which has the most favorable error measure.10-08-2009
20080320363METHOD AND APPARATUS FOR RATELESS SOURCE CODING WITH/WITHOUT DECODER SIDE INFORMATION - A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence.12-25-2008
20100275099Systems and Methods for Tri-Column Code Based Error Reduction - Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.10-28-2010
20100275096Systems and Methods for Hard Decision Assisted Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge10-28-2010
20100153816Methods and apparatus to identify the accessibility of femto-base stations in communication systems - A system and method for identifying the accessibility of femto base stations in a communication system. The system and method includes a plurality of macro base stations, open-access femto base stations and femto base stations with different subscriber groups. At least one of the base stations includes a transmitter configured to apply a base station identifier, such as a closed subscription group identifier, as a cyclic redundancy check (CRC) mask to XOR (exclusive OR) the CRC of a broadcast channel communication or an input to generate a scrambling sequence to the broadcast channel communication.06-17-2010
20130219242MULTI-PROCESSING ARCHITECTURE FOR AN LTE TURBO DECODER (TD) - An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.08-22-2013
20090259917METHOD OF CORRECTING MESSAGE ERRORS USING CYCLE REDUNDANCY CHECKS - A method of correcting errors in a message transmitted over a digital communication channel, where the message was encoded using a CRC for purposes of error detection. A parity-check matrix representation of the CRC is computed for any fixed-length message, and that parity-check matrix is combined with the parity-check matrix for any error correcting code that used in conjunction with the CRC. The combined parity-check matrix is extended using sparsification algorithms to allow it to work well under a message passing decoder (MPD). Received messages are decoded using the message passing decoder, making it possible to correct more errors than if the CRC were decoded in a conventional manner.10-15-2009
20090259916DATA ACCESSING METHOD, CONTROLLER AND STORAGE SYSTEM USING THE SAME - Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.10-15-2009
20100050049ERROR CORRECTION APPARATUS, METHOD OF CORRECTING AN ERROR AND METHOD OF GENERATING ERROR LOCATION DATA - An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.02-25-2010
20100153817DATA CORRECTION APPARATUS, DATA CORRECTION METHOD AND TANGIBLE MACHINE-READABLE MEDIUM THEREOF - A data correction apparatus, a data correction method and a tangible machine-readable medium thereof are provided. The data correction method comprises the following steps: receiving a plurality of packets; determining that all of the packets are erroneous packets according to cyclic redundancy check (CRC) information thereof; retrieving any number of pairs among the packets to proceed an exclusive-OR (XOR) logical calculation to generate a plurality of error patterns; obtaining an overall error pattern according to an OR logical calculation of the error patterns; and calculating a correct packet according to one or more of the packets and the overall error pattern.06-17-2010
20100162079METHOD AND APPARATUS FOR PROCESSING DATA - A method of processing data, the method including decoding extracted data, correcting errors of the decoded data and generating data bits and data bit flags indicating error-corrected data bits from among the data bits, re-decoding the extracted data according to the data bits and the data bit flags, and correcting errors of the re-decoded data.06-24-2010
20110107178DECODER, PERPENDICULAR MAGNETIC RECORDING AND REPRODUCING DEVICE, RECEIVING DEVICE, AND DECODING METHOD - An objective of the present invention is to provide a decoder, a perpendicular magnetic recording and reproducing device, a receiving device, and a decoding method that are used for performing decoding resistant to burst errors such as a pole-erase phenomenon, where the burst errors do not have amplitude fluctuation, without the addition of a special code (redundant code) for detecting burst errors. The present invention is a decoder, a perpendicular magnetic recording and reproducing device, a receiving device, and a decoding method that perform a decoding process on an encoded data signal, wherein a parity check is performed on the encoded data signal that is encoded with a low density parity check code to output burst information.05-05-2011
20120246541DTV RECEIVING SYSTEM AND METHOD OF PROCESSING DTV SIGNAL - A method of processing broadcast data in a broadcast transmitting system includes randomizing mobile service data bytes; generating a Reed-Solomon (RS) frame; dividing the RS frame into RS frame portions; converting data bytes of the RS frame portions into data bits; encoding each converted data bit and outputting data symbols corresponding to the encoded data bits; interleaving the data symbols; converting the interleaved data symbols into data bytes; forming data groups including mobile service data corresponding to the converted data bytes, each of the data groups including known data sequences, signaling information, non-systematic RS parity data place holders and MPEG header data place holders; removing the non-systematic RS parity data place holders in the data groups and replacing the MPEG header data place holders in the data groups with MPEG header data to output mobile service data packets; and randomizing the MPEG header data in the mobile service data packets.09-27-2012
20120198306METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING IN COMMUNICATION/BROADCASTING SYSTEM - An apparatus and method are provided for transmitting and receiving in a communication/broadcasting system. The method includes generating a codeword including a first parity bit using a first parity-check matrix, generating an additional parity bit based on a second parity-check matrix, the second parity-check matrix being an extension of the first parity-check matrix, and transmitting the codeword and the additional parity bit.08-02-2012
20120198304INFORMATION REPRODUCTION APPARATUS AND INFORMATION REPRODUCTION METHOD - According to one embodiment, an information reproduction apparatus includes a calculator, selector, and decoder. The calculator calculates parity-check passing ratios based on a check matrix of an LDPC code for code word candidates included in a reproduced signal. The selector selects one of the code word candidates based on the parity-check passing ratios calculated by the calculator. The decoder decodes the code word candidate selected by the selector by an iterative decoding process.08-02-2012
20100262887High Integrity Data Network System and Method - A system for transmitting information data packets over a network includes a plurality of parallel transmission channels, each receiving interleaved data words constituting the data packets. Each channel includes a corresponding check sum data generator to compute check sum data for a corresponding sequence of data words. A logic circuit responsive to the interleaved data words from each channel performs an arithmetic operation on the data words from those channels to generate a parity data stream onto a separate channel. A check sum data generator computes checksum data based on the parity data stream. An encoder device downstream from each checksum data generator encodes the data and checksum from each channel for serial transmission over a network.10-14-2010
20100262889RELIABILITY, AVAILABILITY, AND SERVICEABILITY IN A MEMORY DEVICE - Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.10-14-2010
20100262888DECODING APPARATUS AND METHOD BASED ON VARIABLE ERROR CORRECTION VALUE - Provided is a decoding apparatus and method based on a variable error correction value. The decoding method includes setting an initial normalized factor and a normalized factor correction value, initially updating a check node based on the initial normalized factor, and updating the check node based on a variable error correction value acquired by adding the initial normalized factor and the normalized factor correction value.10-14-2010
20090300464RADIO COMMUNICATION SYSTEM - A base station creates a dummy pattern added with an error correction code, during occurring of a control channel not allocated for transmission of control information, transmits the dummy pattern instead of control information at a power level lower than a normal power level. A mobile station decodes control information transmitted through the control channel, examines whether or not a value specified by the decoded control information is within a suitable range, and performs error detection of the decoded control information. The mobile station stops decoding of data transmitted through a data channel, upon judging that the value is not within the suitable range or detecting an error in the error detection.12-03-2009
20120198307METHOD OF COMMUNICATING SIGNAL DATA IN GNSS USING LDPC CONVOLUTION CODES AND A SYSTEM THEREOF - A method and system for communicating signal data in GNSS system using LDPC convolution codes. The method involves, at transmitting end, formatting signal data into a set of subframes. Each subframe of the signal data can be encoded in accordance with a parity check matrix defining Tanner graph representation of LDPC convolution codes. The encoded signal data can be interleaved and added with a Sync word field to transmit an interleaved block of encoded signal data through a communication channel. At receiving end, the interleaved block of encoded signal data can be de-interleaved after it is received from the communication channel. The Tanner Graph shows the connectivity in time invariant parity check matrix. A message passing technique is used to decode the LDPCCC encoded message. The encoded signal data can be decoded through the message passing technique to obtain the signal data primitively transmitted at the transmitting end. Such method and system are capable of achieving error free performance over the GNSS communication channel for effective navigation data communication, and also provide good BER performance over a wide range of Signal-to-Noise ratios.08-02-2012
20100218069DTV RECEIVING SYSTEM AND METHOD OF PROCESSING DTV SIGNAL - A digital television (DTV) receiving system includes a tuner, a demodulator, a known data detector, an equalizer, a transmission detector, and a block decoder. The tuner receives a DTV signal having a data frame in which main and mobile service data are multiplexed. The demodulator demodulates the DTV signal, and the known data detector detects known data included in the mobile service data. The equalizer equalizes the demodulated DTV signal using the detected known data, and the transmission parameter detector detects an error correction mode from the equalized DTV signal. Finally, the block decoder decodes the equalized DTV signal for error correction using the detected error correction mode.08-26-2010
20120036413DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.02-09-2012
20100211850DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcast receiver and a control method thereof are disclosed. The control method of the digital broadcast receiver includes receiving a broadcast signal into which mobile service data and main service data are multiplexed, extracting transmission parameter channel (TPC) signaling information and fast information channel (FIC) signaling information from a data group in the received mobile service data, acquiring a program table describing virtual channel information and a service of an ensemble, which is a virtual channel group of the received mobile service data, using the extracted FIC signaling information, selectively detecting a first message descriptor mapped with time information or a second message descriptor not mapped with time information, using the acquired program table, performing a control operation to display a message defined in the detected message descriptor.08-19-2010
20100241925Forward Error Correction (FEC) scheme for communications - Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing.09-23-2010
20100241924DECODING DEVICE, ENCODING DEVICE, AND CODING SYSTEM - A decoding device is provided, which can minimize the number of coded data addition requests by the decoding device, reduce processing time to prevent delay, and minimize frame rate reduction. The decoding device performs data reproduction by performing error correction of data of a predicted image using coded data which is an error correction code generated based on original data. The decoding device includes a coded bit receiving part, a preset value generating/updating part, a decoding part that performs a decoding process based on a preset value or a predicted value, and coded bits, and a bit addition request determining part that determines whether or not there is a need to request additional coded bits from decoding process results from the decoder. When it is determined to perform a decoding process with additional coded data, the preset value generating/updating part updates the preset value based on previous decoding process results.09-23-2010
20100251069METHOD AND APPARATUS FOR EFFICIENT MEMORY ALLOCATION FOR TURBO DECODER INPUT WITH LONG TURBO CODEWORD - A method and apparatus for memory allocation for turbo decoder input with a long turbo codeword, the method comprising computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR; storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory; and reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.09-30-2010
20100205507DIGITAL BROADCAST SYSTEM FOR TRANSMITTING/RECEIVING DIGITAL BROADCAST DATA, AND DATA PROCESING METHOD FOR USE IN THE SAME - The present invention is directed to a digital broadcast system and a data processing method. A broadcast signal in which mobile service data and main service data are multiplexed is transmitted and received. Then, in a broadcasting receiver, the program table information including information about a service or a program of an ensemble is parsed according to an identifier of the ensemble in which the mobile service data are multiplexed, in the received broadcast signal. And a mobile service is outputted by using the mobile service data and the parsed program table information.08-12-2010
20100199146STORAGE SYSTEM, STORAGE CONTROLLER AND METHOD FOR CONTROLLING STORAGE SYSTEM - In a storage controller provided for a storage system provided with a plurality of disk devices, for controlling to storage data in the plurality of disk devices, an encoding unit encodes data to be stored in the plurality of disk devices by erasure correction coding to obtain encoded data. A storage/reading unit stores the encoded data in the plurality of disk devices and fetches the encoded data from the plurality of disk devices, according to instructions from a personal computer. A transmitting unit transmits the encoded data fetched from the plurality of disk devices by the storage/reading unit to a storage system 08-05-2010
20100088573METHOD AND APPARATUS FOR HIGH SPEED STRUCTURED MULTI RATE LOW DENSITY PARITY CHECK CODES - Certain aspects of the present disclosure relate to a method for designing structured multi-rate low-density parity-check (LDPC) codes. These LDPC codes can be also adapted to support efficient encoding.04-08-2010
20110066920Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.03-17-2011
20110066919MEMORY ERROR DETECTION AND/OR CORRECTION - An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.03-17-2011
20120198303DIGITAL BROADCAST SYSTEM FOR TRANSMITTING/RECEIVING DIGITAL BROADCAST DATA, AND DATA PROCESSING METHOD FOR USE IN THE SAME - A digital broadcast system having storing resistance to errors generated during the transmission of mobile service data, and a data processing method are disclosed. The digital broadcast system additionally encodes mobile service data. As a result, the mobile service data has strong resistance to a channel variation and noise, and at the same time the system can quickly cope with the channel variation.08-02-2012
20090319865CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD - A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.12-24-2009
20100223527DATA PROTECTION CIRCUIT, DATA PROTECTION METHOD, AND DATA PROCESSING APPARATUS - A generation unit in a data protection circuit acquires input data from one position on a path that outputs the input data as output data, and generates a second error detecting code. A check unit acquires the input data from another position on the path that is closer to an output side than the acquiring position in the generation unit, and checks the input data using a first error detecting code. Further, a connection unit connects the acquiring position in the generation unit and the acquiring position in the check unit so that the input data is acquired by the check unit subsequent to acquirement by the generation unit.09-02-2010
20080282129Operational parameter adaptable LDPC (Low Density Parity Check) decoder - Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations.11-13-2008
20100223529COMMUNICATION METHOD AND SYSTEM USING TWO OR MORE CODING SCHEMES - A communication method includes causing a transmitter to apply error correcting or detecting code systems to multiple frames or packets and to transmit the multiple frames or packets in succession, causing a receiver to receive the transmitted frames or packets and to decode each of the frames or packets received, and causing the receiver to send an acknowledgment signal to the transmitter on the basis of the results of decoding of the frames or packets. The transmitter applies two or more error correcting or detecting code systems to the frames or packets.09-02-2010
20120144264Memory Device On the Fly CRC Mode - On the fly enabling and disabling of error detection for memory access transactions on a transaction basis is provided. Dynamic enabling and disabling of error detection for memory access transactions can also be applied for multiple transactions. Control logic associated with the memory device determines whether to apply error detection, and selectively enables error detection in the memory access transaction. The selective enabling of error detection in a memory access transaction can apply to either reads or writes.06-07-2012
20110119560Flash Memory Device Error Correction Code Controllers and Related Methods and Memory Systems - An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.05-19-2011
20110119559ERROR DETECTING/CORRECTING CODE GENERATING CIRCUIT AND METHOD OF CONTROLLING THE SAME - An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log05-19-2011
20110119556METHODS AND SYSTEMS FOR IDENTIFYING AND CONFIGURING NETWORKED DEVICES - Auto-detection and configuring systems and methods for interconnected, position dependent control devices are disclosed. Embedded identification and configuration keys are associated with each of the control devices in a network, such that specific connection nodes for each controller may be determined by electronically reading the identification as the control devices are installed. Hardware and software compatibility issues may be detected and resolved, including self configuring of the control devices with the proper software where possible. Otherwise, error conditions are signaled.05-19-2011
20090106626LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE - An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.04-23-2009
20100306620DATA PROCESSING DEVICE AND A METHOD FOR ERROR DETECTION AND ERROR CORRECTION - A data processing device and a method for error detection and error correction. The data processing device includes an error detection arrangement and an error correction arrangement. The error detection arrangement is able to detect correctable error and uncorrectable error in the data stored in a memory cell of the memory. The error detection arrangement then determines the neighboring memory cells or memory cells that are physically adjacent to the memory cell for which the correctable error was detected and generates a signal indicating a fault depending on the correctable errors detected in the neighboring physically adjacent memory cells. If a signal indicating a fault is not generated, then an error correction arrangement is used to correct the correctable error detected by the error detection arrangement.12-02-2010
20130013976CODE BLOCK REORDERING PRIOR TO FORWARD ERROR CORRECTION DECODING BASED ON PREDICTED CODE BLOCK RELIABILITY - Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.01-10-2013
20090070654Design Structure For A Processor System With Background Error Handling Feature - A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor system that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. The design structure may specify ECC hardware circuitry that provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The design structure for the processor system may permit the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The design structure may provide for local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.03-12-2009
20100306619CONTROLLER AND DATA ACCESS METHOD FOR FLASH MEMORIES - The invention provides a controller. In one embodiment, the controller is coupled to a flash memory and a host, and comprises a selective mapper and an error correction code encoder. The selective mapper receives first source data, processes the first source data according to a plurality of pseudo random sequences to obtain a plurality of first mapped data segments, calculates a plurality of cross correlation values between prior data and the first mapped data segments, selects an optimal mapped data segment from the first mapped data segments according to the cross correlation values, and generates output mapped data according to the optimal mapped data segment. The error correction code encoder encodes a first error correction code to be stored in the flash memory according to the output mapped data.12-02-2010
20100325519CRC For Error Correction - A cyclic redundancy check (CRC) or other function may be used as an error correction mechanism by analyzing CRC results against a table of CRC results for potential flipped bits. From the table, an incorrect bit may be identified and corrected. Two or more bits may be identified and corrected by testing the XOR of the calculated CRC results with two or more results within the table to identify two or more bits that are incorrect. In one embodiment, data stored on a data storage system may be stored with a calculated CRC for each block of data. When the data is read from the storage system, the CRC function may be used to verify data integrity and to identify one or more bits that are incorrect in the retrieved data.12-23-2010
20100325520RADIO COMMUNICATION DEVICE AND REPETITION METHOD - Provided is a radio communication device which can obtain the maximum improvement effect of the error rate characteristic by repletion when an LDPC code is used as an error correction code. In this device, an LDPC encoding unit (12-23-2010
20110010605METHOD FOR TRANSMITTING A BINARY INFORMATION WORD - A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 201-13-2011
20110035643System and Apparatus for Error-Correcting Register Files - A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.02-10-2011
20110035644Data Path Read/Write Sequencing for Reduced Power Consumption - A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.02-10-2011
20110041036SEMICONDUCTOR RECORDING DEVICE - An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 02-17-2011
20110047438COMPUTER AND DATA STORAGE METHOD - A computer and a method for accessing data in the computer are provided. The computer comprises a mainboard chipset, a conventional hard disk, a flash memory and a controller. The controller is connected with the flash memory and selectively stores data to the hard disk or the flash memory according to the command from the mainboard chipset. The mainboard chipset is the south bridge chipset. The controller comprises a data interface unit in communication with the south bridge chipset, a controlling unit configured to receive the command through the data interface unit, and a flash memory accessing unit connected with the flash memory. The controlling unit controls the flash memory accessing unit to exchange the data with the south bridge chipset through the data interface unit according to the received command.02-24-2011
20090089644MULTIPLE CYCLIC REDUNDANCY CHECK (CRC) ENGINES FOR CHECKING/APPENDING CRCs DURING DATA TRANSFERS - Multiple cyclic redundancy check (CRC) engines for checking/appending CRCs during data transfers. Two distinctly implemented CRC engines are employed to enable the processing of different sized byte formats at two ends of a communication channel. These two distinctly implemented CRC engines can be employed to enable the processing of different sized byte formats in a host device at one end and an hard disk drive (HDD) at another end. For example, sometimes the size of blocks, frames, and/or sector sizes that are processed and employed within a first communication device at one end of a communication channel can differ from the size of blocks, frames, and/or sector sizes that are processed and employed within a second communication device at another end of the communication channel. Two distinctly implemented CRC engines allow the appropriate processing and translation of any desired different sized blocks, frames, and/or sector sizes of a communication channel.04-02-2009
20090327835Techniques for Reducing Joint Detection Complexity in a Channel-Coded Multiple-Input Multiple-Output Communication System - A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and a second symbol stream using minimum mean squared error with ordered successive interference cancellation (MMSE-OSIC) based detection. When the decoded signal associated with the first symbol stream fails the cyclic redundancy check, the channel-coded signals in the first and second symbol streams are detected using neighbor search algorithm (NSA) based detection.12-31-2009
20090089645DATA STORAGE SYSTEMS - Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder.04-02-2009
20100241926Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein - Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.09-23-2010
20100223528DTV TRANSMITTING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.09-02-2010
20090313527METHODS AND SYSTEMS FOR CAPTURING ERROR INFORMATION IN A SATA COMMUNICATION SYSTEM - Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.12-17-2009
20090313526Apparatus and method for merging data blocks with error correction code protection - An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.12-17-2009
20100037120 M/H FRAME ENCODING AND DECODING TECHNIQUES FOR 8VSB DTV BROADCASTING SYSTEMS - Modification of the prior-art M/H system to better suit transmission of internet-protocol (IP) transport packets includes a standard codeword length for a plurality of various options for transverse Reed-Solomon coding of M/H data, which options offer different degrees of forward-error-correction capability. A 235-byte standard codeword length for TRS coding of M/H data allows extending the FIC-Chunks in the Fast Information Channel signaling to double length so as to substantially increase the capability of such signaling to convey information concerning M/H services. In some transmitter apparatus constructed in accordance with aspect of the invention the TRS encoder in the M/H Frame encoder is modified for transmitting the parity bytes of TRS codewords before, rather than after, the data bytes of those TRS codewords.02-11-2010
20090327836Decoding method for convolution code and decoding device - A decoding method performs turbo decoding on data that includes a first value before transmission and that includes a second value after received, the second value changed from the first value due to the influence of a transmission path. The decoding method includes performing the turbo decoding on the data to obtain a log-likelihood ratio for the second value, converting the second value to a third value that is obtained by correcting the second value to become closer to the first value when a decoded result from the turbo decoding on the data includes an error and when an absolute value of the log-likelihood ratio is equal to or greater than a predetermined threshold value; and performing the turbo decoding on the data including the third value to obtain a decoded result of the data.12-31-2009
20100070827ERROR CORRECTION CIRCUIT, FLASH MEMORY SYSTEM INCLUDING THE ERROR CORRECTION CIRCUIT, AND OPERATING METHOD OF THE ERROR CORRECTION CIRCUIT - A flash memory system includes a memory unit including a main cell that stores main data and a parity cell that stores parity data, and an ECC receiving a codeword including the stored main data and the stored parity data, performing error correction on the codeword by executing an operation on a finite field with respect to the codeword, and an element of the finite field comprising a codeword corresponding to an erased page of the memory unit.03-18-2010
20100064199Efficient, programmable and scalable low density parity check decoder - In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable. In exemplary embodiments of the present invention, an H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to, for example: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.03-11-2010
20110214034SEMICONDUCTOR RECORDING DEVICE AND SEMICONDUCTOR RECORDING DEVICE CONTROL METHOD - A semiconductor recording device includes: flash memories including a plurality of physical blocks each including a plurality of pages; an external interface unit which receives data to be recorded on the flash memories; a first ECC generation unit which generates a first ECC code by adding parity data to the data; a data writing unit which records the data based on the first ECC code into the pages in the flash memories; and a page shuffling unit which controls assignment of a symbol of the first ECC code to the pages, and the page shuffling unit controls the assignment of the symbol of the first ECC code such that the symbol of the first ECC code is assigned to pages having at least two page numbers in the physical blocks included in a group.09-01-2011
20110252288AUXILIARY PARITY BITS FOR DATA WRITTEN IN MULTI-LEVEL CELLS - Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.10-13-2011
20110252287INFORMATION PROCESSING DEVICE, METHOD AND PROGRAM - An information processing device includes: an obtaining means for obtaining encoded data obtained by encoding image data formed by blocks with predetermined data unit, for each block, and redundant data for the encoded data obtained by encoding the encoded data using a forward error correction method; a decoding means for decoding each block using the encoded data and intermediate data generated during a decoding process if the encoded data is all collected or using dummy data, the encoded data, and intermediate data generated during a decoding process if the encoded data is not all collected; a forward error correction method decoding means for decoding the encoded data and the redundant data and recovers lost encoded data; and a setting means for decoding the encoded data and setting intermediate data obtained during the decoding to be used to decode a subsequent block as intermediate data during a decoding process for a block which has been decoded.10-13-2011
20110083059Information processing device, data transmitting device, and data transfer method of data transmitting device - A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.04-07-2011
20110083058TRAPPING SET BASED LDPC CODE DESIGN AND RELATED CIRCUITS, SYSTEMS, AND METHODS - A method of generating a Tanner graph includes generating a pseudo-random parameter and selecting a subgraph within the Tanner graph to be designed, and assigning new edges to the subgraph as a function of the value of the pseudo-random parameter and as a function of prior edges, if any, that have been assigned to the subgraph. The method detects whether the subgraph contains a common feature indicative of a trapping set or sets to be avoided during generation of the Tanner graph until either the common feature is not detected or all possible combination of edges have been assigned to the subgraph. The subgraph containing no occurrences of the common feature is included as part of the Tanner graph or one of combinations is selected as the subgraph and is included as part of the Tanner graph. These operations are repeated until the entire Tanner graph is generated.04-07-2011
20110154158SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.06-23-2011
20110078536Using Motion Change Detection to Reduce Power Consumption of Display Systems - Image data, such as graphics, text, and video may be conveyed from a host to a remote display. In some cases, an analysis of successive frames may be undertaken to determine whether motion exists between those frames. In one embodiment, this motion detection may involve the use of an error correction code, such as a cyclic recovery check. This may enable a relatively efficient, low cost determination of whether motion is occurring. If motion is not occurring, motion estimation may be simplified in some cases and, in some cases, refreshing of the display may be curtailed, for example, using a local frame buffer associated with the display.03-31-2011
20120304036MANUFACTURING TESTING FOR LDPC CODES - An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.11-29-2012
20110078538MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive effect element including a first magnetic layer invariable in magnetization direction, a second magnetic layer variable in magnetization direction, and an intermediate layer between the first magnetic layer and the second magnetic layer, an error detecting and correcting circuit which detects whether first data in the magnetoresistive effect element includes any error and which outputs error-corrected second data when the first data includes an error, a writing circuit which generates one of the first write current including a first pulse width and the second write current including a second pulse width greater than the first pulse width, and a control circuit which controls the writing circuit to pass the second write current through the magnetoresistive effect element when the second data is written into the magnetoresistive effect element.03-31-2011
20110078537ERROR DETECTION AND CORRECTION FOR EXTERNAL DRAM - One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.03-31-2011
20110072330Modified error distance decoding - Modified error distance decoding. In certain communication systems, multiple signals (e.g., which may be viewed as being codewords, groups/sets of bits or symbols, etc.) can be commonly affected by such deleterious phenomenon as burst noise when traversing a communication channel (e.g., from a transmitter communication device to a receiver communication device). In such instances, a test error pattern may be identified which covers those affected bits (or symbols) among at least two respective signals (e.g., all of the respective signals or any subset thereof). Various respective test error patterns may be employed, each having a different respective weight, to the desired group of signals (e.g., codewords, groups/sets of bits or symbols, etc.). As such, more than one possible estimate of each respective signal may be generated. A variety of selection operations may be employed when more than one possible estimate exists (e.g., random selection, that estimate with minimum distance, etc.).03-24-2011
20110060965SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - A semiconductor memory device is provided. The semiconductor memory device includes an error correction code block and a memory. The error correction code block performs error correction encoding for user data to generate parity data. The memory stores the user data and the parity data. The error correction code block generates parity data, including a number of bits equal to at least 2t, wherein t is a natural number, and the bits of the parity data distinguish free page data from user data that is equal to the free page data.03-10-2011
20130159812MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS - According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.06-20-2013
20100281337ANALOG ITERATIVE DECODER WITH EARLY-TERMINATION - An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.11-04-2010
20090313528Method and System for Cooperative Communications with Minimal Coordination - A method and system are provided in a wireless communications system comprising a plurality of nodes (users) working cooperatively. The system provides cooperative diversity by allowing nodes to actively share their antennas and other resources to obtain spatial diversity. The nodes receive the same message (information data) from a common source. Each node enhances the reliability of the message with a modern forward error correction (FEC) code, converts the FEC encoded message into an ensemble of symbols, divides the ensemble of symbols into packets, modulates, dithers and transmits the packets to a receiving node. The dithering process is performed by varying the signal amplitude, phase, frequency and/or symbol timing of the modulated packets. A unique dither pattern is assigned to each node. The receiving node captures a composite signal comprising the transmitted packets of all or most of the transmitting nodes in the cooperative communications system. Because the transmitted packets are dithered independently in phase and/or amplitude, spatial diversity is transformed into temporal diversity.12-17-2009
20110154159CYCLIC REDUNDANCY CHECK CODE GENERATING CIRCUIT AND CYCLIC REDUNDANCY CHECK CODE GENERATING METHOD - A cyclic redundancy check code generating circuit successively receives one or more parallel data as input, and repetitively performs a prescribed operation for calculating a cyclic redundancy check code for each parallel data, based on the parallel data and on an initial value or an earlier calculated cyclic redundancy check code. The cyclic redundancy check code generating circuit includes: a plurality of sub-operation units which, based on the initial value and the parallel data, perform sub-operations in different pipeline stages, respectively, by dividing the prescribed operation in a bit length direction of the parallel data; and a correction unit which, based on the initial value and the earlier calculated cyclic redundancy check code, corrects the cyclic redundancy check code calculated by the sub-operation units.06-23-2011
20080320365PROVIDING AN INITIAL SYNDROME TO A CRC NEXT-STATE DECODER INDEPENDENTLY OF ITS SYNDROME FEEDBACK LOOP - An initial syndrome for use by a next-state decoder in a cyclic redundancy check apparatus can be inserted independently of the syndrome feedback path and its associated clock. This eliminates a clock cycle penalty that would otherwise be imposed on an incoming data stream each time the initial syndrome value is inserted.12-25-2008
20090138782METHOD AND APPARATUS FOR DATA TRANSFER - A method of transmitting data and a data management layer. The method includes: providing a cyclic redundancy check generator connected to a retry buffer through a multiplexer; providing a sequence number generator connected to the retry buffer through the multiplexer; generating a sequence number; generating a sequence number cyclic redundancy check remainder using preset inputs of a cyclic redundancy check remainder latch of the cyclic redundancy check generator; providing an input data bus connected directly to the cyclic redundancy check generator and connected to the retry buffer through the multiplexer; providing an output data bus directly connected to the retry buffer; receiving a data packet on the input data bus; adding the sequence number and the cyclic redundancy check remainder to the data packet to create a modified data packet; storing the modified data packet in the retry buffer; and transmitting the modified data packet using the output data bus.05-28-2009
20080320364ADDING KNOWN DATA TO CRC PROCESSING WITHOUT INCREASED PROCESSING TIME - Cyclic redundancy check processing can be applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already known before the unknown data portion becomes available. A syndrome contribution that the already-known data portion contributes to a syndrome for the set of input data can be determined before the unknown data portion becomes available. When the unknown data portion becomes available, the syndrome for the set of input data can be determined based on the unknown data portion and the syndrome contribution.12-25-2008
20120204078FLASH-BASED EEPROM EMULATION USING ERROR CORRECTION CONTROL - A circuit for emulating bit-level erasable non-volatile memory includes an emulator that activates a first virtual sector of a bit-level programmable, block-level erasable non-volatile memory. The first virtual sector receives and stores write requests having an address and a record to be written to the received address. A linked list of records is used to store each subsequent record received in subsequent write requests having the received address. A separate thread in the linked list is maintained for each different received address. The last record subsequently received for each of the received addresses is copied to a linked list of a second virtual sector when a first operating parameter has been exceeded. The active virtual sector is deactivated and erased when the last record subsequently received for each of the received addresses in the linked list of the active virtual sector have been copied to the second virtual sector.08-09-2012
20110161779SEMICONDUCTOR RECORDING DEVICE, CONTROL METHOD OF SEMICONDUCTOR RECORDING DEVICE, AND SEMICONDUCTOR RECORDING SYSTEM - Included are a flash memory onto which user data and parity data are recorded, an external interface unit which receives a first write command for instructing recording of the user data onto the flash memory, and a block managing unit which manages management information indicating whether parity data is valid or invalid. When the user data related to the first write command received through the external interface unit is recorded onto the flash memory 18, the block managing unit updates the management information so as to indicate that the parity data corresponding to the user data is invalid.06-30-2011
20110161777Reliable Packet Cut-Through - A cut-through data packet mechanism is described. Forwarding of a cut-through data packet by an intermediary node enables packet transmission of the cut-through data packet to begin prior to performing a frame CRC on the packet. The CRC is instead performed while transmission of the packet is occurring. If one or more errors are found in the cut-through data packet, then a packet trailer indicating such errors is transmitted toward an endpoint node that receives the cut-through packet.06-30-2011
20110161778METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA IN RESOURCE ALLOCATION IN WIRELESS COMMUNICATION SYSTEM - A method and an apparatus for transmitting and receiving data in resource reallocation in a wireless communication system are provided. The method includes transmitting control information for the uplink resource reallocation to a corresponding terminal, according to the uplink resource reallocation, receiving an uplink packet from the corresponding terminal and determining whether the corresponding terminal receives the control information, and when the corresponding terminal does not receive the control information, informing the corresponding terminal of the determination result by transmitting a NULL signal over a feedback channel for previous uplink resource allocation. Thus, the resource utilization of the system can be raised by preventing repeated data retransmission until a next resource reallocation period.06-30-2011
20110047437APPARATUS, SYSTEM, AND METHOD FOR GRACEFUL CACHE DEVICE DEGRADATION - An apparatus, system, and method are disclosed for graceful cache device degradation. The method may include determining the risk of data loss on the cache device, which may increase (as with Flash memory) with use and age. If the risk of data loss on the cache devices exceeds a threshold risk level, a modified cache policy may be implemented for the cache device to reduce the risk of data loss below the threshold level. This process may iterate until the cache device cannot guarantee performance sufficient to merit continued use of the cache device, and the cache device is logically removed from the system. The changes in cache policy and in the risk of data loss may be hidden from clients that make use of the cache device. The cache policies may transition, for example, in the following order: write back; write through; write around; read only; and bypass.02-24-2011
20120311400Single CRC polynomial for both turbo code block CRC and transport block CRC - Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.12-06-2012
20120204079SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.08-09-2012
20080256416Apparatus and method for initializing memory - An apparatus includes a memory including a controller for initializing the memory, the controller storing a first data including a first code for correcting a first error of the first data, to the memory when initializing, and a memory controller controlling a data transmission to the memory, the memory controller being connected to the memory. The memory controller includes a code generation circuit storing a second data including a second code, to the memory after the initializing, the second code including an address parity for detecting an address causing a second error of the second data in said memory.10-16-2008
20080256414SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHOD OUTPUTTING DATA - A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.10-16-2008
20080256413Redundancy in Signal Distribution Trees - A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (10-16-2008
20080244359Techniques For Correcting Errors Using Iterative Decoding - Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.10-02-2008
20080244362BOSE-CHAUDHURI-HOCQUENGHEM ERROR CORRECTION METHOD AND CIRCUIT FOR CHECKING ERROR USING ERROR CORRECTION ENCODER - A Bose-Chaudhuri-Hocquenghem (BCH) error correction circuit and method including storing normal data and first parity data in a memory cell array, the normal data and first parity data forming BCH encoded data; generating second parity data from the stored normal data; comparing the first parity data with the second parity data; and checking for an error in the normal data in response to the comparing.10-02-2008
20080229174ERROR DETECTION IN A COMMUNICATIONS LINK - An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.09-18-2008
20110258512Apparatus, System, and Method for Storing Data on a Solid-State Storage Device - An apparatus, system, and method are disclosed for storing data on a solid-state storage device. A method includes receiving a storage request to store data on the solid-state storage device, representing the data in an object entry in an object index maintained by a solid-state storage device controller, storing the data as one or more object data segments on the solid-state storage device, and referencing in the object entry the one or more object data segments on the solid-state storage device.10-20-2011
20100287443PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS - A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.11-11-2010
20110029837Systems and Methods for Phase Dependent Data Detection in Iterative Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.02-03-2011
20110119558NONVOLATILE MEMORY AND MEMORY SYSTEM - Disclosed herein is a nonvolatile memory, including: a memory area including a data area configured to retain data and an error correction code area configured to retain an error correction code known as ECC; and a control unit configured to control access to the memory area. The control unit includes an error detection and correction function configured to detect an error in the data read from the data area and to correct the detected error, at least one save area configured such that if data at a designated address and ECC corresponding thereto are read from the memory area and if an error is detected, then the save area retaining the address and correct data corresponding thereto, and a validity presentation block configured to indicate whether or not the address and the correct data retained in the save area are valid.05-19-2011
20110119557Data Transmission Methods and Universal Serial Bus Host Controllers Utilizing the Same - A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.05-19-2011
20100185920DIGITAL BROADCAST SYSTEM, AND DATA PROCESSING METHOD - A digital broadcast system having storing resistance to errors generated during the transmission of mobile service data, and a data processing method are disclosed. The digital broadcast system additionally encodes mobile service data. As a result, the mobile service data has strong resistance to a channel variation and noise, and at the same time the system can quickly cope with the channel variation.07-22-2010
20100185919Enhanced Error Detection in Multilink Serdes Channels - A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.07-22-2010
20110087948LOSS CORRECTION ENCODING DEVICE AND LOSS CORRECTION ENCODING METHOD - A loss correction encoding device having an improved capability of loss correction using LDPC-CC is disclosed. In the loss correction encoding device (04-14-2011
20110060964DATA TRANSMISSION METHOD, DATA RECEPTION METHOD, MOBILE TERMINAL AND RADIO COMMUNICATION SYSTEM - A data transmission method according to the present invention includes the steps of: (A) adding a first CRC code to transmission data; (B) dividing the transmission data to which the first CRC code has been added into a plurality of encoded bit sequences; (C) adding a second CRC code to at least one of the divided encoded bit sequences; (D) performing error correction encoding processing on the encoded bit sequences; and (E) transmitting the encoded bit sequences on which the error correction encoding processing has been performed.03-10-2011
20110093763ELECTRICAL CIRCUIT COMPRISING A DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH CONCURRENT REFRESH AND READ OR WRITE, AND METHOD TO PERFORM CONCURENT - Electrical circuit comprising: A Dynamic Random Access Memory comprising a plurality of memory cells; An associated device connected to said memory via a data bus; Memory cell refresh means, in which: A refresh access is employed to refresh stored data in a memory cell, with the aid of said refresh means; A data access is employed to exchange data between the associated device and a memory cell via said data bus, said data access comprising a read access or a write access, wherein: The circuit comprises conflict check means that, for a given memory cell, detect and communicate a conflict between a requested access of a first type to said cell, said first type being one of a data access and a refresh access, and an ongoing access of a second type to said cell, said second type being the other of a data access and a refresh access.04-21-2011
20110093762APPARATUS AND METHOD FOR TRANSMITTING DATA USING TURBO CODE - The present invention provides an apparatus for transmitting data using turbo code. The apparatus includes an auxiliary bit adding unit configured to add padding bits to information bits, a convolutional turbo code (CTC) encoder configured to encode the padding bit-added information bits using turbo codes to generate coded data, a padding removing unit configured to remove the padding bits from the coded data, and a transmission processing unit configured to transmit the padding bit-removed coded data. The auxiliary bit adding unit adjusts the length of the padding bits according to a maximum size of an input that can be processed by the CRC encoder, and adds the length-adjusted padding bits to the information bits. Limited radio resources can be effectively used and the efficiency of data transmission can be improved.04-21-2011
20110093761SOLID STATE STORAGE ELEMENT AND METHOD - A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.04-21-2011
20110093760Message-Wise Unequal Error Protection - Message-wise unequal error protection is provided using codeword flipping to separate special and ordinary codewords without discarding any codewords. Special messages are encoded to ensure the codeword weight is less than a certain threshold weight. Ordinary messages are encoded to ensure the codeword weight is greater than the threshold weight. The bits of the codeword are flipped to enforce the weight criterion. Ordinary and special messages are encoded using different encodings to provide different levels of error protection. Upon receipt, codewords are separated into special and ordinary codewords for appropriate decoding. If a codeword is of indeterminate type, it is iteratively processed as both a special codeword and an ordinary codeword. The decoding result of each process is periodically checked to determine which decoding result satisfies decoding criteria.04-21-2011
20100115375Header encoding/decoding - In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data.05-06-2010
20110154157Hybrid Error Correction Code (ECC) For A Processor - In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.06-23-2011
20110197107NON-VOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address.08-11-2011
20100031119Permuted accelerated LDPC (Low Density Parity Check) decoder - Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (λ) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(γ)) values and check edge message/intrinsic information (λ) values for their respective updating in successive decoding iterations.02-04-2010
20100023838Quasi-cyclic LDPC (Low Density Parity Check) code construction - Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix.01-28-2010
20100017681METHOD AND APPARATUS FOR ENHANCED HASHING - A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions.01-21-2010
20100017680TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST SIGNAL IN TRANSMITTING/RECEIVING SYSTEM - A receiving system and a method of processing data are disclosed herein. The receiving system includes a receiving unit, an equalizer, a block decoder, and an RS frame decoder. The receiving unit receives and demodulates a broadcast signal. Herein, the broadcast signal includes at least a mobile service data and a data group including a plurality of known data sequences. The equalizer channel-equalizes the data group included in the demodulated broadcast signal by using the plurality of the known data sequences. The block decoder performs turbo-decoding in block units on data of portion allocated to the channel equalized data group. And, the RS frame decoder configures an RS frame by gathering data of the turbo decoded M number of portions, wherein M is an integer greater than 1 (M>1). And, when a number of contiguous CRC errors is equal to (a maximum number of errors that can be corrected by RS erasure decoding)+1, wherein the number of contiguous CRC errors is determined by performing CRC decoding on each row of the RS frame, the RS frame decoder sets up erasure points in all data of the rows including the CRC errors, so as to perform RS erasure decoding on all columns of the RS frame in the column direction.01-21-2010
20110307758APPARATUS, SYSTEM, AND METHOD FOR PROVIDING ERROR CORRECTION - An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines a set of error-correcting code (“ECC”) characteristics for a data storage device. The set of ECC characteristics includes at least one attribute selected from a plurality of supported attributes. A decoder configuration module configures an ECC decoder to operate in compliance with the set of ECC characteristics. An ECC module validates requested data read from the data storage device using the ECC decoder.12-15-2011
20110307757SYSTEMS AND METHODS FOR ERROR CORRECTION - Systems, methods, and an article of manufacture for decoding a broadcast signal are shown and described. In particular, aspects of the Reed-Solomon decoding algorithm are improved to thereby reduce the amount of processing time required to execute the Reed-Solomon decoding.12-15-2011
20110307759Functional DMA - In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.12-15-2011
20120042226ITERATIVE DECODING OF BLOCKS WITH CYCLIC REDUNDANCY CHECKS - The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a predetermined number of consecutive iterations. In another example embodiment, a decoding iteration is performed on a particular sub-block of multiple sub-blocks of a transport block, which includes a single CRC over an entirety of the transport block. The CRC is checked using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from previous decoding iterations on other sub-blocks of the multiple sub-blocks. The decoding iteration is then performed on a different sub-block if the CRC does not check. Also, the decoding iterations for the sub-blocks may be terminated if the CRC checks.02-16-2012
20120005556Organizing And Managing A Memory Blade With Super Pages And Buffers - A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed by a buffer. Additionally, the system and method includes a memory controller to process the memory request to identify the buffer that manages the address location in the memory module. Further, the system and method includes an address mapping module to process the memory request to identify at least one super page associated with the memory module, the at least one super page associated with the address location.01-05-2012
20120005555MEMORY SYSTEM AND COMMAND HANDLING METHOD - A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.01-05-2012
20120047416BROADCASTING RECEIVER AND BROADCAST SIGNAL PROCESSING METHOD - A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.02-23-2012
20120210192HAMMING RADIUS SEPARATED DEDUPLICATION LINKS - A data storage system includes a data storage array configured for de-duplication of duplicate data therein by: identification of a plurality of portions of data; a comparison of each portion of the data to identify duplicate data and identification of a link associated with each duplicate data; a determination of whether a Hamming link-separation-distance of the identified link is greater than twice a Hamming radius of an error correction code in the data storage system; and replacement of the duplicate data with the identified link when it is determined that the Hamming link-separation-distance is greater than twice the Hamming radius.08-16-2012
20110167317APPARATUS FOR ADAPTABLE/VARIABLE TYPE MODULATION AND DEMODULATION IN DIGITAL TX/RX SYSTEM - Disclosed is an adaptable/variable type modulation/demodulation apparatus. A physical layer transmission apparatus for adaptable/variable type modulation, the transmission apparatus including a classification unit to classify a bit stream according to a standard that is determined in advance after receiving the bit stream, an uncoded bit group unit to group the bit stream not to be LDPC-coded by a predetermined number of bits, an LDPC encoder to perform LDPC-coding of the bit stream, a coded bit group unit to group the coded bit stream by the predetermined number of bits, a quadrature amplitude modulation (QAM) unit to select a symbol coset using the coded bit groups; and a convolutional interleaver to perform convolutional interleaving of the symbol.07-07-2011
20110167318READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE AND MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE - A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A07-07-2011
20120017135Combined Single Error Correction/Device Kill Detection Code - In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.01-19-2012
20090055711DIGITAL BROADCASTING TRANSMISSION/RECEPTION SYSTEM UTILIZING MULL PACKET AND TRS CODE TO IMPROVE RECEIVING PERFORMANCE AND SIGNAL PROCESSING METHOD THEREOF - A digital broadcasting transmission and/or reception system having an improved reception performance and a signal-processing method thereof. A digital broadcasting transmitter comprises a TRS encoder for to TRS-encode a MPEG-02-26-2009
20120173953METHOD TO SYNCHRONIZE A REPLACEMENT CONTROLLER'S FIRMWARE VERSION TO THE NATIVE CONFIGURATION DATABASE VERSION ON A SIMPLEX ARRAY - Disclosed are a method and a simplex array controller device that synchronize firmware revisions between an original, native, storage array controller in a single controller storage array system (i.e., a simplex array controller) and a replacement storage array controller that replaces the original, native, storage array controller. An embodiment may create and store an original firmware code image containing a copy of the firmware revision information running on an original simplex array controller along with controller and firmware revision identification off-board of the original array controller on a firmware repository storage device. The firmware repository storage device may be one of the storage devices selected from the array of storage devices controlled by the original array controller. When the original array controller is replaced by the replacement array controller, such as when the original array controller has failed, the replacement array controller may compare the firmware revision information of the firmware currently running on the array controller with the firmware revision information stored in the original firmware code image, and, if the revision information does not match, replace/overwrite the firmware revision on the replacement controller with the firmware revision stored in the firmware code image.07-05-2012
20120060074DECODER BASED DATA RECOVERY - Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.03-08-2012
20120060073MAGNETIC RECORDING APPARATUS - According to one embodiment, there is provided a magnetic recording apparatus configured to record data subjected to error correcting coding according to a shingled recording scheme, the magnetic recording apparatus including a magnetic recording medium in which unit bits of the data subjected to error correcting coding are recorded with phase shifted between adjacent tracks, a read head having a width covering a plurality of tracks and configured to read data from the plurality of tracks, and a recording controller configured to record the data subjected to error correcting coding and a parity for the data in the plurality of tracks covered by the read head, in a divided manner.03-08-2012
20120159282TRANSMITTER, ENCODING APPARATUS, RECEIVER, AND DECODING APPARATUS - An encoding apparatus includes a dividing unit that divides an input signal bit sequence into data blocks and an encoding unit that applies error correction encoding to the data blocks to generate code blocks decodable by repetitive decoding calculations for estimating the reliability of signal bits for a plurality of times and a generation unit that generates redundant bits by performing bit calculations between data blocks of each set combining the divided data blocks; and an output unit that outputs the generated code blocks and redundant bits.06-21-2012
20120072802CHANNEL ESTIMATION IN ADAPTIVE MODULATION SYSTEMS03-22-2012
20110078539DIGITAL TELEVISION TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A digital television (DTV) transmitting system includes a first frame decoder, a second frame decoder, and a frame multiplexer. The first frame decoder forms first enhanced data frames, encodes each data frame for error correction, forms a first super frame by combining the encoded first frames, and interleaves the first super frame. The second frame decoder forms second enhanced data frames, encodes each data frame for error correction, forms a second super frame by combining the encoded second frames, and interleaves the second super frame. The frame multiplexer multiplexes the interleaved first and second enhanced data frames.03-31-2011
20110083057EFUSE DEVICES, CORRECTION METHODS THEREOF, AND METHODS FOR OPERATING EFUSE DEVICES - An efuse device for recording input data according to address data comprises a first check-bit generator, a programming unit, and an efuse array. The first check-bit generator receives the input data and generates first check-bit data according to the input data by a predetermined error correction code. The programming unit generates blowing signals according to the input data and the first check-bit data. The efuse array receives the blowing signals and the address data. The input data and the first check-bit data are recorded in the efuse array according to the blowing signals and the address data.04-07-2011
20100095185TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.04-15-2010
20110099457DTV TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.04-28-2011
20110099456SUPPORTING GLOBAL INPUT/OUTPUT INTERCONNECT FEATURES ON PORTS OF A MIDPOINT DEVICE - In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.04-28-2011
20120233522METHOD FOR HANDLING LARGE OBJECT FILES IN AN OBJECT STORAGE SYSTEM - Several different embodiments of a segmented object storage system are described. The object storage system divides files into a number of object segments, each segment corresponding to a portion of the object, and stores each segment individually in the cloud storage system. The system also generates and stores a manifest file describing the relationship of the various segments to the original data file. Requests to retrieve the segmented file are fulfilled by consulting the manifest file and using the information from the manifest to reconstitute the original data file from the constituent segments. Modifying, appending to, or truncating the object is accomplished by manipulating individual segments and the manifest file. In further embodiments, manipulation of the individual object segments and/or the manifest is used to implement copy-on-write, snapshotting, software transactional memory, and peer-to-peer transmission of the large file.09-13-2012
20120124448MEMORY SUBSYSTEM HAVING A FIRST PORTION TO STORE DATA WITH ERROR CORRECTION CODE INFORMATION AND A SECOND PORTION TO STORE DATA WITHOUT ERROR CORRECTION CODE INFORMATION - A system comprising a memory subsystem having at least one memory device, and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem.05-17-2012
20120124447METHOD AND APPARATUS FOR ERROR MANAGEMENT - To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.05-17-2012
20090132888RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTIONS FOR MEMORY TECHNOLOGY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.05-21-2009
20120221922MEMORY MANAGEMENT SYSTEM AND METHOD - A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.08-30-2012
20120233521APPARATUS, SYSTEM, AND METHOD FOR DECODING LINEAR BLOCK CODES IN A MEMORY CONTROLLER - Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.09-13-2012
20120166909METHOD AND APPARATUS FOR INCREASING DATA RELIABILITY FOR RAID OPERATIONS - A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.06-28-2012
20120131415METHOD OF SETTING NUMBER OF ITERATION COUNTS OF ITERATIVE DECODING, AND APPARATUS AND METHOD OF ITERATIVE DECODING - A method of setting a number of iteration counts of iterative decoding, and an apparatus and method of iterative decoding. The iterative decoder including a signal-to-noise ratio (SNR) estimation unit that estimates an SNR of a received signal, an iterative decoding count setting unit that sets a minimum number of iteration counts for the received signal based on the estimated SNR, and a decoding unit that iteratively decodes the received signal using tentative decoding and error check, and selectively performs the error check based on the minimum number of iteration counts.05-24-2012
20120131413APPARATUS, SYSTEM, AND METHOD TO INCREASE DATA INTEGRITY IN A REDUNDANT STORAGE SYSTEM - An apparatus, system, and method are disclosed to increase data integrity in a redundant storage system. The receive module receives a read request to read data from an ECC chunk spanning N storage elements of an array of N+P storage elements. The N storage elements each store a portion of the ECC chunk and the P storage elements store parity data. The data read module reads data from each of X number of storage elements of the N+P storage elements where (N+P)>X≧N. The ECC correction module corrects the read data of the ECC chunk using Error Correcting Code (“ECC”) in response to the ECC chunk comprising a number of bit errors below a correctable bit error threshold. The substitution module may correct the read data with substitute data from a substitute storage element.05-24-2012
20120131412TRANSMISSION APPARATUS, TRANSMISSION METHOD, RECEPTION APPARATUS, RECEPTION METHOD, PROGRAM AND TRANSMISSION SYSTEM - Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines.05-24-2012
20120216095MEMORY DEVICE AND MEMORY CONTROL UNIT - A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.08-23-2012
20120216094Controller, A Method Of Operating The Controller And A Memory System - The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.08-23-2012
20110185256Adjustment of Write Timing Based on Error Detection Techniques - A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.07-28-2011
20120137192METHOD AND APPARATUS FOR ERROR MANAGEMENT - To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.05-31-2012
20100174967CONTROL APPARATUS AND CONTROL METHOD - A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.07-08-2010
20120173952PARALLEL CRC COMPUTATION WITH DATA ENABLES - Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.07-05-2012
20100050050Coding system, encoding apparatus, and decoding apparatus - An encoding apparatus includes a systematic encoder that generates information bits and parity bits, both of which are transmitted selectively to a decoding apparatus. At certain points, sufficient bit data are transmitted to identify the state of the systematic encoder. The decoding apparatus partitions the received bits at these identifiable points, and processes each partition separately by predicting the information bits, modifying the predicted information bits according to the received information bits, and using the parity bits to correct errors in the resulting information bits. In video coding, this partitioning scheme can deal flexibly with multiple image formats without requiring extra decoding circuitry. With a parallel decoding apparatus, the number of decoding units operating concurrently can be changed flexibly. The error correcting capability of the decoding apparatus is also improved.02-25-2010
20100275097DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcasting system and a method of processing data is disclosed. A receiving system of the digital broadcasting system may include receiving system may include a signal receiving unit, a demodulating unit, a deinterleaver, and a decoder. The signal receiving unit receives a broadcast signal including mobile service data. The mobile service data may construct a code block, the code block including at least one data packet for the mobile service data, an RS parity generated based on the at least one data packet, and a CRC checksum generated based on the at least one data packet and the RS parity. The demodulating unit performs demodulation on the received mobile service data. The deinterleaver deinterleaves the demodulated mobile service data. The decoder corrects error generated from the mobile service data by performing CRC decoding and RS decoding on the code block of the deinterleaved mobile service data.10-28-2010
20100275098BIT ERROR RATE REDUCTION BUFFER, METHOD AND APPARATUS - A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.10-28-2010
20110107177Low Density Parity Check (LDPC) Code - Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown.05-05-2011
20120185750DECODING DEVICE AND DECODING METHOD FOR DECODING DATA ENCODED BY LDPC - A min-sum processing unit executes, on input data, check node processing for each row of a check matrix and variable node processing for each column of the check matrix. When the decoded result involves an error, a detection unit detects a bit of a low degree of reliability from the decoded result. An identifying unit identifies a row and a column of a low degree of reliability in the check matrix on the basis of the bit of the low degree of reliability detected. The min-sum processing unit executes, on the decoded result, check node processing on the row identified as well as variable node processing on the column identified.07-19-2012
20120185749STORAGE APPARATUS AND RESPONSE TIME CONTROL METHOD - A storage apparatus and response time control method capable of preventing response performance deterioration effectively are suggested. Since a response time control unit which delays a response of a corresponding storage device to a command and transfers it to a controller for a storage apparatus is located between the controller and part of or all storage devices in order to equalize response time for the plurality of storage devices to respond to a command issued from the controller, it is possible to equalize the response time of the plurality of storage devices and thereby effectively prevent deterioration of the response performance of the storage apparatus.07-19-2012
20120221921MEMORY DEVICE HAVING MULTIPLE CHANNELS AND METHOD FOR ACCESSING MEMORY IN THE SAME - According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.08-30-2012
20120221920MULTIPLE ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.08-30-2012
20120221919ERROR DETECTION AND CORRECTION CIRCUITRY - Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.08-30-2012
20120084626System and Method for Adding a Storage Device to a Cluster as a Shared Resource - A system and method are described for adding a disk to a cluster as a shared resource. In one embodiment, a request is received to add a disk to a cluster as a shared disk resource. The disk may share a disk identifier with a second disk currently connected to the cluster as a shared resource. A determination is made as to which partition format is used by the disk. A unique disk identifier is retrieved and written to the disk in accordance with the determined partition format. The disk is then connected to the node as a shared disk resource. The disk may be a snapshot, mirror, or backup of the second disk currently connected to the cluster.04-05-2012
20090019338Communications device and wireless communications system - Turbo coding and decoding devices provide interleaving in the error correction coding process, which improves error correction capability. A turbo decoding device for decoding data obtained by performing error detection coding on a plurality of data blocks and further subjecting that data to turbo coding that includes interleaving in the coding process, comprises a rearrangement unit to perform interleaving between a first decoding a second decoding, an error detection unit to perform error detection processing for each block based on data after the first decoding, and an adjustment unit to adjust a likelihood indicated by data obtained after decoding in the first decoder but prior to the interleaving and corresponding to blocks evaluated as having no errors by the error detection unit.01-15-2009
20090019337Methods and apparatus to compute CRC for multiple code blocks - A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.01-15-2009
20110004804Systems and methods for channel coding of wireless communication - Embodiments of an apparatus and method for coding of wireless transmissions channel are generally described herein. Other embodiments may be described and claimed.01-06-2011
20110131468ERROR DETECTION SYSTEM - This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.06-02-2011
20110131467METHOD AND APPARATUS FOR ENCODING LBA INFORMATION INTO THE PARITY OF A LDPC SYSTEM - Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.06-02-2011
20110131466METHOD FOR TRANSMITTING MULTIMEDIA DATA IN AD HOC COMMUNICATION NETWORKS - A method for transmitting multimedia data in an ad hoc network including receiving a packet on a radio interface, and if the node is not its destination, is copied into a local buffer Q while awaiting the verification of the packet, the packet is also uploaded to the top layers for on the one hand verification of its possible corruption and on the other hand optional storage in a local stack P of long duration with additional information about the data fragment. In the case where the transmission on the last hop before the current node has corrupted the packet, it is verified that the headers are intact so as to be able to route the packet appropriately, after having verified whether the stack P is present and whether it contains an intact version of the packet, in which case it is the intact payload which will be substituted for the erroneous payload in the buffer Q. If the stack P is not present or does not contain the packet, then the method will nevertheless propagate the packet when only the payload has been corrupted since a robust multimedia decoder might be able to use this packet correctly.06-02-2011
20120324311APPARATUS, SYSTEM, AND METHOD FOR MANAGING DATA USING A DATA PIPELINE - An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.12-20-2012
20110214033SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other. The identification information associates the second data and the redundant information, and the region specifying information specifies the storage regions in the semiconductor memory chips to which the first data included in the second data and the redundant information are written.09-01-2011
20090106625 Basic Matrix, Coder/Encoder and Generation Method of the Low Density Parity Check Codes - The invention relates to a base matrix, a encoder/decoder of Low Density Parity Check (LDPC) codes and a generation method thereof. The encoder/decoder is determined uniquely by the parity check matrix of the LDPC codes. With different code sizes, said parity check matrix can be obtained by expanding different base matrixes, and also can be obtained by expanding a unique base matrix after correction. Elements of said base matrix must meet an inequation in which the girth value is up to the standard, e.g. when girth ≧6, for any element i, j, k, l in the matrix which forms the short loop having a length of 4 in anticlockwise, there are always mod(i−j+k−l, z) unequal to 0. By this invention, the girth of the constructed base matrix is made as large as possible, the amount of the shortest loops is as few as possible when it is the same girth, thus the curve of bit error ratio (BER) is dropped quickly, the error floor of the LDPC codes is eliminated effectively, and the optimal performance of the LDPC codes is obtained.04-23-2009
20110239087CRC COUNTER NORMALIZATION - The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.09-29-2011
20110239086METHOD AND SYSTEM FOR ROUTING IN LOW DENSITY PARITY CHECK (LDPC) DECODERS - An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.09-29-2011
20110239085ECC WITH OUT OF ORDER COMPLETION - Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.09-29-2011
20110239084CODE-ASSISTED ERROR-DETECTION TECHNIQUE - Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.09-29-2011
20120131414RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTION FOR MEMORY TECHNOLOGY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.05-24-2012
20110264984ENCODING METHOD, ENCODER AND DECODER - Disclosed is an encoding method to change an encoding rate of an erasure correcting code, while decreasing a circuit scale of an encoder and a decoder. 12k bit (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and comprises information and parity, is defined as one cycle. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k−1) X6(i+k−1)+1, X6(i+k−1)+2, X6(i+k−1)+3, X6(i+k−1)+4, and X6(i+k−1)+5. Known information is inserted, in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.10-27-2011
20120096328MULTI-WRITE ENDURANCE AND ERROR CONTROL CODING OF NON-VOLATILE MEMORIES - Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.04-19-2012
20120331369Systems and Methods for Error Correction Using Low Density Parity Check Codes Using Multiple Layer Check Equations - Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.12-27-2012
20110320911Computer System and Method of Protection for the System's Marking Store - A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.12-29-2011
20110320910STORAGE MANAGEMENT METHOD AND STORAGE SYSTEM - A storage system is provided. The storage system comprises a storage media, a storage controller and a host. The storage controller is connected to the storage media. The host is connected to the storage controller, and performs a physical resource management algorithm for managing a physical resource of the storage media, so as to output at least a media operation command to the storage controller. The storage controller performs the media operation command to manage the storage media. A storage management method is also provided.12-29-2011
20110320909MEMORY SYSTEM FOR ERROR CHECKING FETCH AND STORE DATA - A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.12-29-2011
20100199147DEVICE FOR PROCESSING STREAMS AND METHOD THEREOF - A device for processing streams is disclosed. The device includes a stream arranging unit which stacks and rearranges a stream, and a dummy inserting unit which inserts a dummy into the rearranged stream. The device may further include a convolutional interleaver which interleaves the stream with a dummy or an RS encoder and a CRC encoder.08-05-2010
20100199145METHOD AND APPARATUS FOR TURBO ENCODING - An apparatus for encoding an information bit stream using turbo code is provided. The apparatus includes a temporary bit generator for creating a temporary bit stream, an interleaver for independently receiving the information bit stream and the temporary bit stream, a first constituent encoder for independently receiving the information bit stream and the temporary bit stream and generating a first parity bit stream and a second constituent encoder for receiving an output of the interleaver and generating a second parity bit stream. Performance of a turbo code can be enhanced without changing a code rate by making a decoded bit stream longer.08-05-2010
20090006925FEEDBACK SIGNALING ERROR DETECTION AND CHECKING IN MIMO WIRELESS COMMUNICATION SYSTEMS - A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.01-01-2009
20130013975SYSTEM AND DEVICE - According to one embodiment, a system includes a plurality of ring-connected devices. The system includes a first device and a second device. The second device is connected to receive a signal from the first device. When the first device is a data relay station and receives the data containing an error, the first device replaces a part of the data with internally generated data and transmits the resultant data to the second device.01-10-2013
20100131823DIGITAL BROADCAST SYSTEM FOR TRANSMITTING/RECEIVING DIGITAL BROADCAST DATA, AND DATA PROCESSING METHOD FOR USE IN THE SAME - A digital broadcast system having storing resistance to errors generated during the transmission of mobile service data, and a data processing method are disclosed. The digital broadcast system additionally encodes mobile service data. As a result, the mobile service data has strong resistance to a channel variation and noise, and at the same time the system can quickly cope with the channel variation.05-27-2010
20100131822INTEGRATED CIRCUIT COMPRISING ERROR CORRECTION LOGIC, AND A METHOD OF ERROR CORRECTION - An integrated circuit comprises forward error correction (FEC) decoder logic being coupled to memory and arranged to receive data, comprising application data, from a host application process. The FEC decoder logic performs error detection upon the received data. Logic is further arranged to transmit error free application data back to the host application process prior to performing error correction; and store in memory only application data in which errors are detected.05-27-2010
20120151297Enhanced Coherency Tracking with Implementation of Region Victim Hash for Region Coherence Arrays - A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.06-14-2012
20130019140Method of Identifying and Protecting the Integrity of a Set of Source Data - A method of identifying and protecting the integrity of a set of source data which produces and combines an identification signature with a detection and correction remainder and extends the existing capability of some information assurance methods.01-17-2013
20110161780METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE - A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.06-30-2011
20130024742ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.01-24-2013
20130173988Mixed Domain FFT-Based Non-Binary LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.07-04-2013
20080256415Error Detection/Correction Circuit as Well as Corresponding Method - In order to provide an error detection/correction circuit (10-16-2008
20080250296Apparatus, method and system for permanent storage of data - A plurality of first storage elements store data. A plurality of second storage elements store an error correcting code based on a data sub-string of the data. A syndrome is generated based on the first and second storage elements. An erroneously programmed content of the first storage elements is corrected based on the syndrome.10-09-2008
20080244361Pipelined cyclic redundancy check (CRC) - Methods and apparatus to provide a pipelined cyclic redundancy check (CRC) are described. In one embodiment, a plurality of stages determines a plurality of CRC values corresponding to portions of a data packet. The plurality of CRC values may be accumulated to determine a CRC value for the data packet. Other embodiments are also described.10-02-2008
20110246854Secure Communication Using Non-Systematic Error Control Codes - A transmitter device (10-06-2011
20110246853SEMICONDUCTOR DEVICE AND DECODING METHOD THEREOF - An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.10-06-2011
20080222489APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION - A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.09-11-2008
20080222488 METHOD OF COMPUTING PARTIAL CRCS - Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.09-11-2008
20080222487Quantum Key Distribution Mehtod and Communication Apparatus - An error of reception data is corrected using check matrixes for an “Irregular-LDPC code” that are definite and have stable characteristics and a part of shared information is discarded according to error correction information opened to the public. A parity check matrix corresponding to a specific coding rate is extracted from parity check matrix optimized at a coding rate in a desired range while a coding rate is lowered until the error of the reception data is completely corrected, an additional syndrome is generated, and error correction processing is repeatedly executed using the additional syndrome.09-11-2008
20130097470ENCODING APPARATUS AND ENCODING METHOD IN DATA COMMUNICATION SYSTEM - An encoding method and apparatus in a data communication system are provided. The method includes inputting a source block including a plurality of source payloads, converting the source block to an information block including a plurality of information payloads according to an Information Block Generation (IBG) mode selected from a plurality of IBG modes, transmitting a delivery block generated by adding a parity block generated by encoding the information block according to a selected encoding scheme to the source block to a receiver, and transmitting information indicating the selected IBG mode to the receiver.04-18-2013
20130104001STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.04-25-2013
20130124941CYCLIC REDUNDANCY CHECK CODE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AMD METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.05-16-2013
20130132796Accelerated Cyclical Redundancy Check - The disclosure relates generally to the field of communications in transceiver, and more particularly to improved strategies for Cyclical Redundancy Check (CRC). A CRC check of a codeblock may be initiated by a CRC decoder before receiving all of the bits by a corresponding FEC encoder. Furthermore, an incremental CRC check with respect to the data packet without the need for requesting passed through data from higher layers.05-23-2013
20080201625ERROR CORRECTION SYSTEM AND METHOD - A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data.08-21-2008
20100293435Method for increasing efficiency of transferring packet of isochronous transfer type and device thereof - A method for increasing the efficiency of transferring packets of isochronous transfer type in USB 3.0 includes ignoring a packet of isochronous transfer type with an incorrect header. When the receiving end receives a packet of isochronous transfer type with an incorrect header, the receiving end does not send a retry signal to the transmitting end. Therefore, the transmitting end can more quickly transmit the following packets of isochronous transfer type.11-18-2010
20120260145Per-Image Forward Error Correction - Some embodiments provide a method for encoding digital video. The method receives a digital video image. The method encodes the digital video image. The method generates error correction information for the encoded digital video image using only data from the encoded digital video image. The method transmits the generated error correction information with the encoded digital video image. In some embodiments, the method determines a level of error protection for the encoded digital video image based on an image type of the encoded digital video image.10-11-2012
20100318881Flexible Node Identity for Telecom Nodes - Features of a node (12-16-2010
20100318880DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed enhanced data, and a multiplexer multiplexing the enhanced data packets with main data packets. The transmitter further includes an RS encoder RS-coding the multiplexed packets by adding systematic RS parity data to each main data packet and by adding non-systematic RS parity place holders to each enhanced data packet, and a data interleaver interleaving the RS-coded packets. The non-systematic RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet, and a sequence of known data place holders is periodically included in the interleaved enhanced data packets.12-16-2010
20100318879STORAGE DEVICE WITH FLASH MEMORY AND DATA STORAGE METHOD - A method of storing write data in flash memory incorporated in a storage device, the method includes; receiving write data and a logical block address (LBA) for the flash memory, determining whether the LBA exists in the cache memory, if the LBA exists in the cache memory, comparing the write data with cache data stored in the cache memory at a location associated with the LBA, and if the write data and the cache data are the same, terminating operation of the storage device without programming the write data to the flash memory, else updating an error detection information lookup table entry associated with the LBA and programming the write data to the flash memory, and if the LBA does not exist in the cache memory, updating the error detection information lookup table entry associated with the LBA and programming the write data to the flash memory.12-16-2010
20130159810Error Detection And Correction Of A Data Transmission - Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.06-20-2013
20130159811Method of Hybrid Compression Acceleration Utilizing Special and General Purpose Processors - A novel and useful hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.06-20-2013
20090055709GENERATING AND IMPLEMENTING A SIGNAL PROTOCOL AND INTERFACE FOR HIGHER DATA RATES - A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.02-26-2009
20130191699INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS - A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.07-25-2013
20120290895CONTROLLER FOR DETECTING AND CORRECTING AN ERROR WITHOUT A BUFFER, AND METHOD FOR OPERATING SAME - An operational method of a controller for a flash memory may include receiving target data read out from the flash memory, outputting the received target data to a main memory, and generating an error detection syndrome related to the received target data after or simultaneously with completion of the output of the target data.11-15-2012
20120290894MEMORY READ-CHANNEL WITH SIGNAL PROCESSING ON GENERAL PURPOSE PROCESSOR - Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.11-15-2012
20120290893METHOD AND APPARATUS FOR DETECTING A PARITY ERROR IN A SEQUENCE OF DQPSK SYMBOLS OF A DIGITAL TRANSMISSION SYSTEM - The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r11-15-2012
20120290892HIGH THROUGHPUT LDPC DECODER - According to one embodiment, a wireless communications device includes a low-density parity check (LDPC) decoder configured to receive a codeword associated with a parity check H-matrix. The LDPC decoder includes multiple processing elements coupled to a memory for storing the parity check H-matrix comprising R rows and C columns. Each processing element is configured to perform LDPC decoding on different rows of the H-matrix during multiple sub-iterations. A first portion of the processing elements are configured to process certain rows in an upward direction in the H-matrix relative to other rows and a second portion of the processing elements are configured to process other certain rows in a downward direction in the H-matrix relative to the other rows.11-15-2012
20110320912DECODING DEVICE AND DECODING METHOD - A multistage difference cyclic permutation means (12-29-2011
20120005554SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.01-05-2012
20120030541TRANSMISSION DEVICE, RECEPTION DEVICE, TRANSMISSION METHOD, AND RECEPTION METHOD - In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit.02-02-2012
20120030540RAM MEMORY DEVICE SELECTIVELY PROTECTABLE WITH ECC - An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.02-02-2012
20120030539ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION - Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.02-02-2012
20130198584Systems and Methods for Multi-Pass Alternate Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit.08-01-2013
20120297268NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.11-22-2012

Patent applications in class Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)