Class / Patent application number | Description | Number of patent applications / Date published |
714757000 | Parallel generation of check bits | 23 |
20080222486 | METHODS AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK (LDPC) CODES - A novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph are provided. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed to form a loop twice, once using a low degree variable nodes and once using a higher degree variable which is higher than the low degree variable node, where the higher degree variable node comprises a non-loop-closing edge. In one embodiment, the plurality of low degree variable nodes may have the same permutation on each edge. | 09-11-2008 |
20080235558 | Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module - A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs. | 09-25-2008 |
20080250295 | ENCODING METHOD, ENCODING APPARATUS, AND PROGRAM - An encoding method encodes by using a quasi-cyclic code having a code length of n=m n | 10-09-2008 |
20080301521 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 12-04-2008 |
20080301522 | STRUCTURED DE-INTERLEAVING SCHEME FOR PRODUCT CODE DECODERS - A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding. | 12-04-2008 |
20090024898 | CONCURRENT PRODUCTION OF CRC SYNDROMES FOR DIFFERENT DATA BLOCKS IN AN INPUT DATA SEQUENCE - Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks. | 01-22-2009 |
20090077447 | MULTI-LAYER CYCLIC REDUNDANCY CHECK CODE IN WIRELESS COMMUNICATION SYSTEM - A wireless communication device ( | 03-19-2009 |
20090187806 | SYSTEM AND METHOD FOR ERROR DETECTION IN A REDUNDANT MEMORY SYSTEM - A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical mirroring scheme. A cyclic redundancy code is generated on the basis of the data bits and address bits. The generated cyclic redundancy code and a copy of the cyclic redundancy code are saved to the memory channels according to a horizontal mirroring scheme or a vertical mirroring scheme. | 07-23-2009 |
20090199070 | DATA TRANSMISSION SYSTEM AND METHOD OF CORRECTING AN ERROR IN PARALLEL DATA PATHS OF A DATA TRANSMISSION SYSTEM - A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths. | 08-06-2009 |
20090199071 | Systems and Methods for Low Cost LDPC Decoding - Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update. | 08-06-2009 |
20090327834 | DEVICE HAVING TURBO DECODING CAPABILITIES AND A METHOD FOR TURBO DECODING - A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration. | 12-31-2009 |
20110041035 | SEMICONDUCTOR MEMORY APPARATUS AND DATA READ METHOD OF THE SAME - Various embodiments of a semiconductor memory apparatus and a related data read method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a global data bus, an error detection unit, a first data output unit, and a second data output unit. The global data bus transfers first data and second data. The error detection unit performs an error bit detection operation on the first data and the second data and generates a first error detection bit and a second error detection bit. The first data output unit combines the first data and the first error detection bit in series and outputs the combined bits. The second data output unit combines the second data and the second error detection bit in series and outputs the combined bits. | 02-17-2011 |
20110066918 | SOFT ERROR CORRECTION IN A MEMORY ARRAY AND METHOD THEREOF - A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other. | 03-17-2011 |
20110119555 | APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETECTING EMBEDDED INFORMATION - A control unit extracts partial information containing embedded information from a partial area of a content, and controls decoding of the embedded information. A decoding unit performs a decoding process of decoding a plurality of code words contained in the embedded information from the partial information. When the decoding process is successfully performed, the decoding unit notifies the control unit of completion of the decoding process so that each of the control unit and the decoding unit perform a parallel processing in an asynchronous manner. The control unit repeatedly extracts the partial information and sends extracted partial information to the decoding unit until the decoding process is successfully performed. | 05-19-2011 |
20110154156 | METHODS AND APPARATUS FOR EARLY STOP ALGORITHM OF TURBO DECODING - Methods and apparatus for early stop algorithm of turbo decoding are disclosed. An example method comprises of combination of comparing of hard decisions of soft outputs of the current iteration and the previous iteration and comparing the minimum log likelihood results against a threshold. The decoding iteration is stopped once the hard decisions are matched and the minimum soft decoding result exceeds a threshold. | 06-23-2011 |
20120079345 | SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER UNITS IN A TURBO DECODING SYSTEM HAVING PARALLEL DECODING UNITS - A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping. | 03-29-2012 |
20120084625 | APPARATUS AND METHOD FOR DECODING LDPC CODES IN A COMMUNICATIONS SYSTEM - An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword. | 04-05-2012 |
20130117625 | SYSTEM AND METHOD FOR REDUCING MEMORY IN A MULTI-CHANNEL PARALLEL ENCODER SYSTEM - A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit determines, for the plurality of encoders, respective times for the encoders to receive a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders according to the determined times for use in respective encoding operations. | 05-09-2013 |
20150318057 | VARIABLE READ DELAY SYSTEM - A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay. | 11-05-2015 |
20150363263 | ECC Encoder Using Partial-Parity Feedback - ECC Encoders that process packets of p bits (with p>1) in a data block in parallel and generate a set of N parity/check bits that are stored along with the original data in the memory block. Encoders according to the invention can be used to create a nonvolatile NAND Flash memory write cache with BCH-ECC for use in a disk drive that can speed up the response time for some write operations. Encoder embodiments of the invention use Partial-Parity Feedback along with a XOR-Matrix Logic Module, which calculates N output bits from p input bits, and a Shift Register Module that accumulates N check bits. The XOR-Matrix Logic Module is designed using a precalculated Matrix of p×N bits, which is translated into VHDL design language to generate the hardware gates. High-Order p-bit Partial-Parity Feedback improves over LFSR designs and achieves Minimal Critical Path Length:=p. | 12-17-2015 |
20150381207 | PARALLEL BIT INTERLEAVER - A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. | 12-31-2015 |
20160134305 | NON-CONCATENATED FEC CODES FOR ULTRA-HIGH SPEED OPTICAL TRANSPORT NETWORKS - A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture. | 05-12-2016 |
20160164539 | DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE - An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality. | 06-09-2016 |