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Double encoding codes (e.g., product, concatenated)

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714746000 - Digital data error correction

714752000 - Forward correction by block code

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714756000 Cross-interleave Reed-Solomon code (CIRC) 21
Entries
DocumentTitleDate
20080282128Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance - An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash.11-13-2008
20120173951ERROR CORRECTION CODE BLOCK HAVING DUAL-SYNDROME GENERATOR, METHOD THEREOF, AND SYSTEM HAVING SAME - An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.07-05-2012
20100088572PROCESSOR AND ERROR CORRECTING METHOD - A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register.04-08-2010
20110191651TWO-PLANE ERROR CORRECTION METHOD FOR A MEMORY DEVICE AND THE MEMORY DEVICE THEREOF - In order to correct errors of a first page on one plane in a two-plane NAND flash memory, use data of a second page on another plane to mix the encoding and leverage the error correction code of the first page. Each of the error correction codes of the first page and the second page is divided into an inner correction code and a cross correction code. The inner correction codes are used to correct errors of their own pages and the cross correction codes are used to correct errors of two distinct groups, grouped from the even and odd bytes of the two pages respectively. The second page, with fewer errors, is therefore used to enhance the correcting ability of the first page, without lengthening the error correction code of the first page.08-04-2011
20090193313Method and apparatus for decoding concatenated code - Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders.07-30-2009
20120246539WIRELESS SYSTEM WITH DIVERSITY PROCESSING - A wireless system with Diversity processing is provided having Turbo Codes Decoders for computing orthogonal multipath signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the Wireless system to deliver data rates from up to 600 Mbit/s. Several pipelined decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for the pipeline operations.09-27-2012
20100077279Non-Volatile Memory Devices, Systems, and Data Processing Methods Thereof - Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.03-25-2010
20130086445Quasi-Cyclic Low-Density Parity-Check Codes - A system and a method for determining a quasi-cyclic (QC) low-density parity-check (LDPC) code, such that the QC LDPC code has no trapping sets are disclosed. A set of matrices representing a family of QC LDPC codes are acquired, wherein each QC LDPC code is a tail-biting spatially-coupled code of girth not less than eight, and wherein each column of each matrix in the set has a weight not less than four. Based on a trapping set pattern, a matrix from the set of matrices is selected such that the matrix represents the QC LDPC code with no trapping sets. The matrix can be stored into a memory.04-04-2013
20130086446SOVA SHARING DURING LDPC GLOBAL ITERATION - Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.04-04-2013
20130080853SYSTEM AND METHOD OF DATA ENCODING - A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.03-28-2013
20130042162CHAINED CHECKSUM ERROR CORRECTION MECHANISM TO IMPROVE TCP PERFORMANCE OVER NETWORK WITH WIRELESS LINKS - Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first CSUM; error checking the received data block in a second sequence using a second polynomial, using the first CSUM as a second predetermined initial error checking state, producing a second CSUM; comparing the second CSUM to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.02-14-2013
20100042898RECONFIGURABLE MINIMUM OPERATOR - In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first non-reconfigurable minimum operator determines whether a first half of a first ten-bit message is less than a first half of a second ten-bit message, and the second non-reconfigurable minimum operator determines whether a second half of the first ten-bit message is less than a second half of the second ten-bit message. The reconfigurable minimum operator determines whether the first ten-bit message is less than the second ten-bit message based on the comparisons of the first and second non-reconfigurable minimum operators.02-18-2010
20090158118CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES - A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.06-18-2009
20120166908SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, AND ERROR CORRECTION SYSTEM - A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).06-28-2012
20120166907OBFUSCATING DATA STORED IN A DISPERSED STORAGE NETWORK - A method begins by a processing module dispersed storage error encoding secret data in accordance with first dispersed storage error encoding parameters to produce at least one set of encoded secret slices and dispersed storage error encoding data in accordance with second dispersed storage error encoding parameters to produce a plurality of sets of encoded data slices. The method continues with the processing module determining an inter-dispersing function for outputting the sets of encoded secret slices and the plurality of sets of encoded data slices, and for a set of the plurality of encoded data slices: identifying at least one encoded data slice of the set of encoded data slices based on the inter-dispersing function, replacing the at least one encoded data slice with at least one encoded secret slice to produce a mixed set of encoded slices, and outputting the mixed set of encoded slices.06-28-2012
20130047052HIGH SPEED HARD LDPC DECODER - The subject disclosure describes a method for performing error code correction, the method comprising, loading a code word comprising a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits comprises soft information. In certain aspects, the method further comprises decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided.02-21-2013
20090319863ERROR-CORRECTING SYSTEM OF SEMICONDUCTOR MEMORY, ERROR-CORRECTING METHOD, AND MEMORY SYSTEM WITH ERROR-CORRECTING SYSTEM - An error-correcting system includes a data buffer, a generating unit, a syndrome holding unit, a parity holding unit, and a decoding unit. The data buffer is capable of holding N bits of data. The generating unit generates a syndrome and parity on the basis of the data output from the data buffer. The data buffer outputs n bits in the N bits to a generating unit, while shifting the data bit by bit at intervals of k cycles of a clock. The n bits in the N bits are combination of bits based on a determinant complying with the hamming code. The decoding unit identifies a bit position of an error in the data held in the data buffer using the syndrome held in the syndrome holding unit and causes the data buffer to correct the error.12-24-2009
20130061109TURBO CODE INTERLEAVER WITH NEAR OPTIMAL PERFORMANCE - A method of interleaving blocks of indexed data of varying lengths is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.03-07-2013
20120117442System and method for handling forward error correction code blocks in a receiver - A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.05-10-2012
20090019335AUXILIARY PATH ITERATIVE DECODING - A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.01-15-2009
20090013236Method And Apparatus For Cascade Encoding - A cascade encoding method and apparatus are applied to a handheld television system or other fields. The method includes the following: A. Reed-Solomon (RS) encoding is performed on inputted Medium Access Control (MAC) packets, and coded MAC packets are outputted; and B. Low density parity check code (LDPC) encoding is performed on the coded MAC packets, and LDPC encoding blocks are outputted. The apparatus includes an RS coder and an LDPC coder. The RS encoding and LDPC encoding are cascaded to encode an inputted code flow, so as to reduce an error rate. Meanwhile, bytes in one RS encoding data block are dispersed into different LDPC blocks to be encoded through byte interleaving, thereby sufficiently utilizing error code characteristics of the RS encoding and the LDPC encoding for decoding, and improving error correction capability of a system.01-08-2009
20130166986USING ECC ENCODING TO VERIFY AN ECC DECODE OPERATION - A method includes initiating a decoding operation of a first portion of a codeword to generate a set of data bits. The first portion includes first parity bits and is associated with a first error correcting code. The method includes initiating an encoding operation of the set of data bits according to a second error correcting code to generate computed parity bits. The method includes comparing the computed parity bits to a second portion of the codeword to determine a number of bits that differ between the computed parity bits and the second portion of the codeword. The method also includes generating an indication of successful decoding in response to the number of bits that differ being less than a threshold value.06-27-2013
20130166987LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).06-27-2013
20080301520Method and apparatus for recording information on recording medium - A fixed-length block is repetitively generated. The fixed-length block includes a sync information piece, “n-m” information pieces following the sync information piece, an ID information piece following the “n-m” information pieces, and “m” information pieces following the ID information piece, where “n” denotes a natural number equal to or greater than 2, and “m” denotes a natural number smaller than “n” and equal to or greater than 1. The generated fixed-length block is recorded on a recording medium. The ID information piece is placed in an intermediate portion of the fixed-length block.12-04-2008
20080294964SERIAL CONCATENATION OF INTERLEAVED CONVOLUTIONAL CODES FORMING TURBO-LIKE CODES - A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.11-27-2008
20080294963METHOD AND APPARATUS FOR DESIGNING LOW DENSITY PARITY CHECK CODE WITH MULTIPLE CODE RATES, AND INFORMATION STORAGE MEDIUM THEREOF - A method and apparatus for generating a low density parity check (LDPC) code having a variable code rate, the method of generating the LDPC code having a variable code rate including: generating a first parity check matrix by combining a parity matrix or a parity check matrix and a first information word matrix; and generating a second parity check matrix by combining the first parity check matrix and a second information word matrix. According to the method and apparatus, error correction performance is enhanced.11-27-2008
20080294962Efficient Encoding/Decoding of a Sequence of Data Frames - Encoding data by first performing a transformation of predicted data and input data, and then performing a subtraction of the resulting outputs. In an embodiment, the prediction approach is chosen such that fewer elements of different values (compared to a number of elements in the input data) are generated, and the different values are generated in a predictable position. The transformation approach is chosen such that the output expressly represents variations in the input data as well as satisfies a distributive property. The decoding may be performed based on the same concepts. As a result, the data can be encoded and/or decoded efficiently.11-27-2008
20090177943ERROR CORRECTION CODING USING SOFT INFORMATION AND INTERLEAVING - Error correction coding using soft information and interleaving. A symbol interleaved ECC signal (which can be a symbol interleaved multi-level ECC signal) initially undergoes detection (e.g., such as using SOVA detection) to generate soft information. A decoder uses the soft information to generate estimates of at least one symbol (or at least one bit) of the symbol interleaved multi-level ECC signal. Initially, each of the interleaves of the symbol interleaved multi-level ECC signal undergo decoding to determine whether or not any of the interleaves has correctable errors. If not, then a receiving device can request re-transmission of the symbol interleaved multi-level ECC signal from a transmitting device (or a re-read from media of a hard disk drive (HDD)). Interleaves having uncorrectable errors are associated with interleaves having correctable errors. Uncorrectable errors can be corrected via the use of erasure pointers or bit-flipping, among other means.07-09-2009
20120166906MEMORY SYSTEM AND CONTROL METHOD THEREOF - The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.06-28-2012
20100281335Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.11-04-2010
20110302473ERROR CORRECTION CODING - Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may take, as inputs, data packets of a current FEC group and also an untransmitted FEC packet of a preceding FEC group. Due to relationships among the FEC packets, when transmission errors arise and data packets are lost, there remain opportunities for a decoder to recover lost data packets from earlier-received FEC groups when later-received FEC groups are decoded. This opportunity to recover data packets from earlier FEC groups may be useful in video coding and other systems, in which later-received data often cannot be decoded unless earlier-received data is decoded properly.12-08-2011
20120110409ERROR-CORRECTING ENCODING METHOD WITH TOTAL PARITY BITS, AND METHOD FOR DETECTING MULTIPLE ERRORS - An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.05-03-2012
20110296275WIRELESS TRANSMISSION APPARATUS, WIRELESS RECEPTION APPARATUS, TRANSMISSION DATA FORMATION METHOD, AND DATA RECEPTION METHOD - A wireless reception apparatus (12-01-2011
20110296274DATA ENCODING IN SOLID-STATE STORAGE DEVICES - Methods and apparatus are provided for recording input data in q-level cells of solid-state memory (2), where q>2. Input data words are encoded as respective codewords, each having a plurality of symbols. The coding scheme is such that each symbol can take one of q values corresponding to respective predetermined levels of the q-level cells, and each of the possible input data words is encoded as a codeword with a unique sequence of relative symbol values. The symbols of each codeword are then recorded in respective cells of the solid-state memory by setting each cell to the level corresponding to the recorded symbol value. Input data is thus effectively encoded in the relative positions of cell levels, providing resistance to certain effects of drift noise.12-01-2011
20110296273METHODS AND DEVICES TO REDUCE OUTER CODE FAILURE RATE VARIABILITY - The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.12-01-2011
20110296272OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES - Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.12-01-2011
20090300462Coding Apparatus, Coding Method and Coding Program - Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0≦i12-03-2009
20080244354Apparatus and method for redundant multi-threading with recovery - A method and apparatus for reducing the effect of soft errors in a computer system is provided. Soft errors are detected by combining software redundant threading and instruction duplication. Upon detection of a soft error, errors are recovered through the use of software check pointing/rollback technology. Reliable regions are identified by vulnerability profiling and redundant multi-threading is applied to the identified reliable regions.10-02-2008
20130219241METHOD FOR STOPPING ITERATION IN AN ITERATIVE TURBO DECODER AND AN ITERATIVE TURBO DECODER - The present document discloses a method for stopping iteration in an iterative Turbo decoder and an iterative Turbo decoder. Hard decisions from the two convolutional decoders of the iterative Turbo decoder are used simultaneously to determining when to stop the iteration in the iterative Turbo decoder.08-22-2013
20090282314MULTIDIMENSIONAL TURBO PRODUCT CODES AND GENERALIZED LOW-DENSITY PARITY-CHECK CODES WITH COMPONENT REED-SOLOMON CODES FOR OPTICAL TRANSMISSION - A transmitter, a receiver, and corresponding methods are provided. The transmitter includes encoders configured to encode source bit streams from L information sources into bytes of codewords. Each encoder includes different (n, k) multidimensional turbo-product codes of code rate R=k/n, where k is a number of information bytes, and n is code word length. The encoders operate in at least two phases. A first phase involves operating k11-12-2009
20100269013DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.10-21-2010
20090150747CORRECTION OF ERRORS IN A MEMORY ARRAY - A computer system for correction of errors in a memory array includes an error correction algorithm and a memory. The error correction algorithm is capable of correcting errors up to a first bit error rate in a correctable group of memory cells having a standard size. The memory is operative to store a first set of ECC bits having information corresponding to a first group of memory cells having a first size larger than the standard size, and to store a second set of ECC bits having information corresponding to a second group of memory cells having a second size smaller than said first size and being a portion of said first group. The error correction algorithm is operative to correct errors in the second group based on the second set of ECC bits if a failure occurs in correction of the first group based on the first set of ECC bits.06-11-2009
20100122144TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST SIGNAL IN TRANSMITTING/RECEIVING SYSTEM - A receiving system and a method of processing broadcast signal are disclosed herein. The receiving system includes a signal receiving unit, a signaling decoder, a block decoder, and an RS frame decoder. When a parade change command ordering parade change from a first parade to a second parade is generated, the signal receiving unit receives a broadcast signal including data groups of the second parade starting from a generation point of the parade change command. The signaling decoder decodes signaling information included in the data groups and outputting RS frame-related information. The block decoder performs turbo-decoding in block units on data of a portion included in the data groups. And the RS frame decoder inserts null data in data positions of a portion included in non-received data group within an RS frame of the second parade, while configuring the RS frame of the second parade by collecting data of the turbo-decoded portions based upon the RS frame-related information. The RS frame decoder also performs CRC-decoding by indicating the existence of errors on CRC error flags of each row including the null data within the RS frame, and performs RS-decoding on the CRC-decoded RS frame.05-13-2010
20100064198STORED DATA PROCESSING APPARATUS, STORAGE APPARATUS, MEDIUM STORING STORED DATA PROCESSING PROGRAM, AND STORED DATA PROCESSING METHOD - A stored data processing apparatus includes: a format controller that adds an error correction code to data written onto a disk medium for each first block; a redundant data generation section that performs calculation for each bit position using data of all the first blocks in a second block and outputs a result of the calculation as calculation data, the second block being constituted by a plurality of the first blocks each including the error correction code added by the format controller and specified as an update target; and an MPU that writes the calculation data output from the redundant data generation section in a third block associated with the second block as the update target.03-11-2010
20100281336METHOD AND ENTITY FOR PROBABILISTIC SYMMETRICAL ENCRYPTION - The invention relates to a method of probabilistic symmetric encryption of a plaintext message element with the aid of a secret key that can be represented in the form of a matrix. It comprises an operation of encrypting the plaintext message element, with the aid of the matrix parametrized by a random vector, so as to obtain an encrypted message element coupled to the random vector. Furthermore, there is envisaged a step of encoding the plaintext message element as a code word with the aid of an error correcting code having a given correction capacity and a step of adding a noise vector. The error correcting code and the noise vector are adapted so that the Hamming weight of the noise vector is less than or equal to the correction capacity of the correcting code.11-04-2010
20100125771ERROR JUDGING CIRCUIT AND SHARED MEMORY SYSTEM - An error judging circuit includes a first EOR circuit tree that generates a check bit of a correction code by polynomial remainder calculation with respect to a polynomial expression of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (205-20-2010
20100083071LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing - LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.04-01-2010
20090164865APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIPLE INTERMEDIATE OUTPUTS - A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.06-25-2009
20090049362Method and system for decoding a data burst in a communication system - The present invention provides methods and systems for decoding a data burst in a communication system. A data burst, including a plurality of forward error correction (FEC) blocks, is received. At least one FEC block of the data burst is decoded. Thereafter, it is detected if one or more errors are present in the at least one FEC block of the data burst. Upon detecting one or more errors in the at least one FEC block, the method halts the decoding of the data burst. In response to detecting the one or more errors, a retransmitted data burst corresponding to the data burst is received. One or more FEC blocks of the data burst may be combined with corresponding one or more FEC blocks of the retransmitted data burst. The one or more FEC blocks of the data burst includes the at least one FEC block that had the one or more errors detected as present. Thereafter, the decoding of the retransmitted data burst is commenced starting from the at least one FEC block that had the one or more errors detected as present in the previous transmission.02-19-2009
20090049361Protected communication link with improved protection indication - A method for communication includes receiving first and second data frames over first and second communication links, respectively, the first and second data frames containing respective first and second replicas of data, which has been encoded with a Forward Error Correction (FEC) code. The FEC code in the received first and second data frames is decoded, and respective first and second soft quality ranks of the first and second data frames are computed based on the decoded FEC code. One of the first and second replicas of the data are selected based on the first and second soft quality ranks. The selected one of the first and second replicas of the data is provided as output.02-19-2009
20110173511METHOD AND DEVICE FOR ENCODING OF ERROR CORRECTING CODES, AND METHOD AND DEVICE FOR DECODING OF ERROR CORRECTING CODES - Provided is an error correction encoding device including: an outer encoding circuit (07-14-2011
20110173512MEMORY AND METHOD FOR CHECKING READING ERRORS THEREOF - A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.07-14-2011
20090292968Hard Component Failure Detection and Correction - In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check/correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check/correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits. A presence of more than one binary one in the first syndrome indicates a multi-bit error. Responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.11-26-2009
20100287441SIGNAL SEGMENTATION METHOD AND CRC ATTACHMENT METHOD FOR REDUCING UNDETECTED ERROR - The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.11-11-2010
20120297267ERROR FLOOR REDUCTION IN ITERATIVELY DECODED FEC CODES - A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.11-22-2012
20100005364ENCODING METHOD, ENCODING APPARATUS, DECODING METHOD, AND DECODING APPARATUS USING BLOCK CODE - An input unit receives an information sequence. A first encoding unit performs at least a portion of a block encoding process on the information sequence to generate a first code sequence. A second encoding unit performs the block encoding process on a first check symbol sequence in the generated first code sequence to generate a second code sequence. A generating unit combines a second check symbol sequence in the generated second code sequence with the input information sequence to generate a third code sequence.01-07-2010
20100005363CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR WIRELESS ROUTERS USING 802.11N PROTOCOL - Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM symbol, transmitting the base LDPC code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, and transmitting the base LDPC code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers.01-07-2010
20080244358Circuits and Methods for Error Coding Data Blocks - A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.10-02-2008
20080244355COMPARING DATA SETS THROUGH IDENTIFICATION OF MATCHING BLOCKS - A computer-implemented method includes receiving a source data set and a target data set. Differences between the target data set and the source data set are identified by dividing the target data set into a set of target data blocks. At least one duplicate block that is identical to a first portion of the source data set is identified among the target data blocks. At least one modified block for which contents of the modified block are not duplicated within the source data set is identified among the target data blocks. Different portions and identical portions between the modified block and the source data set are also identified.10-02-2008
20080276150ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME - An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.11-06-2008
20080244357PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.10-02-2008
20080235556REVERSE CONCATENATION FOR PRODUCT CODES - A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.09-25-2008
20080235557Semiconductor memory device - A semiconductor memory device includes: a plurality of error correction code (ECC) groups, each ECC group including plural data configured to be read from and written to the semiconductor memory device and plural parity data configured to correct an error of the plural data, wherein at least one of the ECC groups includes the plural data allocated in dispersed memory cells, not adjacent.09-25-2008
20080215950LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing - LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.09-04-2008
20080215951Communication system - At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into, low and high, frequency band components which are designated as a first and a second data stream respectively. Upon receiving the TV signal, a receiver can reproduce only the low frequency band component or both the low and high frequency band components, depending on its capability.09-04-2008
20080209302SYSTEM AND METHOD FOR F-SCCH AND R-ODCCH PERFORMANCE IMPROVEMENT - A control channel encoder, e.g., in a UMB system, uses a channel structure that can efficiently transmit more information bits, yet achieve sufficient detection and false alarm performance. A control channel encoder can use a fixed encoder packet size, tail-biting convolutional coding, and Cyclical Redundancy Check (CRC). A control channel decoder can use a circular Viterbi decoding algorithm and a circular trellis check.08-28-2008
20110126078DECODER AND DECODING METHOD FOR LOW-DENSITY PARITY CHECK CODES CONSTRUCTED BASED ON REED-SOLOMON CODES - Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. To overcome the difficulty in efficient implementation of a high-throughput decoder, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency. In addition, shuffled message-passing decoding can be adopted in decoders according to the invention to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance.05-26-2011
20090031188ERROR CORRECTING CODE GENERATION METHOD AND MEMORY CONTROL APPARATUS - An objective of the present invention is to make it possible to appropriately correct an error of data in a cache memory. A store processing unit generates an nt-ECC on the basis of data stored in a non-target area that was read out from a cache memory with a search of the cache memory, and generates t-ECC on the basis of the data to be stored in the buffer.01-29-2009
20090183050FORWARD ERROR CORRECTION SCHEME FOR DATA CHANNELS USING UNIVERSAL TURBO CODES - A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.07-16-2009
20090282315LDPC coding systems for 60 GHz millimeter wave based physical layer extension - LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).11-12-2009
20090006922ERROR CORRECTING APPARATUS AND ERROR CORRECTING METHOD - According to one embodiment, an error correction parity bit sequence is generated for a data sequence obtained by adding a dummy symbol of a specific pattern to a digital information sequence modulated to convert into a form satisfying the request of a reproducing system. If the parity bit sequence meets the request of the reproducing system, the modulated digital information sequence excluding the dummy symbol and the parity bit sequence are output in such a manner that the information sequence and parity bit sequence correspond to each other. If the parity bit sequence does not meet the request of the reproducing system, a dummy symbol of another pattern is added to the modulated digital information sequence, thereby generating an error correction parity bit sequence.01-01-2009
20080320362Multilevel Low Density Parity-Check Coded Modulation - A method and apparatus are provided for encoding and decoding a communication signal. Processes for encoding and decoding the communication signal use a first low density parity-check code (LDPC) construction and a second low density parity-check code construction that differs from the first low density parity-check code construction. Multilevel coding (MLC) is applied to protect each address bit of a signal point by an individual LDPC code. In one embodiment, the first level is coded with a progressive edge-growth LDPC code, the second level is coded with a Reed-Solomon LDPC code and the third level is left uncoded.12-25-2008
20090249162ERROR CORRECTION SYSTEM USING THE DISCRETEFOURIER TRANSFORM - A system of determining unknown symbols of an error correcting code using the Discrete Fourier Transform (DFT) with arithmetic corresponding to the number field of the error correcting code, including complex numbers. Encoder and decoder configurations are described. Parallel generation of independent parity check equations, simultaneous solution of unknown symbols generating, or regenerating a codeword of the error correcting code.10-01-2009
20090199069METHOD AND APPARATUS FOR FACILITATING CONCATENATED CODES FOR BEACON CHANNELS - Methods, apparatuses, and computer program products are disclosed for encoding/decoding a wireless control signal. For encoding, control bits are received and encoded with a first error control code so as to create a first set of encoded bits. The encoded bits are then encoded with a second error control code so as to create a second set of encoded bits, which are modulated as beacon tones and subsequently transmitted. For decoding, beacon tones corresponding to a set of control bits are received and subsequently demodulated so as to ascertain a set of demodulated bits. The demodulated bits are then decoded with a decoder so as to ascertain a set of decoded bits. The decoded bits are then decoded with a second decoder so as to ascertain a second set of decoded bits, which includes the set of control bits.08-06-2009
20120144263METHODS OF DATA HANDLING - Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.06-07-2012
20090241008Memory devices and encoding and/or decoding methods - Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.09-24-2009
20120079343APPARATUS AND METHOD FOR DETERMINATION OF A POSITION OF A 1 BIT ERROR IN A CODED BIT SEQUENCE, APPARATUS AND METHOD FOR CORRECTION OF A 1-BIT ERROR IN A CODED BIT SEQUENCE AND DECODER AND METHOD FOR DECODING AN INCORRECT, CODED BIT SEQUENCE - An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence.03-29-2012
20120079342Error Correcting Code Logic for Processor Caches That Uses a Common Set of Check Bits - A processor or other apparatus of an aspect may include a first cache, a first error correction code (ECC) logic for the first cache, a second cache, and a second ECC logic for the second cache. The apparatus may also include an interconnect coupled with or between the first cache and the second cache. The interconnect is operable to transmit data and also check bits corresponding to the data between the first cache and the second cache. A method of an aspect may include accessing data, and check bits corresponding to the data, from a first cache. The data and the check bits may be transmitted over an interconnect from the first cache to a second cache. The data and the check bits may be stored in the second cache. Other methods, apparatus, and systems are also disclosed.03-29-2012
20090055705Decoding of Raptor Codes - There are provided a method and apparatus for decoding Raptor code. The apparatus includes a decoder for decoding a sequence of packets representative of a sequence of encoding symbols. The decoder at least partially recovers at least some lost or corrupted packets of the sequence using Raptor code.02-26-2009
20090100314MODIFICATION OF ERROR STATISTICS BEHIND EQUALIZER TO IMPROVE INTER-WORKING WITH DIFFERENT FEC CODES - This invention relates to a receiver circuit which comprises an equalizer (04-16-2009
20090204870METHOD AND DEVICE FOR SECURING THE MEMORY OF A COMPUTER AGAINST ERRORS DUE TO RADIATION - The method is for hardening a computer based on off-the-shelf components so that it resists bombardment by particles of cosmic origin encountered at high altitude and near the poles. It relates more particularly to a computer comprising a processor/bridge pair, the bridge ensuring auxiliary functions for controlling the data exchanges between the processor and a random-access memory incorporating a Hamming-type error corrector code into the information exchanged and consists in inserting between the processor/bridge pair and the random-access memory an interface device carrying out a two-way transcoding between the Hamming-type error correction code incorporated into the information exchanged by the auxiliary functions for controlling the data exchanges of the processor/bridge pair and a Reed-Solomon-type error correction code adapted to the architecture of the random-access memory.08-13-2009
20090249163ITERATIVE DECODING OF CONCATENATED LOW-DENSITY PARITY-CHECK CODES - Techniques to perform iterative decoding of concatenated low-density parity-check codes (LDPC) are described. Iterative decoding of the concatenated code is achieved by performing T common iterations, wherein a common iteration comprises t10-01-2009
20120144261ERROR CHECKING AND CORRECTING CIRCUIT, MEMORY SYSTEM COMPISING ERROR CHECKING AND CORRECTING CIRCUIT, AND RELATED METHODS OF OPERATION - An error checking and correcting (ECC) circuit is connected with nonvolatile memories via a plurality of channels. The ECC circuit calculates a first syndrome according to first read data and stores the first syndrome in a first syndrome register block, and calculates a second syndrome according to second read data and stores the second syndrome in a second syndrome register block.06-07-2012
20080313524RECORDING FORMAT FOR INFORMATION DATE, INFORMATION RECORDING/REPRODUCING CORDING CIRCUIT - The object of the invention is to provide an efficient encoding method for error correction coding for recording/reproducing information in high-density magnetic recording/reproduction apparatus. Based upon the principle of Turbo coding for powerful random error correction, this invention provides a practical encoding method for preventing the propagation of code errors from being caused by the failure of the error correction due to burst signal errors existing on actual reproduced signal and recovering reliable code data from this. In addition, the object is to reduce decoding time delay (latency) in iterative decoding for the error-correction and realize high-speed operation for error correction. To achieve the objects, an information code sequence is divided in units of code block and the random error-correction coding is applied to an individual code block. Concatenated coding with hard-decision error-correction code for compensating a burst error is applied.12-18-2008
20080307286Combined Single Error Correction/Device Kill Detection Code - In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.12-11-2008
20100162078TELECOMMUNICATION SYSTEM AND RELATED METHODS - A telecommunication system and related methods. Implementations may include implementations of a method of encoding data for transmission, including forming a frame by encoding a message block using a short-block low density parity check (LDPC) code and an encoder to form a short encoded block, modulating the short encoded block using a modulation format and a modulator to form a modulated short encoded block, including the modulated short encoded block in a data payload of the frame, and transmitting the frame into a telecommunication channel with a transmitter. The frame may be one of a plurality of frames and each modulated short encoded block in each of the plurality of frames may have a constant number of symbols. The frame may include a modulation/code pair (ModCod) including information relating to the modulation format and the short-block LDPC code used for encoding and modulation.06-24-2010
20090300463SYSTEM AND METHOD FOR DETERMINING PARITY BIT SOFT INFORMATION AT A TURBO DECODER OUTPUT - A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.12-03-2009
20100192040Multi-Stage Decoder for Error-Correcting Codes - A multi-stage decoder decodes a block of symbols, received via a noisy channel, to a codeword. The decoder includes multiple sub-decoders connected sequentially, and wherein a next sub-decoder has a slower processing time and better word error rate than a previous sub-decoder, and wherein the next sub-decoder is only executed if the previous decoder fails to decode the block sequence of symbols, and a last sub-decoder is executed until a termination condition is reached.07-29-2010
20100192039MEMORY DEVICE AND OPERATION METHOD THEREOF - A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.07-29-2010
20100218068MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM - Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.08-26-2010
20100251068STORAGE CONTROLLER WITH ENCODING/DECODING CIRCUIT PROGRAMMABLE TO SUPPORT DIFFERENT ECC REQUIREMENTS AND RELATED METHOD THEREOF - One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.09-30-2010
20100162077METHOD AND APPARATUS FOR MAP DECODING AND TURBO DECODER USING THE SAME - A Maximum A Posteriori (MAP) decoder and a MAP decoding method are provided. The MAP decoder includes a first metric operation unit, a first bit-width control unit, a second metric operation unit, a Log Likelihood Ratio (LLR) operation unit, and a second bit-width control unit. The first metric operation unit outputs a first metric data using an input data. The first bit-width control unit controls a bit-width of the first metric data according to a modulation scheme of the input data. The second metric operation unit outputs a second metric data using the first metric data having the controlled bit-width. The LLR operation unit outputs LLR data using the second metric data. The second bit-width control unit outputs decoding data by re-controlling the bit-width of the LLR data.06-24-2010
20100241923Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding - Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding. An LDPC code is concatenated with a RS code or a binary product code (e.g., using row and column encoding of matrix formatted bits) thereby generating coded bits for use in generating a signal that is suitable to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. and various implementations of cyclic redundancy check (CRC) may accompany the product coding and/or additional ECC/FEC employed. The redundancy of such coded signals as generated using the principles herein are in the range of approximately 20% thereby providing a significant amount of redundancy and a high coding gain. Soft decision decoding may be performed on such coded signal generated herein.09-23-2010
20100211849MULTI-DIMENSIONAL LDPC CODED MODULATION FOR HIGH-SPEED OPTICAL TRANSMISSION SYSTEMS - Arbitrarily high data transmission rates may be achieved by the use of N-dimensional, LDPC-coded modulation. N orthonormal basis functions are employed using coherent reception, resulting in a proportional increase in transmission rate with only a modest increase in bit-error ratio.08-19-2010
20100235711Data Processing System with Concatenated Encoding and Decoding Structure - A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword.09-16-2010
20100235712APPARATUS AND METHOD FOR CHANNEL INTERLEAVING IN COMMUNICATIONS SYSTEM - An apparatus and method for interleaving systematic bits and parity bits to generate an output sequence that can be transmitted in multi-slot packets from a base station to a remote station in a wireless communication system. The apparatus comprises a memory element and a control element coupled to the memory element, wherein the control element is configured to demultiplex the systematic bits and parity bits into sequences, wherein the systematic bits and parity bits are sequentially distributed among the sequences. The control element is further configured to reorder the sequences based on an index set, to group the sequences into segments and to interleave each of the segments forming matrices having elements. The control element is also configured to modulate the elements of the matrices, and to truncate the modulated elements of each matrix, so as to produce the output sequence which comprises truncated modulating elements from each matrix of the matrices.09-16-2010
20100251067SYSTEMS AND METHODS FOR PROTECTING A MULTI-PART BROADCAST CONTROL MESSAGE - A method and/or apparatus are provided for protecting control information during broadcasts in a system where primary and second mobile broadcast control messages (PMBCM and SMBCM) are utilized. In order to protect the SMBCM, a first hash information instance is computed based on hashes for each a plurality of control data blocks for the SMBCM. The first hash information instance is appended to the PMBCM. Error-correcting code words are generated for the plurality of hashes for the plurality of control data blocks for the SMBCM. These error-correcting code words are appended to the control data blocks of the SMBCM. A receiver uses the first hash instance information in the PMBCM to determine if any control data blocks of the SMBCM are corrupt. If so, the error-correcting code words may be used to reconstruct the corrupted hash(es) for the control data block(s) in order to authenticate the remaining control data blocks.09-30-2010
20090037792DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.02-05-2009
20100138721Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder - Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.06-03-2010
20120198302Device and Method for Error Correction and Protection Against Data Corruption - A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cv08-02-2012
20090177944SEMICONDUCTOR MEMORY DEVICE AND ITS CONTROL METHOD - A semiconductor memory device includes a temporary storage circuit configured to receive data items and store the data items in rows and columns, a detecting code generator configured to generate first detecting codes used to detect errors in the data items, respectively, a first correcting code generator configured to generate first correcting codes used to correct errors in first data blocks corresponding to the columns, respectively, each of the first data blocks containing data items that are arranged in a corresponding one of the columns, and a second correcting code generator configured to generate second correcting codes used to correct errors in second data blocks corresponding to the rows, respectively, each of the second data blocks containing data items that are arranged in a corresponding one of the rows.07-09-2009
20100223525ERROR DETECTION DEVICE AND METHODS THEREOF - A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.09-02-2010
20120144262METHOD OF PRODUCING AND DECODING ERROR CORRECTION CODE AND APPARATUS THEREFOR - An apparatus and method for producing error correction code and error correction decoding are provided. The method for producing error correction code includes generating an asymmetric matrix by arranging input data bits in a matrix of a predefined size and adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; primarily encoding the asymmetric matrix by adding one or more parity bits to each row; and secondarily encoding the primarily encoded matrix by adding one or more parity bits to each column of the encoded matrix.06-07-2012
20080244356SUPER BLOCK ERROR CORRECTION CODE (ECC) ADAPTABLE TO COMMUNICATION SYSTEMS INCLUDING HARD DISK DRIVES (HDDs) AND OTHER MEMORY STORAGE DEVICES - Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.10-02-2008
20080229170Parallel arrangement of serial concatenated convolutional code decoders with optimized organization of data for efficient use of memory resources - A decoding system (09-18-2008
20090106624ERROR CORRECTION METHOD - According to an error correction method of the present invention, in the case of decoding a code word (04-23-2009
20100306618TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCASTING SIGNAL IN TRANSMITTING/RECEIVING SYSTEM - A transmitting system, a receiving system, and a method of processing broadcast signals are disclosed. Herein, the transmitting system includes an RS frame encoder, a block processor, a group formatter, and a trellis encoding module. The RS frame encoder performs error correction encoding on an RS frame payload including mobile service data so as to form an RS frame, divides the RS frame into a plurality of portions, and outputs the divided RS frame portions. The block processor performs one of ½-rate encoding and ¼-rate encoding on each bit of the mobile service data included in each portion. The group formatter maps a portion including symbols of the ¼-rate encoded mobile service data and symbols of the ½-rate encoded mobile service data to a corresponding region of a data group. And, the trellis encoding module performs trellis encoding on the symbols of the ¼-rate encoded mobile service data and the symbols of the ½-rate encoded mobile service data of the data group.12-02-2010
20130132792STORAGE DEVICE INCLUDING ERROR CORRECTION FUNCTION AND ERROR CORRECTION METHOD - According to one embodiment, a storage device includes a first encoder, s storage medium, a second encoder, and a wireless communication unit. The first encoder generates a first codeword including a first information part corresponding to at least a part of write data, and a first redundant part used to correct the first information part. The storage medium stores the first codeword. The second encoder generates a second redundant part used to correct a second information part corresponding to the first codeword or the first information part. The wireless communication unit wirelessly transmits the second redundant part to an external storage device.05-23-2013
20130139030STORAGE CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROLLING METHOD - A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.05-30-2013
20100325517APPARATUS FOR PROCESSING STREAMS AND METHOD THEREOF - An apparatus for processing streams includes a trellis encoding unit which changes a part of streams with parities, an RS re-encoding unit which corrects at least one of parity part and data part of the streams, and generates new codewords to match the changed part of the streams, and a multiplexer which re-constructs the streams with the generated codewords.12-23-2010
20130145229Systems, Methods and Devices for Multi-Tiered Error Correction - An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding.06-06-2013
20130145230SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.06-06-2013
20110010604INFORMATION ENCODING METHOD, INFORMATION DECODING METHOD, RECORDING/REPRODUCING APPARATUS, AND INFORMATION STORAGE MEDIUM - A method of encoding information and a method of decoding information, and an apparatus to perform one or both methods, and an information storage medium on which to store the information, the method of encoding the information including encrypting data between two ECC-encoding operations, and the method of decoding the information including decrypting data between two ECC-decoding operations01-13-2011
20110113301Diversity broadcasting of gray-labeled CCC data using 8-VSB AM - Receivers for diversity reception of data transmitted by concatenated convolutional code (CCC) from at least one 8-VSB transmitter are described. Each receiver includes a first turbo decoder for the CCC as finally transmitted, a second turbo decoder for the CCC as initially transmitted, and an information-exchange unit connected for exchanging decoding information between the turbo decoders, which perform decoding concurrently. The turbo decoders are designed for decoding CCC formed from an outer convolutional code encoding de-interleaved Gray-coded data and a subsequent binary-coded inner convolutional code forming a 12-phase trellis code in accordance with a Gray-labeling procedure, the outer convolutional code encoding being symbol-interleaved before encoding within said inner convolutional code so said inner convolutional code has implied symbol interleaving in which the original order of data bits is preserved.05-12-2011
20090089643TURBO DECODER AND ITERATION STOPPING METHOD THEREOF - A turbo decoder includes first and second interleavers, a de-interleaver, first and second component decoders and a stop judging circuit. The first and second component decoders respectively decode a systematic code and an interleaved systematic code into first and second extrinsic information. The de-interleaver, the first and second data interleavers respectively process the second extrinsic information, the systematic code and the first extrinsic information into a first a-priori information, an interleaved systematic code and the second a-priori information. The stop judging circuit includes a signal selector, a difference detector and a comparator. The signal selector outputs the first extrinsic information and the first a-priori information or the second extrinsic information and the second a-priori information. The difference detector and comparator respectively get a difference between two output data of the signal selector and output a stopping signal to stop the iteration when the difference is smaller than a threshold value.04-02-2009
20100223526METHOD AND APPARATUS FOR CHANNEL CODING AND MODULATION FOR UNEQUAL ERROR PROTECTION IN TRANSMITTING UNCOMPRESSED VIDEO OVER WIDEBAND HIGH FREQUENCY WIRELESS SYSTEM - An Unequal Error Protection (UEP) transmission apparatus comprises a bit separator unit configured to, when video data are received, separate pixels of the video data into Most Significant Bits (MSBs) and Least Significant Bits (LSBs) according to a degree of importance on a pixel-component basis; a header generation unit configured to create an MSB sub-frame and a LSB sub-frame based on the respective MSBs and LSBs and create an MSB Medium Access Control (MAC) sub-frame and a LSB MAC sub-frame to which respective headers are added; and a channel coding unit configured to create a channel-encoded MSB data and a channel-encoded LSB data by performing error correction encodings corresponding to the respective MSB MAC sub-frame and LSB MAC sub-frame and add padding bits, corresponding to the respective channel-encoded MSB data and channel-encoded LSB data, to the channel-encoded MSB data and channel-encoded LSB data.09-02-2010
20100211848CODING OF DATA STREAM - Coding a data stream is provided, wherein the data stream comprises at least one packet having a given packet length and respective partitions of the at least one packet are coded with different error protection rates, the respective lengths of the respective partitions being determined by respective predetermined percentages of the packet length or a fraction of the packet length.08-19-2010
20110126077COOPERATIVE TRANSMISSION METHOD AND COMMUNICATION SYSTEM USING THE SAME - A cooperative transmission method includes: a first operation of coding, by a source node, a message desired to be transmitted according to a first encoding scheme to generate a first codeword and transmitting the first codeword to a relay node and a destination node; a second operation of decoding, by the relay node, the first codeword which has been received from the source node, coding the decoded message according to a second coding scheme to generate a second codeword, coding a part corresponding to parity of the second codeword according to the first coding scheme to generate a third codeword, and transmitting the third codeword to the destination node; and a third operation of decoding, by the destination node, the first codeword which has been received from the source node and the third codeword which has been received from the relay node, combining the message generated by decoding the first codeword and the parity part of the second codeword generated by decoding the third codeword to generate a fourth codeword according to the second coding scheme, and decoding the fourth codeword to estimate the message desired to be transmitted.05-26-2011
20090217133INTER-SEQUENCE PERMUTATION TURBO CODE SYSTEM AND OPERATION METHODS THEREOF - A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce memory usage in both encoder and decoder. The proposed system is compatible with 08-27-2009
20100070826TURBO DECODER WITH EXTRINSIC INFORMATION SCALING MODULES - The invention related to a turbo decoder comprising SISO decoding modules each other interconnected in a feedback control scheme having scaling modules for applying a scaling factor to extrinsic information delivered by said SISO decoding modules. The turbo decoder comprises a selection module for adaptively selecting said scaling factor based on a number of decoding iterations of the turbo decoder.03-18-2010
20100070825Fast Low-Density Parity-Check Code Encoder - Methods, apparatus, and systems are provided to encode a low-density parity-check codeword for transmission in a communications channel. In an embodiment, the encoding may include partially computing parity-check bits in response to receiving a block of message bits before obtaining all the message bits for the low-density parity-check codeword, including updating previously partially computed parity-check bits that depend on the received block.03-18-2010
20100064197RANDOM-ACCESS MULTI-DIRECTIONAL CDMA2000 TURBO CODE INTERLEAVER - An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.03-11-2010
20110252286NON-BINARY LDPC CODE DECODER - The present disclosure relates generally to data decoding, and more particularly to non-binary iterative decoders. Non-binary LDPC codes and LDPC decoders that may be used to decode non-binary LDPC codes are disclosed. Systems and methods are also disclosed that compute messages related to non-binary LDPC codes, in a LLRV form and in a metric vector form and to process these messages in non-binary LDPC decoders. Systems and methods are additionally disclosed that convert messages between the LLRV form and the metric vector form. The implementation and use of non-binary low density parity check code decoders, the computation of messages in the LLRV and metric vector forms, and the use of message conversion systems and methods, according to this disclosure, may provide increased information relating groups of codeword bits, increased computational efficiency, and improved application performance.10-13-2011
20110154154SIGNAL SEGMENTATION METHOD AND CRC ATTACHMENT METHOD FOR REDUCING UNDETECTED ERROR - The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.06-23-2011
20110154153Interleaving Redundancy Apparatus and Method - One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving redundancy encoder is configured to calculate at least one redundancy byte based on a series of spaced, non-consecutive bytes in the initial data stream. Other systems and methods are also disclosed.06-23-2011
20110083055DECODING METHOD FOR RAPTOR CODES USING SYSTEM - The present invention relates to a decoding method for a raptor codes using system, which is capable of improving performance of the system and limiting increase in the amount of computation by grouping variable nodes if raptor codes are unsuccessfully decoded, to thereby increase a conjecture efficiency of variable node values. The decoding method is capable of improving performance of the system by making it possible to achieve performance improvement and additional reduction of the amount of computation even under an application of MP decoding by grouping variable nodes whose values cannot be known when decoded, dividing groups of variable nodes into sub groups, and conjecturing and recovering the variable nodes in a manner to exclude sub groups which do not satisfy check node equation.04-07-2011
20110179335METHOD AND APPARATUS FOR CONFIGURING PROTOCOL HEADER IN WIRELESS COMMUNICATION SYSTEM - Provided are a method of configuring a protocol header in a wireless communication system, and a communication apparatus and method using the protocol header configuration method. The protocol header configuration method may include: configuring a variable length physical layer (PHY) header and a fixed length PHY header; encoding the fixed length PHY header according to a first coding scheme; generating a Header Check Sequence (HCS) to check an error regarding a combination of the fixed length PHY header, the variable length PHY header, and a Media Access Control (MAC) header; scrambling the MAC header and an HCS to generate a scrambled MAC header and HCS; and encoding the variable length PHY header and the scrambled MAC header and HCS according to a second coding scheme.07-21-2011
20110060962Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.03-10-2011
20120278679Iterating Inner and Outer Codes for Data Recovery - A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.11-01-2012
20120151296DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device includes: an error corrector configured to perform demodulation and error correction on a received signal to output error-corrected data, the received signal transmitting packets which include packet identifiers and are encrypted by broadcast encryption; and a transport stream generator configured to generate a transport stream based on the error-corrected data. The error corrector selects the packets including a set packet identifier, and outputs the selected packets as the error-corrected data.06-14-2012
20100100792Single-stage decoder for raptor codes - A system and method for recovering erased symbols in a wireless communication is provided. The system and method includes a receiver configured to receive encoded data transmissions. The receiver includes a single stage decoder configured to perform a decoding operation. The single stage decoder also is configured to determine a symbol erasure rate, the symbol erasure rate defined by a number of erased symbols. The single stage decoder further is configured to generate a recovery matrix based on the symbol erasure rate and invert the recovery matrix. Thereafter, the single stage decoder recovers the erased symbols based on a function of the inverted recovery matrix.04-22-2010
20120204077DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA - A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data.08-09-2012
20110161774SEMICONDUCTOR MEMORY SYSTEM HAVING ECC CIRCUIT AND METHOD OF CONTROLLING THEREOF - A semiconductor storage system includes: a memory region having a plurality of memory cells; and a memory controller having a data control unit. The data control unit includes a write control unit which, during a write operation, performs first error check correction (ECC) encoding on an input data to generate a first encoded input data, compresses the first encoded input data to generate a compressed input data, and performs second ECC encoding on the compressed input data to generate a second encoded input data. The write control unit then writes the second encoded input data into the memory region as a write data.06-30-2011
20080320361Information Recording Device, Data-Flow Controller and Data Flow Controlling Method - A method for transferring corrected data to an external buffer within a tape drive is disclosed. After the receipt of data from a data recording medium, the data are stored in an external buffer. The data are then transferred from the external buffer to an error correction code (ECC) device. Any error in the data within the ECC device are corrected. The corrected data are subsequently divided into multiple sub-units, and a transfer flag is added to each of the sub-units having corrected data. Only the sub-units having corrected data are transferred from the ECC device back to the external buffer.12-25-2008
20110161776COMPRESS-FORWARD CODING WITH N-PSK MODULATION FOR THE HALF-DUPLEX GAUSSIAN RELAY CHANNEL - Systems and methods that implement compress-forward (CF) coding with N-PSK modulation for the relay channel are disclosed, where N is greater than or equal to two. In the CF scheme, Wyner-Ziv coding is applied at the relay to exploit the joint statistics between signals at the relay and the destination. Quantizer design and selection of channel code parameters are discussed. Low-density parity check (LDPC) codes are used for error protection at the source, and nested scalar quantization (NSQ) and irregular repeat accumulate (IRA) codes for Wyner Ziv coding (or more precisely, distributed joint source-channel coding) at the relay. The destination system decodes original message information using (a) a first signal received from the source in a first interval and (b) a second signal that represents a mixture of transmissions from the source and relay in the second interval.06-30-2011
20110161775SYSTEM AND METHOD FOR SETTING A FLASH MEMORY CELL READ THRESHOLD - A system, method and computer readable medium for performing a first read attempt of multiple codeword portions while using a first read threshold candidate to provide multiple first read results, wherein the multiple codeword portions are stored in multiple flash memory cells; calculating a first read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple first read results; performing a second read attempt of the multiple codeword portions while using a second read threshold candidate to provide multiple second read results; calculating a second read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple second read results; and selecting a first read threshold out of the first and second read threshold candidates based on a relationship between the first and second read threshold candidate error correction decoding based scores.06-30-2011
20110161773CORRECTING DOUBLE-BIT BURST ERRORS USING A LOW DENSITY PARITY CHECK TECHNIQUE - Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.06-30-2011
20090094503FAST H-ARQ ACKNOWLEDGEMENT GENERATION METHOD USING A STOPPING RULE FOR TURBO DECODING - A stopping rule for Turbo decoding that is applied for both good and bad code blocks is disclosed. If the iteration either converges or diverges, decoding is terminated. In an alternative embodiment, the result of the stopping rule testing may be used for H-ARQ acknowledgement generation: if the iteration converges, an ACK is generated and if the iteration diverges, a NACK is generated. Optionally, the maximum number of decoding iterations may be dynamically selected based on MCS levels.04-09-2009
20110047435METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES - An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ⅗ utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.02-24-2011
20110047436Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors - Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).02-24-2011
20120311399MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM - Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.12-06-2012
20100325518METHOD OF PROCESSING TRAFFIC INFORMATION AND DIGITAL BROADCAST SYSTEM - A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.12-23-2010
20110264983SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND SIGNAL REPRODUCING APPARATUS - According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.10-27-2011
20110264982Method for transmitting and receiving signalling information - A method for protecting signalling information in a frame to be transmitted to a receiver in a communication system, comprising: encoding frame signalling information of the frame to protect the frame signalling information; and encoding Forward Error Correaction FEC block signalling information of FEC blocks in the frame by using Reed-Muller codes to protect the FEC block signaling information.10-27-2011
20110060963METHOD AND APPARATUS FOR INTERLEAVING A DATA STREAM USING QUADRATURE PERMUTATION POLYNOMIAL FUNCTIONS (QPP) - A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.03-10-2011
20120151294METHOD AND APPARATUS FOR CORRECTING ERRORS IN MEMORY DEVICE - A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.06-14-2012
20100293433Burst-error correction methods and apparatuses for wireless digital communications systems - Frames of data that have transverse Reed-Solomon (TRS) coding and subsequent cyclical-redundancy-check (CRC) coding are subjected to de-interleaving before concatenated convolutional coding (CCC). The de-interleaving is related to the symbol interleaving of the outer convolutional coding prior to the inner convolutional coding so as to result in implied interleaving of data bits in the CCC on which wireless digital transmissions are based. The CCC is turbo decoded in a receiver for the wireless digital transmissions and re-interleaved to reproduce soft data, hard data bits of which data are TRS coded. CRC coding is decoded during the turbo decoding procedures and used to influence the confidence levels of the soft data. The confidence levels of the soft data are used for locating byte errors when the TRS coded hard data bits of the soft data are decoded.11-18-2010
20100293432ERROR-CORRECTION CODING METHOD, ERROR-CORRECTION DECODING METHOD, ERROR-CORRECTION CODING APPARATUS, AND ERROR-CORRECTION DECODING APPARATUS - An error-correction coding method that includes outer coding of performing a coding process for an outer code; and inner coding of performing a coding process for an inner code that has an error correction capability adjusted based on an error correction capability of the outer code.11-18-2010
20100293431ERROR CORRECTION METHOD AND ERROR CORRECTION APPARATUS UTLIZING THE METHOD - An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.11-18-2010
20110010603METHOD FOR PREVENTING DATA SHIFT ERRORS AND CONTROLLER USING THE SAME - A method for preventing a data storage device from data shift errors is provided. First, data is encoded into an error correction code. The error correction code is then scrambled to obtain a scrambled code to be stored in a memory. The scrambled code is then retrieved from the memory to obtain first read-out data. The first read-out data is then descrambled to obtain a first descrambled error correction code. The first descrambled error correction code is then decoded to determine whether the first descrambled error correction code has uncorrectable errors. When the first descrambled error correction code has uncorrectable errors, the scrambled code stored in the memory is read again to output second read-out data without shift errors. Following, the second read-out data is then descrambled to obtain a second descrambled error correction code, and the second descrambled error correction code is then decoded to recover the data.01-13-2011
20110179334DIGITAL TELEVISION TRANSMITTER/RECEIVER AND METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER/RECEIVER - A digital television (DTV) transmitter and a method of processing data in the DTV transmitter are disclosed. A pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and for inserting known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. An RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet. And, a data interleaver interleaves the RS-coded main and enhanced data packets, wherein a known data sequence is included in every Nth enhanced data segment outputted from the data interleaver.07-21-2011
20120151295DEVICE AND METHOD FOR TURBO-ENCODING A BLOCK OF DATA - A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.06-14-2012
20110138249Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code - An apparatus for detecting an error within a plurality of coded binary words coded by an error correction code includes a combiner connected town error detector. The combiner generates a combined binary word by combining a first coded binary word and a second coded binary word of the plurality of coded binary words, so that the determined combined binary word is a code word of the error correction code if the first coded binary word and the second coded binary word are code words of the error correction code, and so that the combined binary word is not a code word of the error correction code if the first coded binary word or the second coded binary word is not a code word of the error correction code. Further, the error detector may determine an error detection bit sequence indicating whether or not the combined binary word is a code word of the error correction code.06-09-2011
20110154152ERROR CORRECTION MECHANISMS FOR 8-BIT MEMORY DEVICES - Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction.06-23-2011
20110197106WIRELESS TRANSMISSION DEVICE, WIRELESS RECEIVING DEVICE, AND METHOD FOR TRANSMITTING ENCODED DATA - Disclosed are a wireless transmission device, wireless receiving device, and method for transmitting encoded data with which power consumption can be reduced at the receiving end in accordance with reception conditions, while resource-saving is maintained by employing an erasure correcting code (ECC). In a wireless communication device (08-11-2011
20110219282DECODER AND APPARATUSES INCLUDING THE SAME - A decoder includes a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result. The decoder includes a second decoder configured to perform error correction on a symbol including the decision data according to the indicator data.09-08-2011
20080288847WIRELESS TRANSMIT/RECEIVE UNIT HAVING A TURBO DECODER WITH CIRCULAR REDUNDANCY CODE SIGNATURE COMPARISON AND METHOD - An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.11-20-2008
20090193314FORWARD ERROR CORRECTION FOR BURST AND RANDOM PACKET LOSS FOR REAL-TIME MULTI-MEDIA COMMUNICATION - This invention relates generally to a packet recovery algorithm for real-time (live) multi-media communication over packet-switched networks, such as the Internet. Such multi-media communication includes video, audio, data or any combination thereof. More specifically, the invention comprises a forward error correction (FEC) algorithm that addresses both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred. The transmitter calculates parity packets for the rows, columns and diagonals of a block of multi-media data packets using the exclusive or (XOR) operation and communicates the parity packets along with the multi-media data packets to the receiver. The receiver uses the parity packets to recover missing multi-media data packets in the block. The FEC algorithm is designed to be able to recover long bursts of consecutive missing data packets. If some parity packets are missing, they too can be recovered using an extra single parity packet, so that they can be used to recover other missing data packets. The invention applies to both one-way real-time streaming applications and two-way real-time interactive applications, and to both wired and wireless networks. The invention retains backwards compatibility with existing standards governing FEC for professional video over IP networks.07-30-2009
20090172495Methods and Apparatuses for Parallel Decoding and Data Processing of Turbo Codes - Methods and apparatuses for parallel decoding and data processing of Turbo codes are provided. The method includes: a codeword dividing step for dividing a whole codeword into Q sub-blocks to form a plurality of boundaries between adjacent sub-blocks of the Q sub-blocks so as to decode the Q sub-blocks, wherein the decoding process comprises P times of decoding iterations, and wherein Q is a positive integer and Q>1 and P is a positive integer and P>1; and a boundary moving step for moving at least one position of the boundaries formed in a pth decoding iteration by an offset Δ before performing a (p+n)th decoding iteration, wherein p is a positive integer and 1≦p07-02-2009
20120042224System and Method for Correcting Errors in Non-Volatile Memory Using Product Codes - A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.02-16-2012
20090077446SIGNAL SEGMENTATION METHOD AND CRC ATTACHMENT METHOD FOR REDUCING UNDETECTED ERROR - The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.03-19-2009
20100115373DISTRIBUTED TURBOCODER FOR BLOCK-FADING CHANNELS - A cooperative communications system comprising a source terminal, at least one relay terminal and a destination terminal. The system also comprises a distributed turbocoder over the source terminal and at least the relay terminal. The first part of the turbocoder residing on the source terminal and/or the second part of the turbocoder residing on the relay terminal is(are) equipped with a frequency scheduler (FS05-06-2010
20110167316METHOD AND DEVICE FOR ROW AND COLUMN INTERLEAVING OF BLOCKS OF VARIABLE SIZE - The present disclosure relates to a method for interleaving a stream of input data blocks, the method comprising steps of: subdividing a block into sub-blocks of fixed size in number of data rows and data columns, the sub-blocks being distributed in the block in rows of sub-blocks and in columns of sub-blocks, transferring the data contained in the block into a first memory, while respecting the order of the data in the input stream, transferring the data contained in the block by row of sub-blocks, into a second memory in which the data of each sub-block is accessible from the address of the sub-block, transferring the data of each sub-block by column of sub-blocks, from the second memory into a third memory, by putting back the data of each sub-block in data rows and columns, and transferring the data by data column from the third memory into an output stream.07-07-2011
20120210190ENCODING AND DECODING USING ELASTIC CODES WITH FLEXIBLE SOURCE BLOCK MAPPING - Data can be encoded by assigning source symbols to base blocks, assigning base blocks to source blocks and encoding each source block into encoding symbols, where at least one pair of source blocks is such they have at least one base block in common with both source blocks of the pair and at least one base block not in common with the other source block of the pair. The encoding of a source block can be independent of content of other source blocks. Decoding to recover all of a desired set of the original source symbols can be done from a set of encoding symbols from a plurality of source blocks wherein the amount of encoding symbols from the first source block is less than the amount of source data in the first source block and likewise for the second source block.08-16-2012
20120060071PRODUCT CODE DECODING METHOD AND DEVICE - A method for a decoding device to decode a codeword matrix of a product code includes: generating a first extended parity check matrix for a vertical code; decoding a horizontal codeword of a plurality of rows in the codeword matrix to thus perform a first decoding process; generating a second extended parity check matrix by removing a column corresponding to a row of the first decoding-succeeded horizontal codeword from the first extended parity check matrix; and decoding the first decoding-failed horizontal codeword by using the second extended parity check matrix to thus perform a second decoding process. Therefore, the simple and reliable product code decoding method is provided.03-08-2012
20120159281AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES - A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.06-21-2012
20120072801DATA PROCESSING APPARATUS, CONTROL DEVICE AND DATA STORAGE DEVICE - When write data D is high rewritten data, a PC 03-22-2012
20110107176METHOD AND APPARATUS FOR TRANSMITTING BROADCAST SIGNAL IN TRANSMITTER - A transmitting system, a receiving system, and a method of processing broadcast signals are disclosed. The method for transmitting a broadcast signal includes encoding mobile data for forward error correction (FEC) to build Reed-Solomon (RS) frames, dividing the built RS frames into a number of RS frame portions, dividing one of the RS frame portions into Serially Concatenated Convolutional Code (SCCC) blocks, mapping the SCCC blocks including the convolution-coded data to mobile data blocks according to a SCCC block mode which identifies relationship between the mobile data blocks and the SCCC blocks, forming a data group including the mobile data blocks, forming mobile data packets including data in the data group and, multiplexing a specified number of the mobile data packets, a first scalable number of the mobile data packets, and a second scalable number of main data packets.05-05-2011
20110099455Method and Arrangement for Decoding a Signal Encoded by a Tail-Biting Code - A method of decoding a signal that has been encoded by a tail-biting code based on at least one encoding parameter is disclosed. The at least one encoding parameter may be a trellis size or a quantity of aggregated encoding elements or a code rate. The method is suitable for use in a communication device and comprises receiving (04-28-2011
20110099454Low Complexity LDPC Encoding Algorithm - A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form04-28-2011
20110099453RECEIVING APPARATUS, RECEIVING METHOD, COMPUTER PROGRAM, AND RECEIVING SYSTEM - A receiving apparatus includes: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data; and a control means for controlling storage and output of the decoded data in and from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means.04-28-2011
201100994522D Product Code and Method for Detecting False Decoding Errors - The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.04-28-2011
20110099451Error control coding for single error correction and double error detection - An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P−(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.04-28-2011
20110113302TERMINAL TRANSMISSION APPARATUS FOR PROVIDING MULTIMEDIA SERVICE VIA SATELLITE COMMUNICATION LINK AND METHOD FOR PROVIDING MULTIMEDIA SERVICE USING THE SAME - The present invention separates inputted triple play IP data into Internet and TV data and voice (VoIP) data, encodes the Internet and TV data permitting a long delay time according to the existing DVB-S2 standard, and encodes the voice data permitting only a short delay time according to a DVB-RCS+M standard based 4K mode. Each encoded data is subjected to the orthogonal modulation and the orthogonally modulated voice data is subjected to a direct sequence spectrum spread according to a spreading factor. The spread spectrum signal is multiplexed in a SCPC frequency division multiple access (FDMA) scheme so as to overlap with frequencies allocated to each user.05-12-2011
20120233520Information Processing Apparatus and Information Processing Method - According to one embodiment, there is provided an information processing apparatus including: a flash memory storing data and a first error correcting code at a physical storage area thereof, the physical storage area including a plurality of blocks, each block including a plurality of columns; a first error correcting portion configured to perform, when there is an erroneous part in the data physically read from the flash memory, a first error correction based on the first error correcting code physically read from the flash memory to thereby correct the erroneous part; and a second error correcting portion configured to perform, when the erroneous part is not corrected through the first error correction, a second error correction based on a second error correcting code obtained from the read data to thereby correct the erroneous part.09-13-2012
20120233519METHOD FOR A GENERAL NEAR OPTIMAL TURBO CODE TRELLIS TERMINATION - A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the steps of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.09-13-2012
20120233518Data Processing Systems And Methods Providing Error Correction - A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.09-13-2012
20120131410ERROR CORRECTION CODE DECODING DEVICE - An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.05-24-2012
20120216093SOFT-DECISION NON-BINARY LDPC CODING FOR ULTRA-LONG-HAUL OPTICAL TRANSOCEANIC TRANSMISSIONS - Methods and systems for soft-decision non-binary low-density parity-check (LDPC) coding for ultra-long-haul optical transoceanic transmissions are provided. A receiver includes one or more maximum a posteriori (MAP) equalizers configured to decode one or more symbols of an encoded input stream to provide one or more symbol log-likelihood ratios (LLRs). One or more LLR estimators are configured to estimate the log-likelihood ratios of the one or more symbol LLRs to provide one or more bit LLRs. One or more non-binary LDPC decoders are configured to decode the input stream using the one or more bit LLRs to recover an original input stream.08-23-2012
20120131411MODULATION METHOD AND DEVICE IMPLEMENTING A DIFFERENTIAL MODULATION, CORRESPONDING DEMODULATION METHOD AND DEVICE, SIGNAL AND COMPUTER SOFTWARE PRODUCTS - A method and apparatus are provided for modulating a binary source sequence including of a plurality of source words to generate modulated symbols. The method implements error-correction encoding of the plurality of source words, implementing one or more encoding modules, each implementing a separate error-correction code to generate a plurality of code words, the source words being encoded in series. The code words are interlaced to generate an interlaced sequence. The interlaced sequence is differentially modulated to generate modulated symbols. Each code word is broken down into at least one group with a number of bits equal to the base-2 logarithm of a number of states of a modulation implemented by the step of differentially modulating. The interlacing step distributes the groups such that two adjacent groups in the interlaced sequence belong to separate code words.05-24-2012
20100205506DATA MODULATING DEVICE AND METHOD THEREOF - A data modulating device includes: an LDPC encoding unit configured to execute LDPC encoding; and a balance encoding unit configured to input a data string subjected to encoding by the LDPC encoding unit as data to be encoded, and convert k bits of this data to be encoded into balance code made up of m-bit block data; with the balance encoding unit executing balance encoding of said data to be encoded using a data conversion table subjected to mapping so that a set of the k-bit data patterns of which the Hamming distance is 1 corresponds to a set of block data of which the Hamming distance is 2.08-12-2010
20110185253DIRECTORY FILE SYSTEM IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data storage request, wherein the data storage request includes data and a data identifier (ID). The method continues with the processing module dispersed storage error encoding the data to produce a set of encoded data slices and determining a data dispersed storage network (DSN) address. The method continues with the processing module sending the set of encoded data slices to a DSN memory for storage at the data DSN address and updating a directory file with path information corresponding to the data ID and the data DSN address to produce an updated directory file. The method continues with the processing module dispersed storage error encoding the updated directory file to produce a set of encoded updated directory slices and sending the set of encoded updated directory slices to the DSN memory for storage at a directory DSN address.07-28-2011
20110185255ENCODING/TRANSMITTING APPARATUS AND ENCODING/TRANSMITTING METHOD - An encoding/transmitting apparatus that is used to transmit moving-picture data from a transmitting side to a receiving side through a transmission path and to subject the moving-picture data to streaming in the receiving side has an external-output request determining unit that monitors the state of a network. If the network assumes an undesirable state, the request determining unit causes a multiplex output unit to stop multiplexing data. When the network assumes a desirable state, the multiplex unit starts multiplexing the data again. A video encoding unit and an audio encoding unit keep encoding data, whether the multiplex output unit is multiplexing data or not. When the area occupied by encoded data in an encoded-video-data storage unit and the area occupied by encoded data in an encoded-audio-data storage unit exceed a predetermined value, the encoding units stop encoding data, and wait until the area occupied by encoded data sufficiently decreases.07-28-2011
20110185254ERROR DETECTION AND CORRECTION SCHEME FOR A MEMORY DEVICE - Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.07-28-2011
20110185252CODING PATTERN COMPRISING MULTI-PPM DATA SYMBOLS WITH DIFFERENT LAYOUTS - A substrate having a coding pattern disposed thereon or therein. The coding pattern comprises a plurality of macrodots encoding first and second Reed-Solomon data symbols. Each first Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values. Each second Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a second symbol layout which is different than the first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values.07-28-2011
20100299575METHOD AND SYSTEM FOR DETECTION AND CORRECTION OF PHASED-BURST ERRORS, ERASURES, SYMBOL ERRORS, AND BIT ERRORS IN A RECEIVED SYMBOL STRING - Embodiments of the present invention include ECC-based encoding-and-decoding schemes that are well suited for correcting phased bursts of errors or erasures as well as additional symbol errors and bit errors. Each encoding-and-decoding scheme that represents an embodiment of the present invention is constructed from two or more component error-correcting codes and a mapping function ƒ(). The composite error-correcting codes that represent embodiments of the present invention can correct longer phased bursts or a greater number of erasures in addition to single-bit errors and symbol errors, respectively, than either of the component codes alone, and are more efficient than previously developed ECC-based encoding-and-decoding schemes for correcting phased bursts of symbol errors and erasures combined with additional bit errors and symbol errors.11-25-2010
20120272119ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS - A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.10-25-2012
20100050048MITIGATION OF FIBER NONLINEARITIES IN MULTILEVEL CODED-MODULATION SCHEMES - A receiver and method are provided for mitigation of finer non-linearities in multilevel coded-modulation schemes. The receiver includes a multilevel Bahl-Cocke-Jelinek-Raviv (BCJR) equalizer configured to receive channel samples of an input signal, partially mitigate fiber non-linearities, and provide symbol reliabilities. The receiver further includes a bit probabilities module coupled to the BCJR equalizer configured to calculate soft bit reliabilities from the symbol reliabilities. The receiver also includes one or more low-density parity-check (LDPC) decoders coupled to the bit probabilities module and the BCJR equalizer, configured to receive the soft bit reliabilities and output code words. The one or more LDPC decoders iteratively provide extrinsic soft information feedback to the BCJR equalizer to compensate for the fiber non-linearities.02-25-2010
20100050047DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN THE DIGITAL BROADCASTING SYSTEM - A digital broadcasting system and a data processing method are disclosed. A receiving system of the digital broadcasting system includes a receiving unit, a demodulator, an equalizer, a block decoder, and a RS frame decoder. The receiving unit receives a broadcast signal including mobile service data and main service data. The mobile service data may configure a RS frame. The RS frame includes at least one data packet for the mobile service data, RS parity generated based on the at least one data packet, and CRC checksum generated based on the at least one data packet and the RS parity. The demodulator converts RS frame data included in the broadcast signal received by the receiving unit into a baseband RS frame data. The equalizer performs channel equalization on the data demodulated by the demodulator. The block decoder performs symbol-decoding on the data channel-equalized by the equalizer in block units. The RS frame decoder performs CRC-decoding and RS-decoding on the decoded mobile service data in RS frame units, thereby correcting errors occurred in the mobile service data within the RS frame.02-25-2010
20100011275Methods, Apparatuses, Systems, and Architectures for Quickly and Reliably Encoding and/or Decoding System Data - Methods, apparatuses, systems, and architectures for providing fast, independent, and reliable retrieval of system data (e.g., metadata) from a storage system, which enables minimal degradation in the reliability of user data. Methods generally include encoding the system data at least twice, at least once independently and at least once jointly along with user data. Methods can also include decoding the system data first, and upon a decoding failure, jointly decoding the system data and the user data.01-14-2010
20120254685READDRESSING DECODER FOR QUASI-CYCLIC LOW-DENSITY PARITY-CHECK AND METHOD THEREOF - A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.10-04-2012
20120317457HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.12-13-2012
20120185748Method and Apparatus for Applying Forward Error Correction in 66B Systems - A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity blocks using the 66b code format, wherein the parity is calculated over the data blocks; and generating an FEC codeword using the data blocks and the FEC parity blocks.07-19-2012
20120185747METHODS OF ENCODING/DECODING FOR ERROR CORRECTION CODE UTILIZING INTERDEPENDENT PORTIONS OF CODEWORDS AND RELATED CIRCUITS - A method of encoding/decoding data for storage in and retrieval from a flash memory device, can be provided by generating a first error correction code on a combination of first user data to be stored in a first logical unit of storage in the flash memory device and padding data that is derived from second user data and an associated second error correction code stored in a second logical unit of storage in the flash memory device that is directly adjacent to the first logical unit of storage. The first user data and the first error correction code can be stored in the first logical unit of storage.07-19-2012
20120221918SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.08-30-2012
20120084623ERROR CORRECTION METHOD AND DATA REPRODUCTION DEVICE - The error correction processing includes: data reproduction processing of reproducing recording data, constituted by a plurality of data units each made of a plurality of bits, from a recording medium sequentially; error correction processing of performing error correction in the row direction and error correction in the column direction at least once for an error correction code block that has the reproduced recording data arranged in the row direction over a plurality of rows; determination processing of determining whether uncorrectable data is left behind after execution of the error correction processing; and erasure correction processing of performing, when it is determined that uncorrectable data is left behind, column-direction error correction considering data constituting at least one row of the error correction code block as erasure data, even in cases where uncorrectable data in the error correction in the row direction is not left behind.04-05-2012
20120084621DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital broadcast system and a method of processing data are provided. The transmitting system of the digital broadcast system includes an encoder for encoding mobile data for FEC to build RS frames, a signaling encoder for encoding TPC data including the RS frame mode information, a divider for dividing at least one of the RS frames into a plurality of portions, a block processor for converting one portion to a plurality of SCCC blocks, a converter for converting the SCCC blocks to data blocks, a group formatter for forming data groups, a packet formatter for forming data packets including data in the data groups, a multiplexer for multiplexing main data packets including main data and the data packets, a trellis encoder for performing trellis encoding on data in the multiplexed data packets and a transmission unit for transmitting the broadcast signal including a parade of the data groups.04-05-2012
20120260144ENCODING AND DECODING TECHNIQUES USING LOW-DENSITY PARITY CHECK CODES - Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.10-11-2012
20120221917ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.08-30-2012
20090019334ERROR CORRECTION SYSTEM USING CONCATENATED CODES - This invention provides an error correction system whereby codes, including codes known to be optimum, may be concatenated together so that a longer code is produced which may be decoded by decoding the individual codes using any type of error correcting decoder including list decoders, Dorsch decoders in particular, and iterative decoders. The concatenated code consists of one or more codes having replicated codewords to which are added codewords from one or more other codes. The code construction is utilised in the receiver with a decoder that firstly decodes one or more individual codewords from a received vector. The detected codewords from this first decoding are used to undo the code concatenation within the received vector to allow the replicated codewords to be decoded. Examples of the performance benefits of the invention in comparison to the well known state of the art coding arrangement of LDPC codes, and turbo codes using iterative decoders are given for (256,128) and (512,256) codes.01-15-2009
20090019336MEMORY AND 1-BIT ERROR CHECKING METHOD THEREOF - A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 201-15-2009
20080301519SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM, AND ERROR CORRECTION METHOD FOR SEMICONDUCTOR MEMORY - Aspects of the embodiment include providing a semiconductor memory comprising; a plurality of memory blocks that includes a plurality of regular memory cells; a plurality of first parity blocks that are disposed in accordance with the plurality of memory blocks, wherein the plurality of first parity blocks include a first parity memory cell holding a first parity code; a second parity block that includes a second parity memory cell holding a second parity code having a parity bit corresponding to the first parity code; a parity error correction unit that corrects an error of the first parity code using the second parity code; and a data error correction unit that corrects an error of the data stored in a regular memory cell using the first parity code corrected by the parity error correction unit.12-04-2008
20120240005DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.09-20-2012
20120266042HEADER ENCODING/DECODING - In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data.10-18-2012
20120324310SEMICONDUCTOR DEVICE AND METHOD OF WRITING DATA TO SEMICONDUCTOR DEVICE - A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.12-20-2012
20110239082METHOD FOR ENHANCING ERROR CORRECTION CAPABILITY OF A CONTROLLER OF A MEMORY DEVICE WITHOUT INCREASING AN ERROR CORRECTION CODE ENGINE ENCODING/DECODING BIT COUNT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing error correction capability of a controller of a memory device without increasing an Error Correction Code (ECC) engine encoding/decoding bit count includes: regarding a plurality of rows of a data bit array, respectively calculating a plurality of first parity codes; regarding a plurality of sets of columns of the data bit array, respectively calculating a plurality of second parity codes, wherein each set of the sets includes two or more of the columns, and the sets do not overlap; and performing encoding/decoding corresponding to the first and the second parity codes. An associated memory device and the controller thereof are further provided.09-29-2011
20120278680SET PARTITIONING AND MULTILEVEL CODING - A signal is encoded by receiving input data. A first portion of the input data is encoded to obtain a first set of encoded data. At least some part of the input data is processed to determine which one of a plurality of subsets the input data corresponds to. In the event the input data corresponds to a first subset having a greater signal margin (SM) than a second subset, the first set of encoded data and a second portion of the input data are output. In the event the input data corresponds to the second subset, the second portion of the input data is encoded to obtain a second set of encoded data and the first set of encoded data and the second set of encoded data are output.11-01-2012
20110258511AUTOMATIC ERROR CONTROL SCHEME SELECTION FOR FIXED-LENGTH MESSAGES BASED UPON MESSAGE PAYLOAD SIZE - A communication system enabling wireless transmission of messages via packets; and a method of operating the system provides for improved accuracy in the transmission of a message, particularly for overcoming signal distortion associated with the phase changes and varying multipath found in transmissions from the locomotive of a moving train. The maximum benefit of forward-error correction (FEC) with Reed-Solomon (RS) coding is applied for a message payload that is significantly shorter than the fixed length of a packet, with lesser coding being performed with longer payloads.10-20-2011
20100229070Erasures Assisted Block Code Decoder And Related Method - An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.09-09-2010
20120331368SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.12-27-2012
20120331367Nested Multiple Erasure Correcting Codes for Storage Arrays - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to t12-27-2012
20110320908USER DATA BROADCAST MECHANISM - This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.12-29-2011
20130013974DATA ENCODING IN SOLID STATE STORAGE DEVICES - Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=p01-10-2013
20100146368PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE - A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.06-10-2010
20100131820DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA THEREOF - A digital broadcasting system and data processing method are disclosed, which are highly resistant to channel changes and noise. The present invention includes receiving a broadcast signal having mobile service data and main service data multiplexed with each other from at least one parade, demodulating the broadcast signal, acquiring program table information describing at least one service included in at least one ensemble from the demodulated broadcast signal and decoding the mobile service data associated with a first service using a program table information transport unit in the acquired program table information.05-27-2010
20120151293Sequenced Two-Dimensional Codes in Video - One embodiment described herein may take the form of a system or method for generating and/or receiving a plurality of sequenced matrix codes, such as QR codes, containing information such that the matrix codes may be decoded and analyzed in sequence to retrieve the stored information. In one embodiment, sequencing information may be embedded in one or more of the plurality of sequenced matrix codes to aid in receiving and decoding the codes in the proper and intended order. This sequencing information may be retrieved and maintained by a reader device to ensure that each matrix code in the sequence is received. Further, the plurality of sequenced matrix codes may be provided through a series of images, such as a video component of a multimedia presentation that may be received by the reader device.06-14-2012
20130019138DATA PROCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICEAANM Liang; Li-ChunAACI Kaohsiung CityAACO TWAAGP Liang; Li-Chun Kaohsiung City TW - A data processing method is provided. A data is compressed to obtain a compressed data. Compression information corresponding to the compressed data is obtained. Error checking and correcting (ECC) codes are respectively generated for the compression information and the compressed data. The compression information, the compressed data, and the ECC codes are respectively written into a rewritable non-volatile memory module. The compression information, the compressed data, and the ECC codes are respectively read from the rewritable non-volatile memory module. An ECC procedure is preformed on the compression information according to the corresponding ECC code, so as to obtain a storage state when the compression information is written. An ECC procedure is preformed on the compressed data according to the storage state of the compression information and the ECC code corresponding to the compressed data, so as to obtain a storage state when the compressed data is written.01-17-2013
20130024741DATA PROCESSING METHOD, DATA PROCESSING SYSTEM, AND RECEIVER - The present invention provides a data processing method, a data processing system and a receiver. The method includes: performing optical-to-electrical conversion processing on a received current optical data signal, to generate a current electric data signal; performing analog-digital conversion processing on the current electric data signal, to generate a current data block; performing equalization processing on the current data block according to a previous second output data block, to generate a current first output data block, where the previous second output data block is generated by performing forward error correction decoding processing on a previous first output data block, and the previous first output data block is generated by performing equalization processing on a previous data block of the current data block; and performing forward error correction decoding processing on the current first output data block, to generate a current second output data block.01-24-2013
20130173984FORWARD ERROR CORRECTION (FEC) CONVERGENCE BY CONTROLLING RELIABILITY LEVELS OF DECODED WORDS IN A SOFT FEC DECODER - A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.07-04-2013
20130173985METHOD OF READING DATA FROM STORAGE DEVICE, ERROR CORRECTION DEVICE AND STORAGE SYSTEM INCLUDING ERROR CORRECTION CODE DECODER - Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data.07-04-2013
20130173986MEMORY CONTROLLER, DATA STORAGE DEVICE, AND MEMORY CONTROLLING METHOD - A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host.07-04-2013
20130173987Method and Apparatus for Dispersed Storage Memory Device Utilization - A method begins with a processing module receiving data for storage. The method continues with the processing module determining storage metadata regarding storage requirements of the data. When the storage metadata includes a first type of storage mode, the method continues with the processing module determining a first error coding dispersal storage function; identifying first memory of DSN memory; encoding the data in accordance with the first error coding dispersal storage functions; and outputting the first encoded data slices to the first memory for storage therein. When the storage metadata includes a second type of storage mode, the method continues with the processing module determining a second error coding dispersal storage function; identifying second memory of a dispersed storage network (DSN) memory; encoding the data in accordance with the second error coding dispersal storage functions; and outputting the second encoded data slices to the second memory for storage therein.07-04-2013
20080256412TRANSPORT STREAM GENERATING APPARATUS, TURBO PACKET DEMULTIPLEXING APPARATUS, AND METHODS THEREOF - A transport stream generating apparatus, a turbo packet demultiplexing apparatus, and methods thereof, the transport stream generating apparatus including: a Reed Solomon (RS) encoder to RS-encode turbo data, an interleaver to interleave the RS-encoded turbo data, a duplicator to add a parity insertion area to the interleaved turbo data, and a multiplexer to multiplex normal data and the turbo data processed by the duplicator to generate a transport stream. Accordingly, reception performance can be improved in an advanced vestigial sideband (AVSB) system.10-16-2008
20080229172High Rate Turbo Encoder and Recoder for Product Codes - The invention relates to a Method of decoding a matrix built from concatenated codes, corresponding to at least two elementary codes, with uniform interleaving, this matrix having n09-18-2008
20080229171Serial Concatenated Convolutional Code Decoder - A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory (09-18-2008
20110246852SYSTEM AND METHOD FOR RESTORING DAMAGED DATA PROGRAMMED ON A FLASH DEVICE - A system and a method for restoring damaged data programmed on a memory, such as a Flash memory, including detecting a failure of a memory controller to successfully decode encoded data using a first decoding algorithm, performing soft sampling of the encoded data to provide soft samples of the encoded data, applying, for example, by a computer coupled to the memory controller, a second decoding algorithm on the soft samples of the encoded data. The second decoding algorithm may have an error correction capability exceeding an error correction capability of the first decoding algorithm10-06-2011
20110246851Transmission device, transmission method and program - A transmission device includes a first conversion unit converting first transmission target data into first transmission data formed by N symbol values, with predetermined units of data, based on a first conversion table, a second conversion unit converting first error correction data into first symbol data formed by the a symbol values, based on a second conversion table, a third conversion unit converting second transmission target data into second symbol data formed by the (N-a) symbol values, based on a third conversion table, an addition and generation unit adding the second symbol data to the first symbol data and generating second transmission data formed by the N symbol values, and a transmission unit transmitting a transmission signal formed by the first and second transmission data.10-06-2011
20080222484Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving - A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.09-11-2008
20130179748SYSTEMS AND METHODS FOR ERROR CHECKING AND CORRECTING FOR MEMORY MODULE - Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity.07-11-2013
20110314353DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.12-22-2011
20130124940MEMORY CONTROLLER WITH LOW DENSITY PARITY CHECK CODE DECODING CAPABILITY AND RELEVANT MEMORY CONTROLLING METHOD - A memory controller is disclosed, having a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.05-16-2013
201301327942D PRODUCT CODE AND METHOD FOR DETECTING FALSE DECODING ERRORS - The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.05-23-2013
20130132793ENCODING, DECODING, AND MULTI-STAGE DECODING CIRCUITS FOR CONCATENATED BCH, AND ERROR CORRECTION CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME - The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.05-23-2013
20100281334SYSTEMS AND METHODS FOR COMMUNICATIONS - Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied.11-04-2010
20110214031ERROR CORRECTION DECODER, ERROR CORRECTION VALUE GENERATOR, AND ERROR CORRECTION SYSTEM - An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal.09-01-2011
20110239081SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, write data is written in a nonvolatile semiconductor memory with a first error correction code and a second error correction code attached to the write data. The first error correction code and the write data are read out from the nonvolatile semiconductor memory to perform first error correction processing. When there is a remaining error, the second error correction code corresponding to the write data is read out to carry out second error correction processing.09-29-2011
20130132795SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, AND ERROR CORRECTION SYSTEM - A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code).05-23-2013
20100318878COMMUNICATIONS CHANNEL PARALLEL INTERLEAVER AND DE-INTERLEAVER - A parallel interleaver that operates to interleave convolutionally and turbo encoded data packets is described. Packets are divided into subpackets and interleaved in parallel for improved performance. The Pruned Bit Reversal Interleaver (PBRI) function used to generate interleaver addresses is invertible such that its inverse function can be used to generate de-interleaver addresses. For convolutionally encoded subpackets, encoder output bits are demultiplexed into three sequences V12-16-2010
20100318877ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.12-16-2010
20120284585Systems and Methods for Queue Based Data Detection and Decoding - Various embodiments of the present invention provide systems and methods for variable iteration data processing.11-08-2012
20120284584DECODING METHOD AND DEVICE FOR CONCATENATED CODE - Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes: carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.11-08-2012
20110289376ENHANCED MULTILEVEL MEMORY - Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.11-24-2011
20130191696PARITY FRAME - A method of forward error correction in an optical communications system. A signal to be transmitted is logically defined as a super-frame comprising a plurality of frames including a parity frame and a predetermined set of data frames. Each frame of the super-frame is processed in accordance with a first FEC scheme having a known error correlation characteristic. At least the set of data frames is processed in accordance with a second FEC scheme which is selected based on the error correlation characteristic of the first FEC scheme.07-25-2013
20130191697ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.07-25-2013
20120030538Forward Error Correction Decoding - A system may be used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder may receive an input bit stream and process it to produce an output bit stream, which may be convolutionally encoded. K-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the bits marked for erasure.02-02-2012
20120030537SYMBOL ENCODING FOR TOLERANCE TO SINGLE BYTE ERRORS - The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.02-02-2012
20120030536Initializing Decoding Metrics - A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.02-02-2012
20130198582SUPERCHARGED CODES - A system and method is provided for encoding k input symbols into a longer stream of n output symbols for transmission over an erasure channel such that the original k input symbols can be recovered from a subset of the n output symbols without the need for any retransmission. A symbol is a generic data unit, consisting of one or more bits, that can be, for example, a packet. The system and method utilize a network of erasure codes, including block codes and parallel filter codes to achieve performance very close to the ideal MDS code with low encoding and decoding computational complexity for both small and large encoding block sizes. This network of erasure codes is referred to as a supercharged code. The supercharged code can be used to provide packet-level protection at, for example, the network, application, or transport layers of the Internet protocol suite.08-01-2013
20120042225DATA STORAGE WITH AN OUTER BLOCK CODE AND A STREAM-BASED INNER CODE - Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.02-16-2012
20120066565DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.03-15-2012
20120066564Differential Encoding With Adaptive Resetting - To feedback MIMO channel conditions, a codeword from a codebook is selected. To reduce signalling, the codewords are organized into codeword subsets. The receiver signals an index of a codeword into a current 5 codeword subset previously made known to the transmitter. The current codeword subset is adaptively selected based on a threshold criterion. For example, if the best codeword from the current codeword subset is not sufficiently similar to the best codeword in the full codebook, a switch in the codeword subset is made.03-15-2012
20120079344DETECTION, AVOIDANCE AND/OR CORRECTION OF PROBLEMATIC PUNCTURING PATTERNS IN PARITY BIT STREAMS USED WHEN IMPLEMENTING TURBO CODES - Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.03-29-2012
20120084624DTV TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA - A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and encodes the frame two times for first and second error correction, respectively. It further permutes a plurality of encoded data frames. The randomizer randomizes the permuted enhanced data, and the block processor codes the randomized data at a rate of 1/N1. The group formatter forms a group of enhanced data having one or more data regions and inserts the data coded at the rate of 1/N1 into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into enhanced data packets.04-05-2012
20120084622SYSTEM AND METHOD OF DATA ENCODING - A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.04-05-2012
20130091402STRONG SINGLE AND MULTIPLE ERROR CORRECTING WOM CODES, CODING METHODS AND DEVICES - Preferred embodiments of the invention provide WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. Preferred codes of the invention also the following property: if the code corrects two/three errors it has two/three parts of redundancy bits. For double error correction, if only one part of the redundancy bit has no errors then it is possible to correct one error. For triple error correction, if only one/two parts of the redundancy bits have no errors then it is possible to correct one/two errors. Preferred methods of the invention use codes that correct/detect a single, two and three cell-erasures. A preferred method of the invention applies a code that has three roots, ah a2, a3, each of which is a primitive element and where every pair of roots generates a double error correcting code. Methods of the invention further provide and utilize codes utilitizing a triple error correcting WOM code that can correct an arbitrary number of errors.04-11-2013
20130091401FEEDBACK SIGNALING ERROR DETECTION AND CHECKING IN MIMO WIRELESS COMMUNICATION SYSTEMS - A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.04-11-2013
20130091400Systems and Methods for Parity Shared Data Encoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a low density parity check encoding system is described that includes: a low density parity check encoder circuit, and a combining circuit. The low density parity check encoder circuit is operable to encode a first data set to yield a first low density parity check encoded sub-codeword, and to encode a second data set to yield a second low density parity check encoded sub-codeword. The combining circuit is operable to: generate a composite low density parity check sub-codeword by mathematically combining at least the first low density parity check encoded sub-codeword and the second low density parity check encoded sub-codeword; and combine at least the first low density parity check encoded sub-codeword and the composite low density parity check sub-codeword into an overall codeword.04-11-2013

Patent applications in class Double encoding codes (e.g., product, concatenated)

Patent applications in all subclasses Double encoding codes (e.g., product, concatenated)