Class / Patent application number | Description | Number of patent applications / Date published |
714753000 | Double error correcting with single error correcting code | 9 |
20090094502 | DIGITAL BROADCASTING TRANSMISSION SYSTEM, AND A SIGNAL PROCESSING METHOD THEREOF - A digital broadcasting transmission system, and a signal processing method thereof, includes a parity area generating unit preparing a first area for parity insertion with respect to a dual transport stream (TS) which includes a normal stream and a turbo stream as multiplexed, a first interleaver interleaving the dual TS which is transmitted from the parity area generating unit, a turbo processing unit detecting the turbo stream from the interleaved dual TS, exclusively encoding the detected turbo stream for turbo-processing, and stuffing the encoded turbo stream into the dual TS, a deinterleaver deinterleaving the dual TS which is processed by the turbo processing unit, and a transmitting unit transmitting the dual TS which is processed at the deinterleaver. | 04-09-2009 |
20090106623 | METHOD FOR TURBO TRANSMISSION OF DIGITAL BROADCASTING TRANSPORT STREAM, A DIGITAL BROADCASTING TRANSMISSION AND RECEPTION SYSTEM, AND A SIGNAL PROCESSING METHOD THEREOF - A digital broadcasting transmission/reception system, and a signal processing method thereof for turbo-processing digital broadcasting transport stream and transmitting the processed stream, includes a parity area generating unit preparing a first area for parity insertion with respect to a dual transport stream (TS) which includes a normal stream and a turbo stream as multiplexed, a first interleaver interleaving the dual TS which is transmitted from the parity area generating unit, a turbo processing unit detecting the turbo stream from the interleaved dual TS, exclusively encoding the detected turbo stream for turbo-processing, and stuffing the encoded turbo stream into the dual TS, a deinterleaver deinterleaving the dual TS which is processed by the turbo processing unit, and a transmitting unit transmitting the dual TS which is processed at the deinterleaver. | 04-23-2009 |
20100269012 | High Density High Reliability Memory Module with Power Gating and a Fault Tolerant Address and Command Bus - An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices. | 10-21-2010 |
20110055658 | CONTENT DISTRIBUTION METHOD, ENCODING METHOD, RECEPTION/REPRODUCTION METHOD AND APPARATUS, AND PROGRAM - There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder | 03-03-2011 |
20110320907 | DATA PROCESSING CIRCUIT AND DATA PROCESSING METHOD - A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit. | 12-29-2011 |
20130139028 | Extended Bidirectional Hamming Code for Double-Error Correction and Triple-Error Detection - An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2 | 05-30-2013 |
20140013181 | Error Correction Coding Using Large Fields - An improved error correction system, method, and apparatus provides encoded sequences of finite field symbols, each with a plurality of associated weighted sums equal to zero, and decodes encoded sequences with a limited number of corruptions. Each of the multiplicative weights used in the weighted sums is preselected from a smaller subfield of a large finite field. Decoding proceeds by determining multiplicative weights using various operations over the smaller subfield. When a limited number of corruptions occur, improved system design ensures that the probability of decoding failure is small. The method and apparatus extend to determine one or more decoding solutions of an underdetermined set of equations, including detection of ambiguous solutions. | 01-09-2014 |
20150341055 | DOUBLE BIT ERROR CORRECTION IN A CODE WORD WITH A HAMMING DISTANCE OF THREE OR FOUR - A method for determining the erroneous bits in an initial binary word affected by a double error and arising from a code endowed with a minimum Hamming distance equal to 3 or 4 comprises reception of a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, a step of generating the syndrome on the basis of the initial word and a step of determining whether the syndrome is that of a code word affected by a double error, in which if it identifies, on the basis of the syndrome, an error in the initial word whose two affected bits correspond to bits of low confidence in the initial word, the two erroneous bits are selected to be corrected. The method applies notably to the fields of error correcting codes and nanometric technologies. | 11-26-2015 |
20150341056 | DEVICE FOR CORRECTING TWO ERRORS WITH A CODE OF HAMMING DISTANCE THREE OR FOUR - A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means. | 11-26-2015 |