# Forward correction by block code

## Subclass of:

## 714 - Error detection/correction and fault detection/recovery

## 714699000 - PULSE OR DATA ERROR HANDLING

## 714746000 - Digital data error correction

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

714763000 | Memory access | 1331 |

714758000 | Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity) | 529 |

714755000 | Double encoding codes (e.g., product, concatenated) | 384 |

714776000 | For packet or frame multiplexed data | 344 |

714781000 | Code based on generator polynomial | 258 |

714780000 | Using symbol reliability information (e.g., soft decision) | 76 |

714777000 | Hamming code | 36 |

714762000 | Burst error correction | 31 |

714774000 | Adaptive error-correcting capability | 27 |

714759000 | Look-up table encoding or decoding | 21 |

714757000 | Parallel generation of check bits | 18 |

714760000 | Threshold decoding (e.g., majority logic) | 15 |

714775000 | Synchronization | 14 |

714754000 | Error correction during refresh cycle | 10 |

714779000 | Variable length data | 8 |

714753000 | Double error correcting with single error correcting code | 7 |

714761000 | Random and burst error correction | 3 |

20090187807 | METHOD FOR OPTIMIZING BLOCK CODING PARAMETERS, A COMMUNICATIONS CONTROLLER EMPLOYING THE METHOD AND A COMMUNICATIONS NODE AND LINK EMPLOYING THE CONTROLLER - A method of determining optimal FEC configuration parameters, a communications controller, a communications link and a communications node is disclosed. In one embodiment, the communications controller, includes: (1) a processor, (2) a communications system information collector configured to receive operational information from a communications system having a block encoder, a block decoder and a decision feedback equalizer, (3) a code determiner configured to employ the operational information to select, from a set of candidate codes, a random error correction code or a burst error correction code that has a least error correction capability and satisfies a target performance specification for the communications system and (4) a parameter selector configured to select configuration parameters associated with the selected random error correction code or the selected burst error correction code and send the selected configuration parameters to the block encoder and the block decoder. | 07-23-2009 |

20120047417 | OPERATION UNIT AND PROGRAM - In an embodiment, regarding an addition of a kb-bit number A and a b-bit random number r, element data of a pre-calculated table C′ is set based on a sum A | 02-23-2012 |

20140181618 | ERROR DETECTION AND CORRECTION APPARATUS AND METHOD - Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed. | 06-26-2014 |

Entries | ||

Document | Title | Date |
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20110179333 | LOWER-COMPLEXITY LAYERED BELIEF PROPAGATION DECODING LDPC CODES - Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures. | 07-21-2011 |

20110185251 | SYSTEM AND METHOD TO CORRECT DATA ERRORS USING A STORED COUNT OF BIT VALUES - In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine. | 07-28-2011 |

20080222482 | TRANSMITTER AND RECEIVER - There is provided with a transmitter including: an input unit configured to input a data symbol sequence; a block generator configured to sequentially generate data blocks each including a plurality of data symbols by using the data symbol sequence; an addition unit configured to add a duplicate of h data symbols at an end of a first data block to a head of the first data block as a cyclic prefix to obtain a first data block with the cyclic prefix; and a transmission unit configured to transmit the first data block with the cyclic prefix, wherein the block generator uses, as k data symbols that precede the h data symbols at the end of the first data block, a duplicate of k data symbols at an end of a second data block that precedes the first data block. | 09-11-2008 |

20080222481 | MULTIPLE PROTECTION GROUP CODES HAVING MAXIMALLY RECOVERABLE PROPERTY - A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable. | 09-11-2008 |

20080222480 | ERASURE-RESILIENT CODES HAVING MULTIPLE PROTECTION GROUPS - A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable. | 09-11-2008 |

20120192028 | ITERATIVE DECODING OF SIGNALS RECEIVED OVER A NOISY CHANNEL USING FORWARD AND BACKWARD RECURSIONS WITH WARM-UP INITIALIZATION - A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window. The decoding further comprises, for each repeated recursion: alternating the direction of the warm-up runs between forward and reverse with each successive iteration over the sequence, storing one of the sets of state metrics from each window, and initialising the warm-up run of each window using a corresponding stored set of state metrics from a previous iteration. | 07-26-2012 |

20120192027 | Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme - The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks. | 07-26-2012 |

20100058139 | Method for constructing large-girth quasi-cyclic low-density parity-check codes - A method constructs a code, wherein the code is a large-girth quasi-cyclic low-density parity-check code. A base matrix is selected for the code. A cost matrix corresponding to the base matrix is determined. A single element in the base is changed repeatedly maximize a reduction in cost. A parity check matrix is constructing for the code from the base matrix when the cost is zero, and an information block is encoded as a code word using the parity check matrix in an encoder. | 03-04-2010 |

20100275088 | LOW-LATENCY DECODER - In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated. | 10-28-2010 |

20110314352 | REDUCED-COMPLEXITY LDPC DECODING - Methods and systems for reduced-complexity decoding of low-density parity-check (LDPC) information. An encoded input stream is received. The received stream is decoded with one or more reduced-complexity min-sum or a posteriori probability LDPC decoders. A v-node update rule in the reduced complexity decoder is omitted. | 12-22-2011 |

20100325514 | DECODING METHOD AND DECODING DEVICE - In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs. | 12-23-2010 |

20090125780 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals. A symbol interleaver is arranged in operation to read-into a symbol interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals. The set of addresses are generated by an address generator which has been optimised to interleave the data symbols on to the sub-carrier signals of the OFDM carrier signals for a given operating mode of the OFDM system, such as a 32K operating mode for DVB-T2 or DVB-C2. | 05-14-2009 |

20090193312 | FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS - Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities. | 07-30-2009 |

20120246537 | ERROR CORRECTION METHOD AND DEVICE - Provided is an error correction method for an optical communication system that transmits a transmission frame formed of information data added with an overhead and an error correction code, the error correction method including adjusting a size of an FEC redundant area of an FEC frame for storing client signals of different signal types in accordance with the client signals so that transmission rates of the FEC frame for the respective client signals have an approximately N-multiple relationship (N is a positive natural number). With this, it is possible to obtain an error correction method and device capable of providing a high-quality and high-speed optical communication system without performance degradation caused by jitter or the like and with the common use of circuits having a reduced circuit scale. | 09-27-2012 |

20120246536 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes. | 09-27-2012 |

20140344639 | APPARATUS AND METHOD FOR CODING/DECODING BLOCK LOW DENSITY PARITY CHECK CODE IN A MOBILE COMMUNICATION SYSTEM - A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix. | 11-20-2014 |

20110320904 | System and Method Having Optimal, Systematic q-Ary Codes for Correcting All Asymmetric and Symmetric Errors of Limited Magnitude - A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided. | 12-29-2011 |

20140164865 | ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS - An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations. | 06-12-2014 |

20090144599 | METHOD FOR EVALUATING THE OPERATING SAFETY OF A SYSTEM - Evaluating the operating safety of a complex software and or hardware system such as a system for displaying flight information on an instrument panel of an aircraft. The evaluation method includes construction of a first architecture of the system, divided into several blocks each comprising data inputs/outputs, the inputs of a block being connected to the outputs of other blocks in the first architecture; identification of failures of the outputs of the blocks of the architecture; construction of first boolean expressions expressing the states of the outputs of the blocks of the first architecture as a function of the states of the identified failures, of the states of the inputs of the blocks; definition of a first feared event to be examined by a second boolean expression constructed based on the first boolean expressions; and reduction of the second boolean expression in a sum of monomials. | 06-04-2009 |

20150039960 | ENCODING AND DECODING TECHNIQUES USING LOW-DENSITY PARITY CHECK CODES - Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described. | 02-05-2015 |

20130117623 | Method, Apparatus And Computer Program Product Providing Soft Interative Recursive Least Squares (RLS) Channel Estimator - Disclosed is an apparatus having a detector for an iterative LDPC-coded MIMO-OFDM system, where the detector is configured to use a structured irregular LDPC code in conjunction with a belief propagation algorithm. Also disclosed is an apparatus having a detector for a structured irregular LDPC-coded MIMO-OFDM system, where the detector is configured to use an iterative Recursive Least Squares-based data detection and channel estimation technique. Corresponding methods and computer program products are also disclosed. | 05-09-2013 |

20100318874 | ELECTRONIC MEMORY DEVICE AND METHOD FOR ERROR CORRECTING THEREOF - An electronic memory device includes a controller and a memory unit. The controller includes a micro processor, a host interface, a memory unit interface connected to the memory unit, a data cache area for provisionally storing data, an ECC unit coupled to the memory unit for testing whether there is any error bit in the data or not, and an error correcting unit coupled to the memory unit. If an error bit in the data is found and can be dealt by the ECC unit, the error bit is then directly recovered by the ECC unit. However, if the error bit exceeds beyond the processing capability of the ECC unit, the error correcting unit is selected to primarily invert predetermined data bit till the number of the error can be successfully recovered by the ECC unit. | 12-16-2010 |

20110107174 | METHOD AND APPARATUS FOR INTERCHANGING MULTIPATH SIGNALS IN A SC-FDMA SYSTEM - The present invention provides a MIMO transmitter and a MIMO receiver, used in SC-FDMA system, which make interchanging for multiple paths of modulated symbol sequences in order to acquire diversity gain while ensure PAPR of single antenna. MIMO transmitter interchanges partial symbols of at least one error-correction codeword of at least one of the multipath modulated symbol sequences and partial symbols of at least one error-correction codeword of at least one of the other of the multipath modulated symbol sequences so as to obtain interchanged multipath modulated symbol sequences; MIMO receiver executes inverse-interchanging which is inverse to the interchanging in a MIMO transmitter for multipath interchanged signals received from multiple transmitting antennas. The present invention could reduce the BLER of the entire SC-FDMA system, and obtain diversity gain while ensure PAPR of single antenna. | 05-05-2011 |

20100100789 | METHOD AND SYSTEM FOR DATA TRANSMISSION IN A MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) SYSTEM - A method for data transmission in a multiple input multiple output (MIMO) system. The method for data transmission includes receiving multiple input data streams and performing low density parity check (LDPC) encoding of the input data streams utilising a parity check matrix. The parity check matrix comprises a plurality of sub-parity check matrices for encoding respective associated ones of the input data streams and performing space time encoding for transmitting the LDPC encoded input data streams over a plurality of antennas. The performing of the LDPC encoding of the input data streams includes generating one or more connection matrices, each connection matrix for injecting information of one of the input data streams into the encoding of another one of the input data streams. Each connection matrix is a zero matrix if a lowest parity check protection level based on the sub-parity check matrix for the one of the input data streams is equal to or lower than an assigned parity check protection level for the one input data stream, and a non zero matrix otherwise. | 04-22-2010 |

20100042895 | SELECTING LAYERED-DECODING SCHEDULES FOR OFFLINE TESTING - A method for selecting a population of schedules of an n-layer decoder for offline schedule testing. The method identifies one or more triads, where a triad is a sequence of three layers where no layer is repeated. The method selects a set of schedules where each of the identified triads is contained in at least one schedule. The method associates each selected schedule with one or more key-layer values, where a key layer is the middle layer of a triad contained within the schedule. | 02-18-2010 |

20100042894 | ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING LMAXB-BASED SELECTION OF ALTERNATIVE LAYERED-DECODING SCHEDULES - A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer L | 02-18-2010 |

20100042893 | RECONFIGURABLE CYCLIC SHIFTER - In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message. | 02-18-2010 |

20100042892 | RECONFIGURABLE TWO'S-COMPLEMENT AND SIGN-MAGNITUDE CONVERTER - In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above. The reconfigurable SMT2 is selectively configurable to operate in (i) a five-bit mode to convert two five-bit messages concurrently and (ii) a ten-bit mode to convert one ten-bit message at a time. | 02-18-2010 |

20100042891 | ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 02-18-2010 |

20100042890 | ERROR-FLOOR MITIGATION OF LDPC CODES USING TARGETED BIT ADJUSTMENTS - Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials. | 02-18-2010 |

20100042889 | MEMORY SYSTEM AND METHOD USING A MEMORY DEVICE DIE STACKED WITH A LOGIC DIE USING DATA ENCODING, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits. | 02-18-2010 |

20090158115 | Apparatus and method for decoding signal in a communication system - A method and apparatus for decoding a signal in a communication system. The method and apparatus includes receiving a punctured codeword including information bit nodes and unpunctured parity bit nodes; analyzing the unpunctured parity bit nodes, and detecting at least one first block including the unpunctured parity bit nodes among a plurality of blocks each including parity bit nodes having the same importance among all parity bit nodes; and recovering said all parity bit nodes by serial-decoding parity bit nodes included in the first block according to decoding priorities of parity bit nodes, determined by reflecting the first block in a predetermined decoding priority determining algorithm. | 06-18-2009 |

20090158114 | ERROR-CORRECTING MULTI-STAGE CODE GENERATOR AND DECODER FOR COMMUNICATION SYSTEMS HAVING SINGLE TRANSMITTERS OR MULTIPLE TRANSMITTERS - A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols (subject to the resolution of the key used) can be generated, if needed. The output symbols are information additive such that a received output symbol is likely to provide additional information for decoding even when many symbols are already received. The output symbols are such that a collection of received output symbols can provide probabilistic information to support error correction. A decoder calculates check symbols from the output symbols received, wherein each check symbol is associated with one or more input symbols and redundant symbols For each received output symbol, the decoder updates a running total of estimated information content and, in one or more rounds, generates a probability distribution for each input symbol over all or some of the possible values of input symbols. This process may be repeated until, for all of the input symbols, one of the many possible values is much more probable than others, or the process may be repeated a predetermined number of rounds, or other criteria is met. The updating can take into account already decoded symbols, additional output symbols and the check symbols. | 06-18-2009 |

20090158113 | APPARATUS AND METHOD FOR ENCODING LDPC CODE USING MESSAGE PASSING ALGORITHM - Provided is an apparatus and method for encoding a Low Density Parity Check (LDPC) code using a message passing algorithm. The apparatus, includes: a parity calculating unit for operating a check node value on an input bit and a predetermined parity bit according to the message passing algorithm and calculating a parity bit; a parity correcting unit for correcting the calculated parity bit according to a parity check result of the calculated parity bit; and an output transform unit for combining the input bit and the corrected parity bit. | 06-18-2009 |

20100107033 | RADIO COMMUNICATION DEVICE AND PUNCTURING METHOD - Provided is a radio communication device which can minimize degradation of the error ratio characteristic attributed to puncturing when an LDPC code is used as an error correction code. In this device, an LDPC encoding unit ( | 04-29-2010 |

20100107031 | MULTIPLE-INPUT-MULTIPLE-OUTPUT TRANSMISSION USING NON-BINARY LDPC CODING - A wireless communication system constructed by a MIMO antenna system and transmitting information from a transmitter having Nt number of transmitting antennas to a receiver | 04-29-2010 |

20100107030 | LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS - In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices. | 04-29-2010 |

20130055043 | Two Low Complexity Decoding Algorithms for LDPC Codes - In the present invention, two improved variants of the reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes are presented. The new algorithms are obtained by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. In contrast to the first algorithm, the second algorithm includes check reliability that changes at each iteration. For the tested random and structured LDPC codes, both algorithms, while requiring very little additional computational complexities, achieve a considerable error performance gain over the standard one. More importantly, for short and medium block length LDPC codes of relatively large column weight, both algorithms outperform or perform just as well as the iterative decoding based on belief propagation (IDBP) with less decoding complexity. | 02-28-2013 |

20090158112 | METHOD FOR PRODUCING PARITY CHECK MATRIX FOR LOW COMPLEXITY AND HIGH SPEED DECODING, AND APPARATUS AND METHOD FOR CODING LOW DENSITY PARITY CHECK CODE USING THE SAME - Provided are a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same. The method includes: calculating a cyclic shift value of a subblock to a matrix; and when the calculated cyclic shift values of the subblock are arrayed in the matrix, producing a parity check matrix by arraying the cyclic shift values of the subblock except ‘0 matrix’ without duplication to any one column. | 06-18-2009 |

20090125781 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN A COMMUNICATION SYSTEM USING LOW DENSITY PARITY CHECK CODE - A method for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix includes generating an LDPC codeword by encoding information data bits, interleaving the LDPC codeword, mapping the interleaved LDPC codeword to a modulation signal, and generating a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part of said modulation signal, among bits constituting the modulation signal, generating a modulation signal by high-order-modulating the mapped signal and Radio Frequency (RF)-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna. | 05-14-2009 |

20090292967 | CHANNEL SWITCHING SIGNAL GENERATING CIRCUIT AND CHANNEL SWITCHING SIGNAL GENERATING METHOD - An error correction decoder ( | 11-26-2009 |

20090292966 | Method for recovery of lost and/or corrupted data - A method for recovery of lost and/or corrupted data transmitted from a transmitter device to a receiver device. The data is coded by an encoder connected to the transmitter device. The data is transmitted from the transmitter device to the receiver device via a transmission system and is decoded by means of a decoder connected to the receiver device. This is performed through application of a low density parity check method, wherein lost and/or corrupted data is restored during decoding. The decoding is performed by solving the equation system of the parity check matrix H. The parity check matrix H is brought into a triangular form by column and/or row permutations. Columns of a sub-matrix B of the matrix H which impede the triangulation process are shifted into a sub-matrix P of the matrix H so that the triangulation process can be continued until the matrix H except for the sub-matrix P has been completely brought into a triangular form. The Gaussian elimination method is applied to a part of the sub-matrix P. The selection of the column or columns of the sub-matrix B which are to be shifted into the sub-matrix P is performed on the basis of the weight of the column which corresponds to the number of non-zero-entries in the column, and/or on the basis of the weight of the rows of the sub-matrix B connected to the column. | 11-26-2009 |

20140068367 | LDPC Decoder Trapping Set Identification - The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder. | 03-06-2014 |

20120005552 | ON-LINE DISCOVERY AND FILTERING OF TRAPPING SETS - A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system. | 01-05-2012 |

20120011415 | METHOD AND APPARATUS FOR IMPROVED MULTICAST STREAMING IN WIRELESS NETWORKS - The invention includes a method and apparatus for providing media content. The method includes duplicating each packet of an original packet stream for which an associated importance level satisfies an importance condition, inserting each duplicate packet within the original packet stream to form thereby a modified packet stream, and transmitting the modified packet stream toward a wireless terminal adapted for processing the modified packet stream for presenting the media content conveyed by the original packet stream. The duplicate packets may be inserted within respective windows associated with the duplicate packets, wherein each window is determined according to an original packet position associated with the original packet from which the duplicate packet is formed. | 01-12-2012 |

20090307561 | Decoding device, decoding method, and recording and reproducing device - A decoding device includes a decoding unit that decodes an information data string including an error-correction parity for each interleaved data string obtained by interleaving the information data string for each symbol to generate a decoded data string; an error-correcting decoding unit that interleaves the decoded data string to perform error-correcting decoding, de-interleaves the interleaved decoded data strings after error-correcting decoding when all errors in the decoded data strings are corrected, and generates a decoded data string after error correction when errors are remained; and an event error-correcting unit that corrects data in the decoded data string for the merge section when an error-corrected portion in the decoded data string obtained by comparing the decoded data string and the decoded data string after error correction is in an event information string indicative of a merge section in the decoded data string. | 12-10-2009 |

20110131464 | APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL - In one aspect of the present invention, the method receiving a signal is disclosed. The method includes receiving a signal transmitted in a radio frequency (RF) band including at least one RF channel, demodulating the received signal, parsing a preamble of a signal frame including layer-1 information, from the demodulated signal, deinterleaving bits of the layer-1 information, decoding the deinterleaved bits using an error correction decoding scheme including a shortening scheme and a puncturing scheme and obtaining physical layer pipes (PLPs) from the signal frame using the error-correction-decoded layer-1 information. | 06-02-2011 |

20110131463 | FORWARD SUBSTITUTION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector. | 06-02-2011 |

20130232389 | POWER CONSUMPTION IN LDPC DECODER FOR LOW-POWER APPLICATIONS - This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders. | 09-05-2013 |

20130332790 | LDPC Decision Driven Equalizer Adaptation - The present inventions are related to LDPC decision-driven equalizer adaptation. For example, a data processing apparatus is disclosed that includes an equalizer operable to yield equalized data, a low density parity check decoder operable to decode the equalized data to yield decoded data, and an equalizer adaptation circuit operable to adapt settings in the equalizer based in part on the decoded data. | 12-12-2013 |

20130332789 | INTEGRITY OF A DATA BUS - A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data. | 12-12-2013 |

20090282313 | METHOD AND APPARATUS FOR HARD DECISION BOUNDED DISTANCE DECODING OF NORDSTROM ROBINSON CODE - A receiver is provided that comprises a decoder. The decoder comprises: means for slicing a signal; means for encoding data/messages to a code word among a predetermined number of code words; and means for determining a distance associated with the code word. | 11-12-2009 |

20100332940 | CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM - A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected. | 12-30-2010 |

20100332939 | DECODING APPARATUS, DECODING METHOD, AND PROGRAM - A decoding apparatus includes maximum decoding iteration count controller | 12-30-2010 |

20090276681 | Upgraded Codeword Lock State Machine - An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword. | 11-05-2009 |

20090271683 | System and Method of Processing Video Data - The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a stream of data packets at a re-generator of an Internet Protocol (IP) video transport stream. The stream of data packets includes a plurality of IP media packets and a plurality of forward error correction (FEC) packets. The method also includes determining an error profile of an error within the plurality of IP media packets. The method includes identifying one of the plurality of FEC packets, where the identified FEC packet is associated with an error correction code corresponding to the error profile. The method also includes selecting an inverse FEC function from a plurality of inverse FEC functions. The selected inverse FEC function corresponds to the identified FEC packet. | 10-29-2009 |

20090271682 | RECEIVING/TRANSMITTING SYSTEM AND DATA PROCESSING METHOD IN THE RECEIVING/TRANSMITTING SYSTEM - A receiving system and a data processing method are disclosed. The receiving system includes a receiving unit, a controller, a demodulator, an equalizer, a turbo decoder, and an error correction unit. The receiving unit receives a broadcast signal including data packets, wherein an M/H service data packet includes known data and signaling data is periodically inserted for each of K number of data packets. The controller detects known data and decodes the signaling data from the received broadcast signal. The demodulator demodulates the received broadcast signal, based upon the known data. The equalizer channel-equalizes the demodulated broadcast signal, based upon the known data. The turbo decoder performs regressive turbo decoding on mobile service data, among the channel-equalized data, by applying at least one of an SCCC mode and a PCCC mode, based upon the signaling data. The error correction unit performs error correction on the mobile service data being turbo-decoded and outputted, based upon the signaling data. | 10-29-2009 |

20090063930 | CHECK MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION DEVICE, ENCODER, AND DECODER - A regular quasi-cyclic matrix is generated with cyclic permutation matrices and specific regularity given to the cyclic permutation matrices. A mask matrix for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. An irregular masked quasi-cyclic matrix is generated by converting a specific cyclic permutation matrix in the regular quasi-cyclic matrix into a zero-matrix using a mask matrix supporting a specific encoding rate. An irregular parity check matrix with an LDGM structure is generated with a masked quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner. | 03-05-2009 |

20100269010 | Encoding Method, Encoding Device, Decoding Method and Decoding Device for Low Density Generator Matrix Codes - An encoding method, encoding device, decoding method and decoding device for low density generator matrix codes (LDGC) are disclosed. Wherein, the encoding method comprises: construct an LDGC mother code set using P LDGC with code rate R | 10-21-2010 |

20110010602 | METHOD AND APPARATUS FOR PERFORMING DECODING USING LDPC CODE - A method of performing decoding using an LDPC code is disclosed. The method of performing decoding an encoded codeword using a parity check matrix, comprises decoding the codeword using the parity check matrix, wherein the parity check matrix includes a plurality of layers, each of which includes at least one or more rows split exclusively from a specific row of a base parity check matrix. | 01-13-2011 |

20110010601 | DATA REPRODUCING APPARATUS AND DATA REPRODUCING METHOD - According to one embodiment, a data reproducing apparatus comprises a reader, Viterbi decoder, metric difference calculator, an error correction decoder, and a detector. The reader is configured to read data. The Viterbi decoder is configured to decode the data read by the reader. The metric difference calculator is configured to calculate a metric difference between a maximum likelihood path and a competitive path, based on an output from the Viterbi decoder. The error correction decoder is configured to execute an error correction decoding for the output of the Viterbi decoder. The detector is configured to detect that an error detected by the error correction decoder is uncorrectable, and the metric difference detected by the metric difference calculator is larger than a predetermined value. | 01-13-2011 |

20110010600 | LDPC Hard Decision Decoder for High-Speed Wireless Data Communications - A method for low-density parity-check hard decision decoding includes computing, for every decoding iteration, a discrepancy of extrinsic messages responsive to channel inputs of a receiver, performing a flipping of the channel inputs responsive to a comparison of the discrepancy of extrinsic messages to a flipping threshold, the flipping threshold for each decoding iteration being determined based on a threshold computation responsive to a channel error probability estimation in a first iteration of a decoding of the channel inputs, and check node decoding responsive to the flipping of channel inputs | 01-13-2011 |

20110010599 | N-WAY PARITY TECHNIQUE FOR ENABLING RECOVERY FROM UP TO N STORAGE DEVICE FAILURES - An n-way parity protection technique enables recovery of up to n storage device (e.g., disk) failures in a parity group of a storage array encoded to protect against n-way disk failures. The storage array is created by first configuring the array with m data disks, where m=p−1 and p is a prime number and a row parity disk. n−1 diagonal parity disks are then added to the array. Each diagonal parity set (i.e., diagonal) is associated with a slope that defines the data and row parity blocks of the array that are included in the diagonal. All diagonals having a common slope within a parity group are organized as a diagonal parity class. For each diagonal parity class, a diagonal parity storage disk is provided to store the diagonal parity. | 01-13-2011 |

20090031187 | DATA RECORDING/REPRODUCING APPARATUS AND DATA RECORDING/REPRODUCING METHOD - A data format, a data recording/reproducing method, and a data recording/reproducing apparatus are provided for effectively correcting data errors caused by dust and scratches on a recording medium even with the use of a conventional ECC. The data recording/reproducing apparatus includes a generation unit that generates predetermined data units by dividing an ECC sector including error correction codes generated by an error correction encoder into prescribed data units and encoding the prescribed units into iterative encoded data units using an iterative encoder so that the predetermined data units may consist of the iterative-encoded data units, a recording unit, a reproducing unit, an iterative decoder for conducting iterative decoding on the predetermined data units, and an error correction decoder. The apparatus further includes a distribution unit for distributing the predetermined data units generated by the generation unit. The distribution unit distributes the iterative encoded data units using at least two ECC sectors and records the distributed data units on a recording medium. | 01-29-2009 |

20120192030 | Parity Error Correction for Band-Limited Digital Signals - An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each test sample being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples. | 07-26-2012 |

20120192029 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 07-26-2012 |

20090094499 | REPRODUCTION APPARATUS AND REPRODUCTION METHOD - Disclosed is a reproduction apparatus that reproduces signals of a plurality of channels including: a soft-decision portion that performs a soft decision on each bit of a block encoded with an LDPC code for each channel, as a bit string corresponding to a length of the LDPC code; a holding portion that holds a soft-decision result on the block basis for each channel; a decoding portion that inputs the soft-decision result on the block basis and obtains an estimated bit string by an iterative decoding; and a control portion that determines a priority order among channels for each of which a next block is subjected to the iterative decoding, based on an iteration count at an end of the iterative decoding for each channel, and controls the input of the soft-decision result so that the iterative decoding is performed for each channel in accordance with the priority order. | 04-09-2009 |

20100058143 | Efficient Decoding - Embodiments of a method and apparatus for decoding signals are disclosed. An embodiment of a decoder includes means for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles. | 03-04-2010 |

20090013235 | Conditional decoding receiver - This invention relates to a wireless telecommunication system receiver, comprising a demodulator ( | 01-08-2009 |

20090013234 | DATA STORAGE WITH AN OUTER BLOCK CODE AND A STREAM-BASED INNER CODE - Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application. | 01-08-2009 |

20090013233 | ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes. | 01-08-2009 |

20100235709 | SYSTEMS AND METHODS FOR PROVIDING UNEQUAL ERROR PROTECTION CODE DESIGN FROM PROBABILISTICALLY FIXED COMPOSITION CODES - A method of encoding that uses standard codecs such as linear encoders and decoders for encoding and decoding data with different levels of robustness to errors is described. In one configuration, multiple encoders may be utilized, and one of the encoders may use a standard encoder such as a turbo code followed by a nonlinearity that creates an unequal distribution of ones and zeros in a binary representation of the code. In another configuration, a coder may be utilized that represents message outputs as “channels” that create state transitions (or symbol errors) in a data forward error correction coder. | 09-16-2010 |

20100235706 | INTERLEAVER APPARATUS AND RECEIVER FOR A SIGNAL GENERATED BY THE INTERLEAVER APPARATUS - A convolution interleaver for processing a codeword derived from an input block of symbols using a redundancy-adding coding, and having more symbols than the input block, wherein the codeword has a sequence of interleaving units, wherein each interleaving unit has at least two symbols, includes an interleaver. The interleaver changes the sequence of interleaving units to obtain an interleaved codeword having a changed sequence of interleaving units. In particular, the order of the symbols within an interleaving unit is not changed by the interleaver. The order of the interleaving units in the codeword among each other or with respect to a previous or subsequent codeword is changed, however. | 09-16-2010 |

20090006921 | Distributed checksum computation - Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data. | 01-01-2009 |

20130166984 | Efficient Implementation to Perform Iterative Decoding with Large Iteration Counts - Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, and is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims. | 06-27-2013 |

20130326303 | PROVIDING CAPACITY OPTIMIZED STREAMING DATA WITH FORWARD ERROR CORRECTION - In an example embodiment, there is described herein a methodology were the Forward Error Correction (FEC) data for a data stream is distributed into a plurality of FEC sub-streams. Subscribers to the data stream indicate which of the plurality of FEC sub-streams should be provided to them. The distribution of FEC sub-streams are limited to subscribed FEC sub-streams. FEC sub-streams with no subscribers are not forwarded beyond a distribution point such as an access point (AP). | 12-05-2013 |

20100251066 | DATA HANDLING - Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors in data in accordance with the determined or selected depth of error detection and/or error correction coverage. | 09-30-2010 |

20100251065 | LOW DENSITY PARITY CHECK (LDPC) CODE - Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown. | 09-30-2010 |

20100251064 | LDPC codes robust to non-stationary narrowband ingress noise - LDPC codes robust to non-stationary narrowband ingress noise. Particularly designed LDPC codes are adapted to address deleterious noise-effects incurred within LDPC coded signals that propagate via a communication channel (such as from a transmitting communication device to a receiving communication device). Such LDPC matrices employed for encoding and/or decoding such LDPC coded signals are composed of sub-matrices (e.g., all-zero values sub-matrices and/or CSI (Cyclic Shifted Identity) sub-matrices). The sub-matrices are generally uniform in size and square in shape. Based on certain operational conditions, such as communication channel noise, various operations within a communication device are adaptively modified (e.g., signaling, modulation, demodulation, symbol mapping, metric generation, decoding, etc.). Various types of signaling may be employed for such LDPC coded signals including orthogonal frequency division multiplexing (OFDM) signaling, which may include employing symbols of different size therein (e.g., symbols with x and y bits, respectively, with x and y being integers). | 09-30-2010 |

20100251063 | DECODING DEVICE, DATA STORAGE DEVICE, DATA COMMUNICATION SYSTEM, AND DECODING METHOD - A data converting means generates first interim data held in one-to-one correspondence to columns vectors from data stored in a first storage means and data stored in a second storage means. A check node processing means generates second interim data for updating the data stored in the first storage means based on the sum of the first interim data and received data. The data converting means updates the data stored in the second storage means using the first interim data, and updates the data stored in the first storage means using the second interim data generated by the check node processing means. Decoded data are generated by a process carried out by the data converting means and the check node processing means. | 09-30-2010 |

20100251062 | ENCODING METHOD AND TRANSMISSION DEVICE - Provided is an encoding method including: a step of extending a bidiagonal line of a basic matrix of m rows and n columns in the direction of a bidiagonal line according to an encoding ratio 1/k of the spread code (wherein k=3, 4, 5, . . . , k0) set in the LDPC code inspection matrix so as to constitute an extended matrix of the bidiagonal line structure; a step of moving a first non-zero element of the parity bit portion in the (i*m+1)-th row to the (n−m+1)-th column (wherein i=1, 2, . . . , k0−2) leftward along the row; a step of calculating the parity bit of the (n−m+1)-th column by using a first inspection relationship as a start factor; and a step of simultaneously calculating parity bits of a plurality of groups by the recursive encoding method by using the inspection relationship moved leftward to the (n−m+1)-th column. | 09-30-2010 |

20100251061 | TRANSMISSION DEVICE - Provided is a transmission device which improves the error rate characteristic upon decoding when performing error correction encoding by using a self-orthogonal code or an LDPC-CC in a communication system using a communication path having a fading fluctuation, multi-value modulation, or MIMO transmission. In the transmission device, the self-orthogonal encoding unit ( | 09-30-2010 |

20100251060 | DECODING DEVICE, DECODING METHOD, AND MEDIA DATA DELIVERY SYSTEM - A decoding device includes a first receiving section for receiving a data packets, a second receiving section for receiving a plurality of error correction packets which includes matrix configuration information regarding the plural data packets, a deciding section for deciding a number of packets to be accumulated to restore a lost data packet, based on the matrix configuration information, an accumulating section for accumulating the data packets received by the first receiving section in the number of packets to be accumulated, and a restoring section for, when a loss of any of the data packets received by the first receiving section is detected, restoring the lost data packet by using at least one of the data packets and the error correction packets. | 09-30-2010 |

20100251059 | SHUFFLED LDPC DECODING - An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means ( | 09-30-2010 |

20090287981 | Construction of Parity-Check Matrices for Non-Binarys LDPC Codes - A parity check matrix construction method for constructing a non-binary parity check matrix defining a non-binary LDPC code. In particular, a parity check matrix construction method for setting codewords able to stably give a superior decoding performance is provided. For this reason, the non-binary non-zero elements are selected so that the determinants of the partial matrices corresponding to the cycles in the parity check matrix do not become 0. Due to this, a non-binary parity check matrix able to give large weight codewords is constructed. | 11-19-2009 |

20090287980 | Computational Architecture for Soft Decoding - A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation. | 11-19-2009 |

20090287979 | SYSTEM AND METHOD FOR RELAY CODING - Systems and methods for providing relay in communications systems are disclosed. The relay may receive signals from user equipments (UEs) transmitting coded signals. The relay may receive turbo coded signals from the UEs. The relay station may encode a network channel for transmission to the base station using a recursive systematic convolutional (“RSC”) code. The use of RSC for the network code enables the base station to form as well a distributed turbo code as one can with the UE coded signals. In this manner the base station may recover the signal estimates for the UE signals with lower error probability when estimates at the relay station include errors due to imperfect reception. The use of the relay station and the RSC network code enables the base station to receive UE signals with lower error probability even when the transmission path from the UE is imperfect. | 11-19-2009 |

20090287978 | Operating Parameter Control for Integrated Circuit Signal Paths - An integrated circuit ( | 11-19-2009 |

20110041031 | SEPARATE MEMORIES AND ADDRESS BUSSES TO STORE DATA AND SIGNATURE - A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated. | 02-17-2011 |

20100077276 | TRANSMITTING DEVICE, RECEIVING DEVICE, ENCODER, AND ENCODING METHOD - In such a relationship between information transmitted by a primary BCH, for example, and information transmitted by a non-primary BCH as a case of the transmission for a first information sequence that is easy to keep receiving quality and a second information sequence that is difficult to keep receiving quality, a transmitting device and a receiving device are disclosed for making it possible to improve an error rate of the second information sequence. In the devices, an encoder ( | 03-25-2010 |

20100077275 | METHOD AND SYSTEM FOR DATA TRANSMISSION IN A MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) SYSTEM - A method for data transmission in a multiple input multiple output (MIMO) system, the method including, receiving multiple input data streams; performing low density parity check (LDPC) encoding of the input data streams utilising a parity check matrix, the parity check matrix including a plurality of sub-parity check matrices for encoding respective ones of the input data streams; and performing space time encoding for transmitting the LDPC encoded input data streams over a plurality of antennas. | 03-25-2010 |

20120017133 | MANAGEMENT OF DECODING EFFORT IN AN ITERATIVE DECODING SCENARIO - Schemes for creating a surplus of decoding iterations in a decoder are described. The surplus can be used to augment the decoding of signal blocks. The option of using an idle decoder to decode blocks marked as unproductive for decoding is also described. | 01-19-2012 |

20120017132 | LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing. | 01-19-2012 |

20110161772 | WIRELESS COMMUNICATION DEVICE AND WIRELESS COMMUNICATION METHOD - Disclosed is a wireless communication device capable of always obtaining the optimum error rate characteristic and of keeping the number of retransmissions to a minimum for IR-based HARQ which uses LDPC encoding in the error correction encoding. With the device, an RV control unit ( | 06-30-2011 |

20120173950 | Systems and Methods for Efficient Data Storage - Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data. | 07-05-2012 |

20130007554 | Dynamically Scaled LLR For An LDPC Decoder - A method for decoding an LDPC (low-density parity check) code word. The method includes receiving a plurality of LLR (log likelihood ratio) terms from a demodulation unit of a receiver and generating a scaling factor in accordance with at least one parameter descriptive of communication channel conditions for the receiver. The scaling factor is applied to each of the plurality of LLR terms to compute a corresponding plurality of scaled LLR terms. An iterative layered belief propagation algorithm is then executed by using the plurality of scaled LLR terms to generate decoded information. | 01-03-2013 |

20120192031 | VIDEO DATA TRANSMISSION PROCESSING METHOD, VIDEO DATA SENDING PROCESSING METHOD, APPARATUS, NETWORK SYSTEM - Embodiments of the present invention provide a video data transmission processing method, a video data sending processing method, an apparatus, and a network system. The data transmission processing method includes: receiving a source stream sent from a source transmission network to a target transmission network; performing, according to respective packet loss rates of the source transmission network and the target transmission network as well as error tolerance aid information corresponding to the source stream, error tolerance coding processing on the source stream to obtain an error tolerance stream; and sending the obtained error tolerance stream to the target transmission network. | 07-26-2012 |

20110283158 | APPARATUS AND METHOD FOR LAYERED DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES - A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders. | 11-17-2011 |

20110283161 | Multi-code LDPC (Low Density Parity Check) decoder - Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals. | 11-17-2011 |

20110283159 | METHOD FOR ENCODING OR DECODING LDPC CODE WITH VARIABLE LENGTH, DEVICE, ENCODER, AND DECODER - A method for encoding or decoding an LDPC code with variable code lengths is provided in an embodiment of the present invention. The method includes: obtaining a base exponential matrix of an LDPC code and grouping code lengths during construction of the base exponential matrix; correcting the base exponential matrix according to a grouping correction factor to obtain an exponential matrix of the group corresponding to the grouping correction factor; extending the exponential matrix by using an extension factor of a code length in the group to obtain an LDPC matrix corresponding to the code length; and implementing encoding or decoding by using the LDPC matrix. | 11-17-2011 |

20120089888 | Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes - Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains. | 04-12-2012 |

20120089886 | RELAYING DATA TRANSMITTED AS ENCODED DATA SLICES - A method begins by a first device determining an error coding distributed routing protocol and transmitting a set of encoded data slices, identity of a second device, and the error coding distributed routing protocol to a network, wherein the set of encoded data slices represents data that has been dispersed storage error encoded. The method continues with the network routing a plurality of sub-sets of the set of encoded data slices via an initial plurality of routing paths towards the second, comparing anticipated routing performance with a desired routing performance, and altering the routing path to obtain a favorable comparison. The method continues with the second device receiving at least some of the set of encoded data slices from the network and decoding at least a threshold number of encoded data slices to reproduce the data when at least the threshold number of encoded data slices have been received. | 04-12-2012 |

20120089885 | DATA TRANSMISSION UTILIZING ROUTE SELECTION AND DISPERSED STORAGE ERROR ENCODING - A method begins by a processing module obtaining a set of encoded data slices for transmission to a receiving entity via a network, wherein the set of encoded data slices represents data that has been dispersed storage error encoded. The method continues with the processing module dividing the set into a plurality of sub-sets of encoded data slices in accordance with an error coding distributed routing protocol. The method continues with the processing module determining a plurality of routing paths within the network in accordance with the error coding distributed routing protocol. The method continues with the processing module transmitting the plurality of sub-sets of encoded data slices via the plurality of routing paths to the receiving entity in accordance with the error coding distributed routing protocol. | 04-12-2012 |

20100050046 | IDENTIFICATION OF POTENTIALLY ERRONEOUS AND/OR ERASED DATA - Systems for identifying potentially erroneous and/or erased data are provided. Systems have a bit detector, an accumulator, and a data reconstruction processor. The bit detector assigns values to bits read in a data signal. The bit detector illustratively assigns multiple values to each of the bits. The accumulator accumulates a count of the multiple values assigned by the bit detector for each of the bits. The accumulator associates each bit with a particular value based at least in part on its accumulated count. The data reconstruction processor determines for each of the bits a confidence level of the particular value associated to it. The data reconstruction process sets flags for a portion of the bits. The flags identify the portion of the bits as possible erased or erroneous data. The flags are set based at least in part on the confidence levels of the portion of the bits. | 02-25-2010 |

20100050043 | METHOD AND DEVICE FOR DECODING LDPC CODES AND COMMUNICATION APPARATUS INCLUDING SUCH DEVICE - A device and method for the iterative decoding of a received word represented by signal values according to a parity control matrix code of the type for passing messages between variable nodes and control nodes of a two-part graph related to the matrix. The method includes at least the following steps: setting up at least one message of a variable node, according to the values, by an information representative of the ratio between the probability of having the most likely symbol at a position corresponding to the variable node and the probability of having the current symbol at the position; determining at least one message, relating to a determined symbol, of a control node to a determined variable node, as the selected minimal value, among the symbol sequences corresponding to the control node equation using the determined symbol at the determined variable node, by the maximal value of the messages received at the control node from variable nodes different from the determined variable node and each relating to the symbol associated with the different variable node in the sequence corresponding to the equation; and determining the messages of a variable node to a control node that relate to the whole set of symbols so that the minimal value of said messages is equal to zero. | 02-25-2010 |

20100050042 | DELIVERY METHOD FOR INTERNET PROTOCOL TELEVISION (IPTV) - A delivery method for IPTV which combines forward error correction (FEC) with retransmission techniques for handling packet loss and/or corruption. Packet loss or corruption of popular channels is handled through the use of FEC while packet loss of less popular channels is handled by retransmission. | 02-25-2010 |

20150046765 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |

20110296271 | METHOD OF COMMUNICATION - A method of communication comprising determining whether to use distributing coding between a source (S), relay (R) and destination (D), based on a predetermined transmission rate; if the determination is positive, determining a forward error correction scheme using distributed Alamouti space-time coding, wherein the scheme is determined based on the predetermined transmission rate, a channel signal-to-noise ratio (SNR) and a network topology; relaying coded data from the S to the D using the determined forward error correction. | 12-01-2011 |

20110296270 | Apparatus and method for resource segmentation in wireless communication system - An apparatus and a method segment an allocated resource in data transmission in a wireless communication system. When a size of transmission data is large, the data information bit is distributed to one or more forward error correction (FEC) blocks with consideration of a size of the data information bit. A number of data tones is determined based on control information with respect to each of the one or more FEC blocks. The data information bit distributed to the one or more FEC blocks is mapped into a data tone with consideration of the number of data tones determined for each of the one or more FEC blocks. | 12-01-2011 |

20090276680 | ERROR CORRECTION CIRCUIT AND METHOD THEREOF - An error correction method is applicable for accessing a data in a storage medium. The method includes the steps of: encoding a portion of the data and the whole data to produce a partial data parity for that portion of the data and a whole data parity for the whole data; using the partial data parity to decode the corresponding portion of the data and the corresponding partial data parity in order to correct error bits from the corresponding portion of the data and from the partial data parity according to the decoded result; using the whole data parity to decode the whole data and the whole data parity in order to correct the error bit from the whole data and the whole data parity according to the decoded result; and outputting the corrected data. | 11-05-2009 |

20120131408 | COMPUTER READABLE STORAGE MEDIUM STORING ERROR CORRECTION PROGRAM AND COMMUNICATION APPARATUS - A computer-readable medium storing a program causing a computer to execute a process includes, acquiring a plurality of data units that belong to a first block in a certain hierarchy among hierarchical blocks defined by a plurality of hierarchies; generating error correction information corresponding to the first block that equals to an exclusive-OR of the plurality of data units; generating, in each individual hierarchy of one or more individual hierarchies that are continuous from and are lower than the certain hierarchy, error correction information corresponding to each individual block that equals to the exclusive-OR of all data units that belong to the individual block among the plurality of data units, where the individual block is one or more individual blocks other than one specific block in two or more blocks in the individual hierarchy that are included in the same block in a hierarchy. | 05-24-2012 |

20100037117 | DATA ERROR CORRECTION DEVICE AND METHODS THEREOF - A method of accessing a memory includes accessing multiple ECC words via a single memory channel. Portions of each ECC word are retrieved from different memory ranks, so that a failure in a memory device at one memory rank is less likely to result in uncorrectable errors in the data segment. By accessing the data segments via a single memory channel, rather than multiple memory channels, the single memory channel can be accessed independently, providing for lower cost memory modules, higher memory bandwidth, and lower power dissipation. | 02-11-2010 |

20100011274 | HYPOTHETICAL FEC DECODER AND SIGNALLING FOR DECODING CONTROL - A communication system wherein a transmitter transmits a media stream to a receiver encoded using FEC, comprising at least one hypothetical FEC decoder at the transmitter for decoding the media stream encoded at the transmitter. The transmitter determines what optimization signals to provide the receiver given the outputs of the at least one hypothetical FEC decoder and signals to the receiver those optimization signals. The optimization signals might include slowdown of media consumption signals, indications of variable buffering parameters and/or indications of FEC and source data ordering. | 01-14-2010 |

20090259913 | METHOD FOR ENCODING CONTROL INFORMATION IN A WIRELESS COMMUNICATION SYSTEM USING LOW DENSITY PARITY CHECK CODE, AND METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING THE CONTROL INFORMATION - A method and apparatus for transmitting control information in a wireless communication system using a Low Density Parity Check (LDPC) code is provided. The number of LDPC blocks, through which L1 post-signaling information is to be transmitted, is determined according to the total number of bits of the L1 post-signaling information. The number of input information bits of each LDPC block is calculated when the determined number of LDPC blocks is plural. The number of puncturing bits among parity bits of each LDPC block is determined considering a modulation order. A frame including one or multiple LDPC blocks generated through the preceding steps is transmitted. | 10-15-2009 |

20100169738 | Channel interleaver having a constellation-based block-wise permuation module - A channel interleaver comprises a novel constellation-based permutation module. The channel interleaver first receives a plurality of sets of encoded bits generated from an FEC encoder. The encoded bits are distributed into multiple subblocks and each subblock comprises a plurality of adjacent bits. A subblock interleaver interleaves each subblock and outputs a plurality of interleaved bits. The constellation-based permutation module rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are supplied to a symbol mapper such that a plurality of consecutively encoded bits in the same set of the encoded bits generated from the FEC encoder is prevented to be mapped onto the same level of bit reliability of a modulation symbol. In addition, the plurality of adjacent bits of each subblock is also prevented to be mapped onto the same level of bit reliability to achieve constellation diversity and to improve decoding performance. | 07-01-2010 |

20100169735 | LOW DENSITY PARITY CHECK CODE ROW UPDATE INSTRUCTION - Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value. | 07-01-2010 |

20100023837 | TRANSMITTING APPARATUS, TRANSMITTING METHOD, AND PROGRAM - A change amount detector calculates the amount of change between frames in a predetermined display range in an image corresponding to image data. When the calculated amount of change is larger than a first threshold, a redundancy determining portion determines the number of data of redundant data such that the number of data of the redundant data for image data in the predetermined display range is increased. A communication controller transmits data containing image data based on the determined number of data of the redundant data. | 01-28-2010 |

20120179951 | Digital Watermark Key Generation - This disclosure relates to message encoding. Once claim recites an apparatus comprising: electronic memory for buffering identifying data associated with an entity or client; and a multi-purpose electronic processor programmed for: modifying the identifying data with a random or pseudo-random signal; error correction encoding the modified identifying data; and transforming a plural-bit message with the error correction encoded, modified identifying data to produce a key for use with message encoding. Of course, other claims and combinations are provided as well. | 07-12-2012 |

20120179950 | Method and System for Detecting the Frame Boundary of a Data Stream Received in Forward Error Correction Layer in the Ethernet - The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware. | 07-12-2012 |

20120179949 | METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING - In one embodiment, a coding method that uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. | 07-12-2012 |

20140053037 | Multi-Level LDPC Layered Decoder With Out-Of-Order Processing - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding with out-of-order processing. | 02-20-2014 |

20100100788 | Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel - The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*G | 04-22-2010 |

20100100791 | System and method for low complexity raptor codes for multimedia broadcast/multicast service - A system and method for encoding symbols in a wireless communication is provided. The system and method includes a transmitter configured to encode data transmissions. The transmitter includes a raptor encoder configured to perform a coding operation. The raptor encoder generates intermediate symbols without using a half-code such that the intermediate symbols consist of precoded symbols and parity symbols. Thereafter, the intermediate symbols are encoded using a Luby Transform to produce and output encoded symbols. The transmitter further is configured to transmit one or more of the source symbols, parity symbols or encoded symbols. | 04-22-2010 |

20100269011 | APPARATUS AND METHOD FOR DECODING LOW DENSITY PARITY CHECK CODE USING PROTOTYPE MATRIX - Provided is an apparatus and method for decoding a low density parity check (LDPC) code using a prototype matrix. The apparatus includes: a bit input unit for receiving a log likelihood ratio (LLR) value for an input bit; a check matrix processing unit for sequentially processing a parity check matrix for the received LLR value using a prototype parity check matrix through partial-parallel processing; and a bit processing unit for restoring the input bit by determining a bit level from the partial-parallel processed parity check matrix value. | 10-21-2010 |

20090150744 | APPARATUS, SYSTEM, AND METHOD FOR ENSURING DATA VALIDITY IN A DATA STORAGE PROCESS - An apparatus, system, and method are disclosed for ensuring data validity in a data storage process. A data receiver module receives a storage block and existing parity information. An ECC generation module generates error correcting code (“ECC”) check bits for the data of the storage block in response to receiving the storage block and the existing parity information. The ECC check bits for the storage block are generated using a block code, a convolutional code, etc. A pre-storage consistency module uses the data of the storage block, the existing parity information, and the ECC check bits to determine if the data of the storage block, the existing parity information, and the ECC check bits are consistent. A data storage module stores the data of the storage block and the ECC check bits the data storage device without storing the existing parity information. | 06-11-2009 |

20100269008 | DISPERSED DATA STORAGE SYSTEM DATA DECODING AND DECRYPTION - A computing system retrieves securely stored encrypted and encoded data from a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an error decoder and a decryptor and to decode and decrypt the encrypted and encoded data retrieved from the dispersed data storage system utilizing a read command to the storage units. The storage units retrieve the encrypted and encoded data and send the encrypted and encoded data to the processing module when receiving the read command. | 10-21-2010 |

20100037119 | APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW-DENSITY PARITY CHECK CODES - An apparatus and method for updating a check node of a low-density parity check (LDPC) code in order to decode the LDPC code are provided. The method includes the operations of: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values. Accordingly, the complexity of hardware is reduced, and super high-speed processing is possible. | 02-11-2010 |

20100122143 | METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) CODING FOR SCRAMBLED CODED MULTIPLE ACCESS (SCMA) - A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals. | 05-13-2010 |

20120110407 | DECODING DEVICE AND METHOD, AND PROGRAM - Disclosed herein is a decoding device including: an extracting section, a storing section, an allocating section, and a decoding section. The extracting section acquires data containing plural code words and information other than the plural code words in one frame, and extracts the plural code words from the data every one code word. The storing section at least stores the one code word extracted by the extracting section. The allocating section sets time obtained by dividing time for the one frame by the number of code words contained in the one frame as time allocated to decoding of one code word. The decoding section decodes the code word within the time allocated by the allocating section. | 05-03-2012 |

20100218067 | DIGITAL TRANSMITTING AND/OR RECEIVING APPARATUS AND METHOD THEREOF - A digital transmitting and/or receiving apparatus is provided, in which a digital transmitting apparatus may include a first coder which codes a first layer data to add a first parity, a multiplexer which adds a second layer data to the first layer data to which the first parity is added, a second coder which does a data outputted from the multiplexer to add a second parity, and a modulator which modulates the data to which the second parity is added and outputs the resultant data. Accordingly, a receiving apparatus with a simpler structure can be provided. | 08-26-2010 |

20100218066 | ENCODING DEVICE AND DECODING DEVICE - Disclosed are an encoding device and a decoding device which can effectively reduce the decoding failure frequency in LDPC encoding/decoding. A loss correction encoding device ( | 08-26-2010 |

20090164864 | INSPECTION MATRIX GENERATION METHOD, ENCODING METHOD, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND ENCODER - A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking qc matrix. An irregular parity check matrix with a LDGM structure is generated, in which the masking qc matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. | 06-25-2009 |

20100037118 | UNIFIED DATA PROTECTION AND DATA DE-DUPLICATION IN A STORAGE SYSTEM - A data storage system comprises a plurality of storage devices and a storage system controller. The storage system controller controls data and redundancy data stored to and read from the storage devices such that the data is stored at least in part in a region which comprises storage areas on least two of the storage devices and such that the storage devices appear as a single storage device to an entity external to the data storage system. The storage system controller comprises a redundancy data generator for generating the redundancy data, a de-duplication fingerprint definer to define a portion of the redundancy data as additionally representing a de-duplication fingerprint for the region, and a data de-duplicator to identify a duplicated region based upon finding a match to the de-duplication fingerprint within the redundancy data of the data storage system. | 02-11-2010 |

20100122142 | Scalable Decoder Architecture for Low Density Parity Check Codes - A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values. | 05-13-2010 |

20100281329 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM - The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors. | 11-04-2010 |

20100281332 | ENCODING METHOD AND DEVICE FOR LOW DENSITY GENERATOR MATRIX CODES - The present invention discloses an encoding method and device for Low Density Generator Matrix Codes (LDGC). Wherein, the method comprises: construct an LDGC mother code set using a plurality of LDGC with code rate R | 11-04-2010 |

20100281333 | FEEDBACK WITH UNEQUAL ERROR PROTECTION - Methods and devices provide a feedback message having unequal error protection. The feedback message may include channel quality indicators. The channel quality indicators may have different levels of error protection based on a transmission property. | 11-04-2010 |

20100122138 | Radio Communication Device and Radio Communication Method - Provided is a radio communication device which can always obtain an optimal error ratio characteristic in HARQ using the LDPC code as an error correction code. The device includes: a rearrangement unit ( | 05-13-2010 |

20130007555 | METHODS, SYSTEMS, AND APPARATUS FOR TAIL TERMINATION OF TURBO DECODING - Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder. | 01-03-2013 |

20080244353 | METHOD FOR CREATING AN ERROR CORRECTION CODING SCHEME - The present invention relates to a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further comprises a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result. | 10-02-2008 |

20120131409 | RATE-COMPATIBLE PROTOGRAPH LDPC CODE FAMILIES WITH LINEAR MINIMUM DISTANCE - Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero. LDPC codes built from the protographs created by these methods can simultaneously have low error floors and low iterative decoding thresholds. | 05-24-2012 |

20120240004 | System and Method for Achieving Higher Data Rates in Physical Layer Devices - A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse. | 09-20-2012 |

20120240001 | LDPC CODE FAMILY FOR MILLIMETER-WAVE BAND COMMUNICATIONS IN A WIRELESS NETWORK - A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘−1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value. | 09-20-2012 |

20100100790 | ENCODING OF LDPC CODES - A method and apparatus are disclosed that include encoding a codeword using a systematic low density parity check matrix using an encoder, the low density parity check matrix comprising a first sub-matrix associated with information symbols, a second sub-matrix having a block triangular structure associated with a first subset of parity check symbols and a third sub-matrix that is invertible and associated with a second subset of parity check symbols, the encoding performed over the second sub-matrix before the third sub-matrix. | 04-22-2010 |

20110202814 | INTERLEAVING SCHEME FOR AN LDPC CODED 32 APSK SYSTEM - An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use. | 08-18-2011 |

20090177940 | APPARATUS AND METHOD FOR ERROR CORRECTION IN MOBILE WIRELESS APPLICATIONS INCORPORATING ERASURE TABLE DATA - A receiver ( | 07-09-2009 |

20100174966 | DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION - A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected. | 07-08-2010 |

20100146360 | Unified Decoder for Convolutional, Turbo, and LDPC Codes - A unified decoder ( | 06-10-2010 |

20100275095 | DIGITAL TELEVISION SYSTEM - Disclosed is a digital television system carrying out modulation/demodulation by VSB (vestigial side band). A VSB transmitter includes an additional error correction encoder designed in a manner that a signal mapping of a TCM encoder is considered, a multiplexer (MUX), a TCM encoder operating in a manner corresponding to state transition processes of the additional error correction encoder, and a signal transmission part including an RF converter. And, A VSB receiver includes a signal receiver part receiving a signal transmitted from the transmitter, a TCM decoder, a signal processing part including a derandomizer, and an additional error correction decoder part. | 10-28-2010 |

20090183049 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 07-16-2009 |

20100275091 | DECODING METHOD FOR LOW DENSITY GENERATOR MATRIX CODE - The present invention provides a method for decoding a low density generator matrix code (LDGC), applied for decoding transmitted original information bits encoded in LDGC code. The method comprises the following steps: A: deleting a part erased by a channel in a received code word sequence R filled by a known bit sequence to obtain an erased code word sequence Re, and deleting the rows corresponding to the erased part from a transposed matrix G | 10-28-2010 |

20130097469 | LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 04-18-2013 |

20150046764 | RECORDING AND REPRODUCING APPARATUS - According to one embodiment, a recording and reproducing apparatus includes a first masking unit configured to apply first bit masking to error correction code (ECC) encoded data using a bit sequence for masking, to generate a masked bit sequence to be recorded on a medium, and a de-masking unit configured to apply de-masking, using the bit sequence for masking, to a sequence of decision values based on a signal read from the medium to generate a sequence of de-masked decision values to be ECC decoded. The bit sequence for masking comprises an iteration of a fixed bit sequence of N (>1) bits. The bit de-masking is an inverse process corresponding to the first bit masking. | 02-12-2015 |

20110197104 | METHOD AND APPARATUS FOR ENCODING AND DECODING DATA - A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K′ is determined that is related to K″, where K″ from a set of sizes; wherein the set of sizes comprise K″=a | 08-11-2011 |

20090276682 | TURBO LDPC DECODING - An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates. | 11-05-2009 |

20090300460 | Optical transmitter and receiver and optical transmission and reception system - An optical transmitter and receiver has stored in advance therein FEC techniques and applicable conditions for applying the FEC techniques to a counterpart optical transmitter and receiver. The optical transmitter and receiver measures a state of receiving data transmitted from the counterpart optical transmitter and receiver, determines an applicable condition satisfying the measured data reception state from among the stored applicable conditions, and selects a FEC technique stored in association with the applicable condition determined as satisfying. The optical transmitter and receiver then notifies the counterpart optical transmitter and receiver of the selected FEC technique. | 12-03-2009 |

20110271164 | MEMORY CONTROLLER AND MEMORY MANAGEMENT METHOD - Provided is a memory controller that generates Error Correction Code (ECC) information for data based on a required reliability level predetermined based on a type of the data, that computes an ECC code for the data based on the ECC information, and that records the ECC code in a memory based on the ECC information. | 11-03-2011 |

20140129895 | PARALLEL BIT INTERLEAVER - A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. | 05-08-2014 |

20140129894 | Efficient, Programmable and Scalable Low Density Parity Check Decoder - Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time. | 05-08-2014 |

20120297266 | METHOD FOR PROCESSING FORWARD ERROR CORRECTION, FEC, DATA, DEVICE AND SYSTEM THEREOF - A method for processing Forward Error Correction, FEC, data, which includes: a sender encapsulates the FEC data to be a Transport Stream, TS, message, sets FEC identification information in the TS message, and encapsulates the TS message to be a Real-time Transport Protocol, RTP, message; then sends the RTP message to a terminal side. The reception end receives the RTP message; if the reception end has a function for FEC decoding, the reception end identifies the FEC data according to the FEC identification information in the TS message of the received RTP message, and recovers the missed media message according to the FEC data; if the reception end does not have the function for FEC decoding, the reception end processes the RTP message after removing the message header. The embodiments of the present invention also provide a transmission and processing device. | 11-22-2012 |

20110209027 | ERROR DETECTION IN PHYSICAL INTERFACES FOR POINT-TO-POINT COMMUNICATIONS BETWEEN INTEGRATED CIRCUITS - An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports. | 08-25-2011 |

20110209026 | Systems and Methods for Data Recovery Using Enhanced Sync Mark Location - Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is discussed that includes a data storage circuit, a pattern comparison circuit, and a threshold comparison circuit. The data storage circuit is operable to store a first set of data samples corresponding to a region of interest. The pattern comparison circuit is operable to compare a subset of the first set of data samples with a subset of a second set of data samples corresponding to the region of interest. The pattern comparison circuit is operable to yield a match value corresponding to a degree of similarity between the first set of data samples with the subset of a second set of data samples. The threshold comparison circuit is operable to indicate an anchor point based at least in part on the magnitude of the match value relative to a threshold value. | 08-25-2011 |

20110209025 | MULTICAST SUBSCRIPTION BASED ON FORWARD ERROR CORRECTION - Embodiments are disclosed herein that relate to multicast subscription based on forward error correction. One disclosed embodiment comprises a network-accessible server having a data-holding subsystem holding instructions executable by a logic subsystem to receive a content item, and form a first version of the content item having a first level of forward error correction and a second version of the content item having a second level of forward error correction. The instructions are further executable to stream the first version of the content item to a first multicast address, and while streaming the first version of the content item, stream the second version of the content item to a second multicast address. | 08-25-2011 |

20130086444 | ERROR DETECTION CODE ENHANCED SELF-TIMED/ASYNCHRONOUS NANOELECTRONIC CIRCUITS - Provided is a system including a group of error-detecting/correcting-code self-checked/self-timed/self-corrected circuits for logic robust and performance scalable nanoelectronic design, including: (1) a combinational logic network that outputs an error-detecting/error-correcting code (EDC/ECC); and (2) an error-detecting module which gates an external clock (in a self-checked circuit), or generates an internal clock (in a self-timed circuit), and/or an error-correcting module which corrects the sequential element states (in a self-corrected circuit). Also provided is a method for implementing an error-detecting/error-correcting code (EDC/ECC) self-checked/timed/corrected circuit. The method includes (1) encoding combinational logic outputs in an error-detecting/correcting code (EDC/ECC), (2) synthesizing combinational logic, and (4) generating a gated clock in a self-checked circuit, an internal clock in a self-timed circuit, and/or corrected signals in a self-corrected circuit. | 04-04-2013 |

20130086442 | STORING ENCODED DATA SLICES IN A DISPERSED STORAGE UNIT - A method begins by a processing module receiving a write request that includes a batch of encoded data slices and a corresponding batch of slice names, wherein the batch of encoded data slices includes encoded data slices that have slices names that have a common data object storage name, a common slice storage name, and a different data segment storage name. The method continues with the processing module determining whether a storage file exists based on the common data object storage name. The method continues with the processing module creating the storage file based on the common data object storage name when the storage file does not exist. The method continues with the processing module storing the batch of encoded data slices in the storage file based on the corresponding batch of slice names. | 04-04-2013 |

20110022924 | Device and Method for Frame Erasure Concealment in a PCM Codec Interoperable with the ITU-T Recommendation G. 711 - A device and method for resynchronization and recovery after frame erasure concealment of an encoded sound signal comprise decoding, in a current frame, a correctly received signal after the frame erasure. Frame erasure concealment is extended in the current frame using an erasure-concealed signal from a previous frame to produce an extended erasure-concealed signal. The extended erasure-concealed signal is correlated with the decoded signal in the current frame and the extended erasure-concealed signal is synchronized with the decoded signal in response to the correlation. A smooth transition is produced in the current frame from the synchronized extended erasure-concealed signal to the decoded signal. | 01-27-2011 |

20100138720 | CHANNEL-ENCODING/DECODING APPARATUS AND METHOD USING LOW-DENSITY PARITY-CHECK CODES - An encoding/decoding apparatus and method using a low-density parity-check code (LDPC code) is disclosed. Basic column group information, serving as a set of information regarding positions of rows with weight 1, is extracted from a reference column in each column group of a predetermined parity-check matrix. Column group information transforms the positions of rows with weight 1 into positions whose lengths are within a required parity length. A parity-check matrix is generated according to the generated column group information. Data is encoded or decoded based on the generated parity-check matrix. | 06-03-2010 |

20080276149 | Error control code apparatuses and methods of using the same - An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data. | 11-06-2008 |

20130339816 | CONSERVING COMPUTING RESOURCES DURING ERROR CORRECTION - Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for performing data decoding and error correction. In various embodiments, a plurality of bits of encoded data may be received, e.g., by an iterative decoder. In various embodiments, the iterative decoder may generate a set of m tuples A, each tuple in set A including a symbol comprising a group of bits of the encoded data and a probability associated with the symbol. In various embodiments, the encoded data may be decoded using the set of m tuples. In various embodiments, this may include allocating fewer bits to storage of a probability associated with a first tuple of the set A than are allocated for storage of a probability associated with a second tuple of the set A. Other embodiments may be described and/or claimed. | 12-19-2013 |

20130339815 | Power-Optimized Decoding of Linear Codes - A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word. | 12-19-2013 |

20090063929 | Apparatus and method for transmitting and receiving data in a communication system using low density parity check codes - An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme. | 03-05-2009 |

20100058142 | APPARATUS, METHODS, AND COMPUTER PROGRAM PRODUCTS UTILIZING A GENERALIZED TURBO PRINCIPLE - Exemplary embodiments of the invention provide a generalized Turbo principle that enables the exchange of region beliefs between components. The generalized Turbo principle provides various advantages over the traditional Turbo principle such as, for example, a lower Bit Error Rate (BER) and/or a better quality of the end-result marginals. In one exemplary embodiment, a method includes: receiving an encoded signal (501); and decoding the received signal using a generalized Turbo principle wherein region beliefs are exchanged between components (502). In another exemplary embodiment, methods, computer programs and apparatus are presented for generating a graph structure for a system having a plurality of components. As a non-limiting example, the generated graph structure may be seen to correspond to the region graphs underlying the generalized Turbo principle. | 03-04-2010 |

20100162073 | BIT MAPPING/DEMAPPING METHOD AND APPARATUS FOR COMMUNICATION SYSTEM - An improved bit mapping method and apparatus for a communication system is provided. A bit mapping method of the present invention includes arranging coded bits in a codeword in an order of recovery capability; setting a shift region including a number of coded bits; rearranging the coded bits in the shift region by shifting the shift region by a number of bits equal to a number of bits that is indicated by a shift factor; and mapping the rearranged coded bits into a modulation symbol in an order of reliability from a lowest reliability bit position to a highest reliability bit position of the modulation symbol. | 06-24-2010 |

20090119566 | TRANSMITTING DATA WITH VARIABLE UNIT FOR PLAYBACK - Provided is a transmitter for continuously and sequentially transmitting data with a variable unit for playback. The transmitter includes an obtaining section, a buffer, a computing section and a transmitting section. The obtaining section sequentially obtains segment data of the data to be transmitted. The buffer stores an error correction code to correct an error caused in the data by transmission. The computing section computes, every time newly obtained segment data reaches a predetermined size, XOR of the error correction code already stored in the buffer and the newly obtained segment data, and then updates the error correction code with the computed XOR. The transmitting section sequentially transmits the obtained segment data, as well as reads from the buffer and transmits the updated error correction code every time the computing section computes XOR for data in a size corresponding to the unit for playback. | 05-07-2009 |

20080270868 | DECODING APPARATUS - In the present application, there is provided a decoding apparatus for decoding low density parity check codes, including: a plurality of storage sections configured to store logarithmic likelihood ratios or logarithmic posteriori probability ratios for one codeword into addresses thereof which are independent of each other thereamong; and a readout section configured to simultaneously read out, from among the logarithmic likelihood ratios or logarithmic posteriori probability ratios for the one codeword stored in the storage sections, a plurality of ones of the logarithmic likelihood ratios or logarithmic posteriori probability ratios which correspond to non-zero value elements in a predetermined one row of the check matrix used in a coding process of the low density parity check codes. | 10-30-2008 |

20110022926 | MESM: A FAST BJCR BASED DECODER IMPLEMENTATION SCHEME - A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations. | 01-27-2011 |

20110022925 | Turbo Coding for Upstream and Downstream Transmission in Cable Systems - A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data. | 01-27-2011 |

20110022923 | System and Method for Achieving Greater Than 10 Gbit/s Transmission Rates for Twisted Pair Physical Layer Devices - A system and method for achieving greater than 10 Gbit/s transmission rates for twisted pair physical layer devices. An architecture is provided that enables transmission at the next standardized transmission rate over structured cabling. | 01-27-2011 |

20110022922 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′ | 01-27-2011 |

20110022921 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′ | 01-27-2011 |

20110022920 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′ | 01-27-2011 |

20100146364 | METHOD AND APPARATUS FOR ENCODING/DECODING BUS SIGNAL - Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal. | 06-10-2010 |

20100146362 | Contention-free parallel processing multimode LDPC decoder - A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process. | 06-10-2010 |

20090158116 | APPARATUS AND METHOD FOR GENERATING LOW DENSITY PARITY CHECK CODES FOR SEQUENTIAL DECODING ALGORITHM - A method for generating a Low Density Parity Check (LDPC) code is provided. The method includes generating subsets each including a same number of check nodes, connecting each of variable nodes to the check nodes of the subsets so that the each of subsets is equal in degree or a difference in degree between the subsets becomes a maximum of 1, setting elements corresponding to check nodes connected to each of the variable nodes, to a non-zero value, and generating a parity check matrix H having rows corresponding to the check nodes and columns corresponding to the variable nodes. | 06-18-2009 |

20100146367 | SYSTEM FOR TESTING THE UPSTREAM CHANNEL OF A CABLE NETWORK - A system for testing a portion of a cable network provides a pattern generator, addresser, forward error corrector, and comparator. The system is particularly adapted to testing the upstream channel in a cable network. The pattern generator generates a test signal. The addresser addresses the signal to a known server and also instructs the known server to return the test signal to the test system. The forward error corrector corrects errors introduced in the test signal in transmission from the known server to the test system. The comparator then compares the returned test signal to the originally transmitted test signal to determine the performance of the back channel. Preferably, the comparator uses a bit error rate test to determine the performance of the back channel. | 06-10-2010 |

20140101509 | Systems and Methods for Parallel Retry Processing During Iterative Data Processing - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 04-10-2014 |

20120198300 | PROVIDING CAPACITY OPTIMIZED STREAMING DATA WITH FORWARD ERROR CORRECTION - In an example embodiment, there is described herein a methodology were the Forward Error Correction (FEC) data for a data stream is distributed into a plurality of FEC sub-streams. Subscribers to the data stream indicate which of the plurality of FEC sub-streams should be provided to them. The distribution of FEC sub-streams are limited to subscribed FEC sub-streams. FEC sub-streams with no subscribers are not forwarded beyond a distribution point such as an access point (AP). | 08-02-2012 |

20090187805 | Turbo decoding module supporting state n metric value normalization operations - A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric performs error detection operations, and extracts information from a MAC packet that it produces. | 07-23-2009 |

20090183048 | Systems and methods for LDPC coded modulation - Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error floor, no cycles, an equal bit error rate for the information bits and the parity bits, and timely construction of both a parity check matrix with variable codeword size and a generator matrix is possible. | 07-16-2009 |

20090183047 | Method for Generating Ldpc Codes and Apparatus Using Ldpc Codes - A method for generating an LDPC (low density parity check) code, comprising steps of: determining the number of rows and the number of columns in a matrix for forming the LDPC code according to predetermined code rate and constraint length; dividing the matrix into a plurality of layers according to a predetermined column weight; selecting a parallelization factor; dividing at least one of said layers in the matrix into a plurality of sub-layers and dividing each said sub-layer into a plurality of modular data blocks, according to the parallelization factor; determining the position of each weighted element in each modular data block according to said column weight and a predetermined row weight, so as to form said LDPC code. | 07-16-2009 |

20090187803 | DECODING OF ERROR CORRECTION CODE USING PARTIAL BIT INVERSION - A method includes receiving an Error Correction Code (ECC) code word, which includes multiple encoded bits that represent data and have a bit order. Multiple subsets of the encoded bits are selected using a selection criterion that does not sequentially follow the bit order. For each subset in at least some of the multiple subsets, the bits in the subset are inverted and the code word having the inverted bits is decoded, so as to reconstruct the data. | 07-23-2009 |

20090187802 | DECODING DEVICE AND METHOD, PROGRAM, AND RECORDING MEDIUM - A decoding device for estimating an information word before being coded, wherein a processing range is limited to a range narrower than values that can be assumed by a value used as input to the decoding device, and decoding including a process of performing an operation referring to a look-up table associating a value within the limited range with an operation result when the value is substituted into a predetermined function is performed. | 07-23-2009 |

20130166985 | METHOD OF DETERMINING AT LEAST ONE PARAMETER OF AN ERROR-CORRECTING CODE IMPLEMENTED ON TRANSMISSION, CORRESPONDING DEVICE AND COMPUTER PROGRAM - A method and apparatus are provided for determining at least one parameter of an error correcting code implemented on transmission, termed a “coding parameter”, by analyzing a binary train received. The method implements a first step making it possible to coarsely define said at least one coding parameter, and a second step making it possible to refine said at least one coding parameter. | 06-27-2013 |

20090177942 | SYSTEMS AND METHODS FOR MEDIA CONTAINER FILE GENERATION - A method includes organizing a first media source block in the media container file; calculating forward error correction (FEC) redundancy data based on the first media source block; organizing the FEC redundancy data in at least one FEC reservoir in the media container file; providing, in the media container file, meta data providing an association between the first media source block and the at least one FEC reservoir; storing the first media source block as a first elementary item in the media container file; and providing, in the media container file, information that the first elementary item comprises the first media source block | 07-09-2009 |

20090259914 | DIGITAL CONTENT PROTECTION SYSTEMS AND METHODS - What is disclosed is a method of operating an integrated circuit which includes an input module, an output module, and a processing module coupled to the input module and the output module. The method includes, in the input module, receiving a first data segment; in the processing module, reading a hard coded identifier from an identifier module coupled to the processing module, processing the first data segment with the hard coded identifier to generate a first encoded data segment; and in the output module, transferring the first encoded data segment for storage on a storage system. | 10-15-2009 |

20090144598 | ERROR CORRECTING CODE PREDICATION SYSTEM AND METHOD - In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically, and memory can receive information to be stored in the memory, select a portion of memory to store the information, and store the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory. | 06-04-2009 |

20080320360 | CONTROL METHOD OF INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING DEVICE - A transmitting side device ( | 12-25-2008 |

20090249161 | METHOD OF RESTORING DATA - A method of restoring data from a stream of data segments each including first synchronization information followed by first user data information, second synchronization information, and second user data information, the method includes extracting first and second user data information on the basis of the first synchronization information, and converting the first and second user data information into reproduced data, and carrying out error recovery operation when the detecting of first synchronization information is not successful by a process having extracting second user data information on the basis of the detected second synchronization information, suspending the restoring of data in pipeline operation from another of the data segments subsequent to the certain data segment, and converting the second user data information into reproduced data while the restoring of data in pipeline operation is suspended. | 10-01-2009 |

20090249159 | LDPC ENCODER AND DECODER AND LDPC ENCODING AND DECODING METHODS - Provided are an LDPC encoder and decoder, and LDPC encoding and decoding methods. The LDPC encoder includes: a code generating circuit that includes a memory storing a first parity check matrix and sums a first row which is at least one row of the first parity check matrix and a second row which is at least one of the remaining rows of the first parity check matrix to output a second parity check matrix; and an encoding circuit receiving the second parity check matrix and an information word to output an LDPC-encoded code word. Also the LDPC decoder includes: a code generating circuit including a memory which stores a first parity check matrix and summing a first row which is at least one row of the first parity check matrix and a second row which is at least one of the remaining rows of the first parity check matrix to output a second parity check matrix; and a decoding circuit receiving the second parity check matrix and a code word to output an LDPC-decoded information word. | 10-01-2009 |

20090249160 | METHODS AND APPARATUS FOR POWER REDUCTION IN ITERATIVE DECODERS - There are provided a method, an apparatus and a computer program product for reducing power consumption in an iterative decoder, for example, for low-density parity-check (LDPC) codes or turbo codes. The apparatus includes a memory device and an iteration termination device. The memory device is for storing a decoded codeword for a current iteration, for each iteration of the iterative decoder prior to a maximum number of iterations. The iteration termination device is for comparing the decoded codeword for the current iteration to a previously stored decoded codeword for the previous iteration, incrementing a confidence value when the decoded codeword for the current iteration matches the previously stored decoded codeword for the previous iteration, and terminating further iterations of the iterative decoder when the confidence value exceeds a pre-specified threshold value. | 10-01-2009 |

20090241006 | Bitwise Operations and Apparatus in a Multi-Level System - A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power. | 09-24-2009 |

20090210767 | APPARATUS AND METHOD FOR ENCODING AND DECODING CHANNEL IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES - An apparatus and method for generating a parity-check matrix of a Low-Density Parity-Check (LDPC) code are provided. Parameters for designing the LDPC code are determined, and a first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix, and a third parity-check matrix is created by rearranging the second parity-check matrix. | 08-20-2009 |

20090094501 | METHODS AND APPARATUS TO SELECT TORNADO ERROR CORRECTION PARAMETER - Methods and apparatus to select Tornado forward error correction parameters for delivery systems are disclosed. A disclosed example system includes a transmitter station comprising a processor to select a Tornado error correction parameter based on an error correction configuration for a file and to indicate to a receiver the selected Tornado error correction parameter, and a Tornado error correction circuit to encode the file based on the selected Tornado error correction parameter. | 04-09-2009 |

20110145674 | High-efficiency dynamic transmission that has a high speed and reliability - A system and method for error correction coding is configured to dynamically implement one of a number of error correction coding methods during a transmission of data. The error correction coding method is selected based on a measured bit error rate during the transmission of data. The implementation of the error correction coding method is performed without interrupting the data transmission. | 06-16-2011 |

20090063927 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A decoding section for decoding inputted first data; a first memory for being adapted to store second data obtained by decoding the first data; a second memory for being adapted to store error information on an error in decoding of the first data; and an output section for outputting the second data, wherein when the output section reads and outputs the second data from the first memory, the output section reads and outputs, as data corresponding to an error of the first data, second data stored in the second memory and serving as a decoding result of the other part of the first data based on the error information stored in the second memory. | 03-05-2009 |

20090132886 | Method of Encoding and Decoding Using LDPC Code - A method of encoding/decoding using an LDPC code is disclosed, by which performance is enhanced and by which complexity is reduced. In encoding/decoding using an LDPC code defined by an (n−k) | 05-21-2009 |

20120079341 | ITERATIVE DECODING OF LDPC CODES WITH ITERATION SCHEDULING - A method includes accepting modulated symbols, which carry bits of a code word of a Low Density Parity Check (LDPC) code, and computing respective soft input metrics for the bits. The code word is decoded using an iterative LDPC decoding process that includes selecting, based on a predefined criterion, a number of internal iterations to be performed by an LDPC decoder ( | 03-29-2012 |

20120079340 | COMMUNICATIONS SYSTEM EMPLOYING LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path. | 03-29-2012 |

20090083604 | Ldpc encoders, decoders, systems and methods - An LDPC encoder with a complexity that increases linearly as a function of block size is provided. They arc implementable with simple logic consisting of a repeater with an irregular repeat pattern, an interleaver, and an accumulator that performs irregular accumulations. | 03-26-2009 |

20090241007 | METHOD AND APPARATUS FOR UNEQUAL ERROR PROTECTION OF VIDEO SIGNAL OVER WIDEBAND HIGH FREQUENCY WIRELESS SYSTEM - Disclosed are an Unequal Error Protection (UEP) method and apparatus of video signals based on a dynamic link in a broadband high frequency wireless system. | 09-24-2009 |

20080263425 | Turbo LDPC Decoding - An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates. | 10-23-2008 |

20090199067 | METHOD AND APPARATUS OF ENCODING AND DECODING DATA USING LOW DENSITY PARITY CHECK CODE IN A WIRELESS COMMUNICATION SYSTEM - A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’. | 08-06-2009 |

20090106621 | DATA DECODING APPARATUS, DATA DECODING METHOD, DATA TRANSMITTING/RECEIVING SYSTEM, DATA RECEIVING APPARATUS, DATA RECEIVING METHOD AND PROGRAM - Disclosed herein is a decoding apparatus for decoding an LDPC (Low Density Parity Check) code received in a first format or a second format wherein a process to decode received values each obtained as a result of receiving the LDPC code in the first or second format includes at least F check-node processes carried out concurrently as processes of F check nodes respectively or F variable-node processes carried out concurrently as processes of F variable nodes respectively. | 04-23-2009 |

20140075261 | OPTIMIZED MECHANISM TO SIMPLIFY THE CIRCULANT SHIFTER AND THE P/Q KICK OUT FOR LAYERED LDPC DECODER - A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes. | 03-13-2014 |

20090063926 | APPARATUS AND METHOD FOR DECODING USING CHANNEL CODE - An apparatus and method for decoding a channel code is disclosed. The method for decoding a channel code includes the steps of receiving a low density parity check (LDPC) encoded signal from a transmitting party, generating a parity check matrix by adjusting the order of rows or columns of the parity check matrix, the parity check matrix including a plurality of groups consisting of a plurality of columns, at least one of the groups including at least one row of which every element is zero (0), and iteratively decoding the received signal for each group by using the generated parity check matrix. | 03-05-2009 |

20100275089 | ITERATIVE DECODING OF PUNCTURED LOW-DENSITY PARITY CHECK CODES BY SELECTION OF DECODING MATRICES - Methods and apparatus for enabling effective decoding of rate-compatible punctured codes are presented herein. A puncturing component can derive one or more partial puncturing patterns and corresponding decoding matrices/graphs that represent punctured code from a parity check matrix/graph of a mother code and a puncturing pattern specified for the mother code. Further, a rowcombining component can combine rows of the parity check matrix/graph based on the derived one or more partial puncture patterns. Further, the rowcombining component can create at least one decoding matrix/graph to represent the punctured code based on the combined rows. In addition, a selection component can select a decoding matrix/graph from the created at least one decoding matrix/graph that does not contain a girth-4 cycle. | 10-28-2010 |

20110041033 | Method and System for Decoding Graph-Based Codes Using Message-Passing with Difference-Map Dynamics - A code to be decoded by message-passing is represented by a factor graph. The factor graph includes variable nodes indexed by i and constraint nodes indexed by a connected by edges for transferring messages m | 02-17-2011 |

20140359390 | Encoding Techniques Using Multiple Coding Strengths within a Single LDPC Code Word - Techniques are presented herein to encode information bits. The information bits are partitioned into at least two groups based on inherent reliability and immunity to channel impairments of the respective bits. Each of the groups of information bits is encoded with a different coding strength. The resulting code word may be stored in a storage media or transmitted in a communication channel. | 12-04-2014 |

20090138780 | METHOD AND DEVICE FOR DECODING A RECEIVED SYSTEMATIC CODE ENCODED BLOCK - A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected. | 05-28-2009 |

20080313522 | DIGITAL BROADCASTING SYSTEM AND DATA PROCESSING METHOD - A digital broadcasting system for transmitting/receiving a digital broadcasting signal and a data processing method are disclosed. First program table information and second program table information, which has an identifier different from an identifier of the first program information, are multiplexed and transmitted. The first program table information describes main service data through fixed reception channel, while the second program information described mobile service data through mobile reception channel. Thus, a broadcast receiving system can receive and output the mobile service data by parsing the second program table information. | 12-18-2008 |

20130219240 | DATA PACKET TRANSMISSION/RECEPTION APPARATUS AND METHOD - A method and apparatus are provided for recovering data efficiently even when data loss has occurred over a channel or network. The packet transmission method includes arranging a first transmission packet in a source symbol in a first region of a source block; arranging a second transmission packet in a space starting with an empty space of a last source symbol where the first transmission packet is arranged, remaining after arranging the first transmission packet; arranging information related to the second transmission packet in a second region of the source block; performing Forward Error Correction (FEC) encoding on the source block; and transmitting the encoded source block. | 08-22-2013 |

20100162071 | CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITECTURE LDPC DECODER - A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute | 06-24-2010 |

20090259912 | LDPC CODES AND STOCHASTIC DECODING FOR OPTICAL TRANSMISSION - A method for error correction and a decoder using low density parity check (LDPC) codes includes initializing extrinsic probability information between variable nodes and check nodes in a bipartite graph including generating a Bernoulli sequence according to a probability of a bit having a value one. Parity checking is performed in accordance with a parity check equation. If the parity check equation is not satisfied, then extrinsic information is updated in check nodes from variable nodes using a parity node update logic circuit in a first half iteration, extrinsic information is updated in variable nodes from check nodes using a variable node update logic circuit in a second half iteration, and the variable nodes are updated with a probability based upon the extrinsic information passed between check nodes and variable nodes wherein the probability represents a likelihood that an ith bit is a one. Information bits are passed when the parity check equation is satisfied or a predetermined number of iterations has been reached. | 10-15-2009 |

20090199066 | METHOD FOR DETERMINING TRANSPORT BLOCK SIZE AND SIGNAL TRANSMISSION METHOD USING THE SAME - A method for determining a transport block size and a signal transmission method using the same are disclosed. When the signal transmission method constructs a transport block size combination by predetermining the transport block size, it prevents the insertion of any dummy bits in consideration of the limitation of an input bit length of an encoder during an encoding step. If a CRC is attached to the transport block and the transport block is segmented into a plurality of code blocks, the signal transmission method can establish a length of the transport block in consideration of a length of the CRC attached to each code block. | 08-06-2009 |

20090199068 | METHOD AND APPARATUS OF ENCODING AND DECODING DATA USING LOW DENSITY PARITY CHECK CODE IN A WIRELESS COMMUNICATION SYSTEM - A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’. | 08-06-2009 |

20090199065 | GLDPC ENCODING WITH REED-MULLER COMPONENT CODES FOR OPTICAL COMMUNICATIONS - A method of encoding for optical transmission of information includes encoding information with a generalized low-density parity-check (GLDPC) code for providing coding gains, and constructing the GLDPC code with a Reed-Muller RM code as a component code, the component code being decodable using a maximum posterior probability (MAP) decoding. In a preferred embodiment, the GLDPC code includes a codeword length of substantially 4096, an information word length of substantially 3201, a lower-bound on minimum distance of substantially greater than or equal to 16, a code rate of substantially 0.78 and the RM component code includes an order of substantially 4 and an r parameter of substantially 6. | 08-06-2009 |

20090199064 | Corrupted packet toleration and correction system - A corrupted packet toleration and correction system includes a receiver adapted to employ a cross layer protocol that distinguishes between corrupted packets and error-free packets, and tolerates corrupted packets by making side information about corrupted packets available to an application layer. A decoder of the application layer provides hybrid decoding that simultaneously handles errors and erasures and takes advantage of the side information, including employing LDPC (HEEL) based codes over short packet blocks in the cross layer protocol. | 08-06-2009 |

20100162072 | Processing of Biometric Data by Transformation - Biometric data relating to a biological part are processed by obtaining, on the one hand, a first set of transformed biometric data (f(B | 06-24-2010 |

20100169737 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 07-01-2010 |

20100185917 | Feedback-based management of variable-rate communication links - A method for communication includes transmitting data from a transmitter to a receiver using Adaptive Coding and Modulation (ACM). The data rate is set by selecting, based on feedback, an ACM profile defining a Forward Error Correction code and a modulation scheme. Upon detecting that the feedback is unusable, an operation of the transmitter is changed independently of the feedback. | 07-22-2010 |

20100185915 | METHOD AND DEVICE FOR ENCODING THE LOW DENSITY GENERATOR MATRIX CODE - A method and system for encoding the low density generator matrix code are disclosed. The encoding method includes the following steps: S | 07-22-2010 |

20100185913 | METHOD FOR DECODING LDPC CODE AND THE CIRCUIT THEREOF - A method for decoding LDPC code comprises the steps of: marking non-zero sub-matrices of a parity-check matrix of an LDPC code as 1 and zero sub-matrices of the parity-check matrix as 0 to form a simplified matrix; rearranging the sequence of rows of the simplified matrix according to the dependency between these rows; and updating the LDPC code in accordance with the sequence of the rows. | 07-22-2010 |

20120246535 | PROCESSING OF BLOCK AND TRANSACTION SIGNATURES - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed. | 09-27-2012 |

20100174964 | SYSTEMS AND METHODS FOR A TURBO LOW-DENSITY PARITY-CHECK DECODER - A method for forming a plurality of parity check matrices for a plurality of data rates for use in a Low-Density Parity-Check (LDPC) decoder, comprises establishing a first companion exponent matrix corresponding to a first parity check matrix for a first data rate, and partitioning the first parity check matrix and the first companion exponent matrix into sub-matrices such that the first parity check matrix is defined using a cyclical shift of an identity matrix. | 07-08-2010 |

20120272117 | TRANSMITTER AND RECEIVER FOR BROADCASTING DATA AND PROVIDING INCREMENTAL REDUNDANCY - A transmitter for broadcasting data in a broadcasting system that improves the decoding quality, if needed, comprises a data input, and an encoder for error correction code encoding the input data words into codewords, a codeword comprising a basic codeword portion and an auxiliary codeword portion, wherein said encoder is adapted for generating said basic codeword portion from an input data word according to a first code and for generating said auxiliary codeword portion from an input data word according to a second code, said basic codeword portion being provided for regular decoding and said auxiliary codeword portion being provided as incremental redundancy if regular decoding of the codeword by use of the basic codeword portion is erroneous. Further, the transmitter comprises a data mapper for mapping the codewords onto frames of a transmitter output data stream, and a transmitter unit for transmitting said transmitter output data stream. | 10-25-2012 |

20100185916 | AUDIO REPRODUCTION DEVICE, INFORMATION REPRODUCTION SYSTEM, AUDIO REPRODUCTION METHOD, AND PROGRAM - An audio reproduction device includes a decoding processor to decode input voice data, a discontinuousness determination unit to determine whether or not a packet is discontinuous with a preceding packet, a reset processing unit to reset decode information, a frequency analysis unit to perform frequency analysis on the decoded data, an envelope calculation unit to calculate an envelope of the decoded data, a level difference calculation unit to calculate a level difference of the decoded data, a correction processing unit to apply a specific correction process to the decoded data if the correction process is necessary, and a processing determination unit to determine whether or not the correction process is to be performed, to determine whether or not the packet data is discontinuous, to determine which correction process is to be applied, and to output an instruction to perform the correction process. | 07-22-2010 |

20100180175 | METHOD FOR CONSTRUCTING LDPC CODE IN THE MOBILE DIGITAL MULTIMEDIA BROADCAST SYSTEM - A method for constructing LDPC (Low-Density Parity-Check) code in the mobile digital multimedia broadcast system is provided, wherein the Low-Density Parity-Check matrix of the LDPC code is iteratively constructed according to a code-table and expansion method, and the code-table is a part of the constructed Low-Density Parity-Check matrix. According to the constructing method of the present invention, the LDPC code having excellent performance of error correcting coding which is applicable to the mobile digital multimedia broadcast system. | 07-15-2010 |

20100199144 | Method and device for indicating an uncorrectable data block - A method and device for indicating an uncorrectable data block. The method includes: if a forward error correction decoding fails, setting synchronization character of at least one of the corresponding data blocks to a first character; and performing line decoding on the data block with the set first character, and outputting decoded data. With the invention, indicating the uncorrectable data block Simple and effective to a line decoding module can be implemented in case of a failure of FEC decoding. | 08-05-2010 |

20090063928 | FEC TRANSMISSION PROCESSING APPARATUS AND METHOD AND PROGRAM RECORDING MEDIUM - There is provided with an FEC transmission processing apparatus including: a media packet acquiring unit configured to successively acquire media packets from a media packet generator; a media packet transmission unit configured to transmit the media packets acquired to a media packet reception processing apparatus; an FEC packet generation unit configured to generate a plurality of FEC packets for the media packet reception processing apparatus to recover a lost media packet by carrying out FEC calculation processing using media packets acquired within a predetermined FEC period from acquisition of a first acquired media packet after media packets subjected to the FEC calculation processing immediately before; and an FEC packet transmission unit configured to transmit the FEC packets to the media packet reception processing apparatus within the predetermined FEC period after a lapse of the predetermined FEC period from the acquisition of the first acquired media packet. | 03-05-2009 |

20100162076 | METHOD FOR LOCK-FREE CLUSTERED ERASURE CODING AND RECOVERY OF DATA ACROSS A PLURALITY OF DATA STORES IN A NETWORK - The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness. | 06-24-2010 |

20120198301 | Operational parameter adaptable LDPC (Low Density Parity Check) decoder - Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations. | 08-02-2012 |

20100185914 | Systems and Methods for Reduced Complexity Data Processing - Various embodiments of the present invention provide systems and methods for processing information. For example, a decoding system is disclosed that includes a de-interleaver. The de-interleaver is operable to receive an interleaved codeword that includes two or more reduced codewords interleaved together. Further, the de-interleaver is operable to provide a representation of the two or more reduced codewords. The systems also include a decoder that is operable to decode the two or more reduced codewords. In some instances of the aforementioned embodiments, the decoder is an LDPC decoder that is tailored to the size of one or both of the two or more reduced codewords. | 07-22-2010 |

20100180177 | Decoding system and method for high-density recording medium - In a decoding system and method for a high-density recording medium, a high protective codeword decoder decodes a burst indicator subcode (BIS) while a low protective codeword decoder decodes a long distance code, so as to eliminate the waiting time required for completely decoding all burst indicator subcodes (BISs) and starting the long-distance code (LDC) decoding. In addition, a first memory having a high access speed is implemented to store the BISs and corresponding BIS erasure indicators, and the access to a second memory have a lower access speed relative to the first memory is relatively reduced such that the bandwidth can be effectively used to thereby increase the decoding efficiency on the high-density recording medium. | 07-15-2010 |

20100180174 | DIGITAL SIGNATURE OF CHANGING SIGNALS USING FEATURE EXTRACTION - In one embodiment, a signal transmission authentication apparatus includes an input operable to receive a changing signal, a first extractor operable to extract first phoneme data from the received changing signal, a first generator including logic operable to generate first data representative of the extracted first phoneme data, a first output operable to communicate output data corresponding to the received changing signal and the first data from an associated transmitter to an associated receiver, a second extractor associated with the receiver including logic operable to extract second phoneme data from the received output data via the receiver and regenerate the first phoneme data from the received first data, a comparator including logic operable to generate a comparison signal in accordance with a comparison of the first and second phoneme data, and a second output operable to generate a signal corresponding to authenticity of the received changing signal in accordance with an output of the comparator. | 07-15-2010 |

20090077445 | NONVOLATILE STORAGE DEVICE, CONTROLLER OF NONVOLATILE MEMORY, AND NONVOLATILE STORAGE SYSTEM - A nonvolatile storage device includes a nonvolatile memory for storing data such as a flash memory, and a controller for controlling writing or reading of data to or from the nonvolatile memory. The nonvolatile memory stores control information (control program, control parameter) specifying a method of controlling writing or reading of data to or from the nonvolatile memory. The controller determines a type of the nonvolatile memory, and acquires the control information from the nonvolatile memory according to an acquisition procedure corresponding to the type of the nonvolatile memory, and stores (loads) the control information. | 03-19-2009 |

20100162075 | Low complexity LDCP decoding - A technique for low-density parity-check (LDPC) coding involves utilizing a fixed point implementation in order to reduce or eliminate reliance on floating point operations. The fixed point implementation can be used to calculate check node extrinsic L-value as part of an LDPC decoder in an LDPC system. The technique can include one or more of linear approximations, offset approximations, and node-limiting approximation. A system constructed according to the technique implements one or more of linear approximations, offset approximations, and node-limiting approximation. | 06-24-2010 |

20100281331 | Systems and Methods for a Rateless Round Robin Protocol for Adaptive Error Control - Systems and methods implementing a protocol that provides reliable transport over a point-to-point link characterized by deep and sustained fades. Such a communications link may be a free space optical channel or may be a radio frequency point-to-point channel. Data frames are processed through a circular data buffer that operates in a round robin fashion at a transmission node. The coding and forward error correction processes allow for continued operation in spite of possible signal fades due to atmospheric turbulence or other causes. At a receive node, incoming data is also saved in a circular buffer. A re-acknowledgment list is maintained at the receive node for tracking recently received and decoded data. This allows for a new acknowledgment to be sent in the event that a previously sent acknowledgment failed to reach the transmission node. | 11-04-2010 |

20100180176 | ENCODING METHOD, ENCODER, AND TRANSMITTER - An encoding method by which an encoding speed is improved is disclosed. An encoder ( | 07-15-2010 |

20100241920 | IMAGE DECODING APPARATUS, IMAGE DECODING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An image decoding apparatus is an image decoding apparatus that parses an input bit stream to extract decode parameters and generates a decoded image based on the decode parameters. The image decoding apparatus includes: an error position/recovery position detecting unit that detects an error position and a recovery position in the decode parameters and discards the decode parameters in the error position to the recovery position; and an interpolated-decode-parameter inserting unit that interpolates the decode parameters discarded by the error position/recovery position detecting unit. | 09-23-2010 |

20090222706 | APPARATUS AND METHYOD FOR CHANNEL ENCODING AND DECODING IN COMMUNICATION SYSTEM USING LOW-DENISTY PARITY-CHECK CODES - An apparatus and a method for channel encoding/decoding in a communication system are provided. The apparatus and the method generate LDPC-encoded blocks with various lengths from an LDPC code with fixed length in a communication system using a Low-Density Parity-Check (LDPC) code. The apparatus and the method perform shortening using a predetermined number of shortened bits and perform LDPC encoding. The apparatus and the method apply predetermined rules according to the predetermined number of shortened bits and determine the number of bits to be punctured, and perform puncturing based on the determined number of punctured bits. | 09-03-2009 |

20130238950 | DECODING APPARATUS AND DECODING METHOD FOR DECODING LDPC-ENCODED DATA - A check node processing unit updates an extrinsic value ratio based on a prior value ratio for each row of a parity check matrix with respect to input data. An identifying unit identifies, based on an element of the parity check matrix that can be identified by a row and column associated with the updated extrinsic value ratio, a next-target element in the same column and in a different row. The identifying unit identifies an element to be updated in the next step by the check node processing unit, from among multiple elements included in the same column. A variable node processing unit updates, based on the extrinsic value ratio, a prior value ratio associated with the identified next-target element after the check node processing unit completes the updating of each row. The check node processing unit and the variable node processing unit alternately and iteratively execute their operations. | 09-12-2013 |

20100146366 | WIRELESS TERMINAL BASEBAND PROCESSOR HIGH SPEED TURBO DECODING MODULE - A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives a set of IR samples from the memory, forms a turbo code word from the set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching on the set of IR samples, performs error detection operations, and extracts information from a MAC packet that it produces. | 06-10-2010 |

20100211846 | CHECK MATRIX GENERATING DEVICE, CHECK MATRIX GENERATING METHOD, ENCODER, TRANSMITTER, DECODER, AND RECEIVER - When arranging J cyclic permutation matrices I(p | 08-19-2010 |

20100241922 | ERROR CORRECTION CIRCUIT AND DATA STORAGE DEVICE - According to one embodiment, a circuit includes: an ECC encoder to assign symbols of a data string to M interleaves in sequence, create redundancy symbols for each interleaved string, insert the redundancy symbol into the data string every N symbols of the data string, and create ECC encoded data, where M and N are greater than or equal to 2; and an ECC decoder to assign the symbols of the data string that has been inserted with the redundancy symbols to M interleaves and apply error correction to each assigned string, using the redundancy symbols of that assigned string. The encoder assigns each symbol of the data string that corresponds to an insertion position of the different one of the redundancy symbols in the data string to a next position next to and skipping an in-sequence interleaving position of that symbol, and creates the redundancy symbols for each interleaved string. | 09-23-2010 |

20100241921 | ERROR-CORRECTION DECODER EMPLOYING MULTIPLE CHECK-NODE ALGORITHMS - In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors. | 09-23-2010 |

20100211847 | STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODE - A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[H | 08-19-2010 |

20100229068 | EMBEDDED ELECTRONIC DEVICE AND METHOD FOR STORING DATA - An embedded electronic device is provided. The embedded electronic device comprises a flash memory and a processor. The flash memory comprises a plurality of data storage blocks. The processor performs a parity check process to determine parity data of operation system (OS) data, wherein the parity data serves as a backup for the operation system (OS) data. The processor stores the operation system (OS) data and corresponding parity data into the data storage block of the flash memory. | 09-09-2010 |

20100229066 | CHECK MATRIX GENERATING METHOD - An irregular parity check matrix is generated which has an LDGM structure in which a masking quasi-cyclic matrix and a matrix in which cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. A mask matrix capable of supporting a single encoding rate for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. The irregular parity check matrix is masked using a generated mask matrix, and a parity check matrix is generated combining a masked irregular parity check matrix with a lower triangular matrix formed in a staircase manner to satisfy a single encoding rate. | 09-09-2010 |

20090217131 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 08-27-2009 |

20090217125 | LOW DENSITY PARITY CHECK (LDPC) DECODER - Methods and apparatuses to perform iterative decoding of Low Density Parity Check (LDPC) codes based on selecting a lambda number of minimum values. In one aspect, an LDPC decoder, includes: means for sorting a plurality of incoming messages of a check node according to magnitudes of the incoming messages; means for identifying a predetermined number of unique message magnitudes from the incoming messages; and means for computing outgoing messages for a subset of the plurality of incoming message, where the messages of the subset have different magnitudes larger than the predetermined number of unique message magnitudes but the outgoing messages are computed to have the same magnitude. In at least one embodiment, the decoder further includes means for computing outgoing messages that have magnitudes equal to any of the predetermined number of unique message magnitudes. In general, the magnitudes computed for all outgoing messages may not necessarily be the same. | 08-27-2009 |

20090217121 | Decoding Apparatus and Decoding Method - The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section | 08-27-2009 |

20100050045 | METHOD OF GENERATING A PARITY CHECK MATRIX FOR LDPC ENCODING AND DECODING - A method of encoding input data using a low density parity check (LDPC) code or decoding the encoded data is disclosed. Each index of a model matrix is expanded to an index matrix which includes two or more indexes. Each index included in the index matrix means a specific sub-matrix, and can be replaced with a corresponding sub-matrix to generate a parity check matrix. | 02-25-2010 |

20100050044 | RADIO COMMUNICATION APPARATUS AND TEMPORARY BIT INSERTION METHOD - Provided is a radio communication apparatus capable of always obtaining the optimum error rate characteristic when an LDPC code is used for an error-correcting code. In the apparatus, a temporary bit insertion section ( | 02-25-2010 |

20100138719 | METHOD OF ENCODING DATA USING A LOW DENSITY PARITY CHECK CODE - A method for encoding data using a parity check matrix is disclosed. The method for encoding data using a parity check matrix comprises generating a fourth base matrix by applying a row permutation pattern and a column permutation pattern to rows and columns of a third base matrix, respectively, the third base matrix including a plurality of indexes, each of the plurality of indexes indicating a sub-matrix; generating the parity check matrix by replacing each index of the fourth base matrix with a corresponding sub-matrix; outputting an encoded bit stream by encoding an input bit stream using the generated parity check matrix; and permuting an order of sequences of the encoded bit stream according to an inverse of the column permutation pattern. | 06-03-2010 |

20100138717 | FORK CODES FOR ERASURE CODING OF DATA BLOCKS - Described is a technology in which data blocks are coded into erasure coded blocks in a two-stage, two-level processing operation. In a first processing stage, such as via MDS coding, original blocks are coded into a first level of output data blocks including one or more parity blocks. In a second, fork code processing stage, the first level blocks are partitioned into groups, and those groups used to generate a second level of parity blocks. The blocks are maintained among a plurality of storage nodes. Recovery of a failed data block is accomplished by accessing only the other data blocks associated with the failed data block's coding group (whenever possible), thus facilitating significantly more efficient recovery than with conventional erasure coding techniques. | 06-03-2010 |

20100122139 | PARITY-CHECK-CODE DECODER AND RECEIVING SYSTEM - A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes. | 05-13-2010 |

20100042896 | ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING NON-STANDARD LAYERED-DECODING SCHEDULES - A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer L | 02-18-2010 |

20140310568 | RECEIVER, COMMUNICATION DEVICE, AND COMMUNICATION METHOD - A Sum-product decoder | 10-16-2014 |

20110113300 | DECODING METHOD, DECODING DEVICE, INTERLEAVING METHOD, AND TRANSMITTER - A decoding device allowing a high-speed decoding operation. In a decoding section ( | 05-12-2011 |

20090019333 | Generation of parity-check matrices - Circuits perform row-by-row matrix generation for encoding and decoding of data blocks. They perform fast algebraic generation of high performance low density parity check (LDPC) matrices suitable for use in a wide range of error correction coding and decoding (ECC) applications. Circuit operation is based on a mathematical Cyclic Ring method that enables matrices of any size to be generated from a simple set of initial parameters, based on user-defined performance requirements. The main steps for generating a parity check matrix (H) are selection of an RG matrix structure, selection of Group Ring elements, generating the sub matrices for the RG matrix by a row filling scheme, generating the RG matrix by a cyclic arrangement of the sub matrices, and generating the parity-check matrix by deleting suitably chosen columns from the RG matrix to achieve the desired performance and then transposing the matrix. A circuit performs data encoding or decoding by receiving initial vectors calculated from row vectors of a previously-generated parity check matrix H, cyclic shifting the vectors to generate a desired output row of the parity check matrix H, re-arranging the operation order of the vectors depending on the RG matrix structure and the chosen row, operating on the vectors on information to be encoded. | 01-15-2009 |

20090204869 | METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES - An apparatus and method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes determining a number of parity bits to be subjected to puncturing; dividing the parity bits at predetermined intervals, and determining a number of puncturing bits, which are subjected to puncturing within the predetermined intervals; determining positions of puncturing parity bits corresponding to the determined number of puncturing bits; and repeatedly performing puncturing on the puncturing parity bits corresponding to the determined positions at the predetermined intervals. The predetermined intervals are determined by dividing a length of parity bits by a length of one column group in a parity-check matrix. | 08-13-2009 |

20110066914 | Address Generation Apparatus And Method For Quadratic Permutation Polynomial Interleaver De-Interleaver - An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to L | 03-17-2011 |

20110066913 | APPARATUS AND METHOD FOR HIGH THROUGHPUT UNIFIED TURBO DECODING - An apparatus and method for high throughput unified turbo decoding comprising loading data from a first data window; computing a first forward state metric using the data from the first data window; storing the first forward state metric in a memory; computing a first reverse state metric using the data from the first data window; storing the first reverse state metric in the memory; and computing the log likelihood ratio (LLR) of the first forward state metric and the first reverse state metric. In one aspect, the above-mentioned steps are repeated with data from a second data window. In another aspect, extrinsic information for the first data window associated with the unified turbo decoding is computed. | 03-17-2011 |

20090055704 | Error correction method and apparatus - A transmitting apparatus arranges data in matrix, calculates error correction codes in the data's column direction, arranges the calculated error correction codes in matrix having the same number of columns as the data, attaches number information corresponding to a row number to each row having data or error correction code, encapsulates, into each packet, each row having number information and data or error correction code, plus error detection code detecting one or more bit errors at least in the number information and the data or error correction code in the packet, and transmits the packet. Receiving apparatus discards received packets having detected errors using the error detection code in each packet, checks packet losses according to number information, and restores lost data using the error correction codes. An error correction method compensates for packet losses and bit errors in a packet, realizing efficient transmission with less delay by simple configuration. | 02-26-2009 |

20090319859 | METHOD AND APPARATUS FOR ERROR CORRECTION ACCORDING TO ERASE COUNTS OF A SOLID-STATE MEMORY - Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected. | 12-24-2009 |

20090177941 | MANAGING COMMON UPLINK RESOURCES IN A CELLULAR RADIO COMMUNICATIONS SYSTEM - The technology in this application provides for efficient use of a common uplink radio resource, like the common E-DCH resource. A UE lacking a valid radio network identifier, e.g., a UE in an idle mode, receives a data unit and adds error detection bits to generate a new data unit. The new data unit is divided into segments at a lower protocol layer which are provided for transmission to the network via the common uplink radio resource. A network node detects lower protocol layer data unit segments received on the common uplink radio resource and assembles them into an assembled data unit at a higher protocol layer. Error detection bits included with the assembled data unit are used to determine if the assembled data unit includes correctly received data unit segments, e.g., data unit segments from the same UE. | 07-09-2009 |

20090150745 | TRAPPING SET DECODING FOR TRANSMISSION FRAMES - Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword. | 06-11-2009 |

20080294961 | Method and apparatus for reading data - A reading apparatus reads data from a storage device based on which an error correcting code is to be generated. An error determining unit reads the data from the storage device, and determines whether a read error has occurred in the data. A reading unit re-reads, when the error determining unit determines that a read error has occurred in the data, the same data from the storage device. | 11-27-2008 |

20080263426 | Method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network - A method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network, such as a DOCSIS cable network, is provided. In an embodiment, an upstream modulator portion of a cable modem receives burst data, selectively encodes the burst data for trellis coded modulation to generate encoded symbols, and modulates the encoded symbols for selective transmission over a time division multiple access (TDMA) channel or a synchronous code division multiple access (S-CDMA) channel of the cable network. | 10-23-2008 |

20100306614 | METHOD OF ERROR CONTROL - A method of error control in a wireless access system is disclosed. More particularly, a method of error control using a random liner coding method is disclosed. A method of error control in a wireless access system comprises receiving code blocks generated as data blocks included in a data block set are randomly linear-coded; decoding a predetermined number of code blocks to a first data block set, wherein the predetermined number of code blocks are selected from the code blocks; replacing one or more code blocks among the predetermined number of code blocks with code blocks other than the predetermined number of code blocks selected from the code blocks and decoding them to a second data block set; and comparing the first data block set with the second data block set. | 12-02-2010 |

20100306612 | APPARATUS FOR CORRECTING SINGLE BIT INSERTION OR DELETION IN A DATA PAYLOAD WITH A CHECKSUM CORRECTOR - This application discloses a message format including a data payload of N bits and a corrector component encoding a checksum to correct the checksum of single bit slipping noise, where the checksum is the sum of each data payload bit by its position modulo N+1. The corrector component may encode a second checksum derived from the checksum that may also be included in the message and so on. Apparatus embodiments may include a transmitter generating a transmitted message of this format and/or a receiver using a received message that may be corrupted from the transmitted message through bit slipping in the form of bit insertion or bit deletion. | 12-02-2010 |

20120036410 | Techniques To Control Power Consumption In An Iterative Decoder By Control Of Node Configurations - A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage. | 02-09-2012 |

20110239077 | METHOD FOR CONSTRUCTING CHECKING MATRIX OF LDPC CODE AND CODING AND DECODING APPARATUS UTILIZING THE METHOD - The present invention relates to a method for constructing LPDC code check matrix and encoding and decoding devices using the same. The encoding device encodes the inputted binary information and outputs the encoded system code sequence of position transformation. The encoding device comprises: a matrix multiplication module outputting a check sequence p which is obtained through the binary information sequence m multiplied with a matrix; a sorting index module having N memory units storing index values of a sorting table IDX in turn; and a sorting output module for sorting the m and p and outputting a code word c based on the index value stored in the sorting index table. The present invention constructs the LDPC code check matrix using an algebraic structure, obtaining the LDPC code with stable performance. In addition, the encoding and decoding devices of the present invention occupy less memory, which is preferable for optimization of the devices. | 09-29-2011 |

20090106620 | DECODING APPARATUS, DECODING METHOD AND PROGRAM - Disclosed herein is a decoding apparatus for decoding an LDPC code, the decoding apparatus including: a message computation section configured to carry out a process of decoding received values, where notation F denotes a non-unity measure of the integer P, and outputting F messages; a shift section configured to carry out F×F cyclic shift operations on the F messages and output F messages; a storage section configured to store the F messages and allow the stored F messages to be read out or to store F received values cited above and allow the stored F received values to be read out; and a control section configured to control an operation to supply a unit composed of the F received values to the message computation section by carrying out at least a column rearrangement process or a process equivalent to the column rearrangement process on the received values. | 04-23-2009 |

20090037789 | METHOD OF DECODING CONTENT DATA BLOCKS, CORRESPONDING COMPUTER PROGRAM PRODUCT AND DECODING DEVICE - It is proposed a method of decoding a set of symbols to be decoded, several data blocks representative of the set of symbols to be decoded being received by a decoding node of a communications network. The data blocks are encoded by means of an error correction code enabling a decoding by erasure. The decoding node performs the following steps: a first selecting step of selecting at least one of the data blocks, a first determining step of determining first erasures, a checking step of checking whether the number of the first erasures is below a given threshold. In the event of positive determining, the decoding node performs a first decoding step of decoding by erasure of the set of symbols to be decoded. If not it performs a second selecting step of selecting at least one of the data blocks, a second determining step of determining second erasures, and a second decoding step of decoding by erasure of the set of symbols to be decoded from the second erasures. | 02-05-2009 |

20090037791 | LAYERED DECODER AND METHOD FOR PERFORMING LAYERED DECODING - Embodiments of a decoder and method of decoding blocks of soft bits in a wireless receiver are generally described herein. Other embodiments may be described and claimed. In some embodiments, a memory is initialized with encoded input data and updated with sums of extrinsic reliabilities. Decoded output data is provided from the memory after a predetermined number of iterations. | 02-05-2009 |

20130013972 | CONTINUOUSLY INTERLEAVED ERROR CORRECTION - Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes. | 01-10-2013 |

20090063925 | LCPC DECODING METHODS AND APPARATUS - A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused. | 03-05-2009 |

20100313098 | METHOD FOR TRANSMITTING CONTROL INFORMATION IN WIRELESS COMMUNICATION SYSTEM - A method for transmitting control information in a wireless communication system is provided. A codeword is generated by performing forward error correction (FEC) encoding on control information to generate. An interleaved code is generated by interleaving the codeword. A combined code is generated by combining the codeword and the interleaved code. A transport block is generated by repeating the combined code and is transmitted. | 12-09-2010 |

20100306616 | RECEIVING APPARATUS, RECEIVING METHOD AND PROGRAM, AND RECEIVING SYSTEM - Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a speed control section configured to control a speed of the decoding on the basis of a reception interval of the low density parity check code. | 12-02-2010 |

20100313097 | Flash Memory Organization - A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2 | 12-09-2010 |

20100325511 | METHOD OF GENERATING PARITY-CHECK MATRIX, ENCODING/DECODING METHOD FOR LOW DENSITY PARITY-CHECK CODE WITH VARIABLE INFORMATION LENGTH AND VARIABLE CODE RATE AND APPARATUS USING THE SAME - A method of generating a parity-check matrix of a low density parity-check (LDPC) code with a variable information length and a variable code rate, an encoding/decoding method, and an apparatus using the same are provided. The method of generating a parity-check matrix of an LDPC code includes: a first parity-check matrix generation process of generating a first parity-check matrix constructed with a first information block and a parity block; and an m-th parity-check matrix generation process of generating an m-th parity-check matrix by an m-th information block to a generated (m−1)-th parity-check matrix (1 | 12-23-2010 |

20100325512 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of code bits of an LDPC code such as burst errors or erasure. | 12-23-2010 |

20100325515 | CONTROLLING POINT-TO-MULTIPOINT TRANSMISSIONS OF CONTENT DATA OVER A RADIO INTERFACE - The invention relates to error control for point-to-multipoint (PTM) transmissions of content data over a radio interface. A method embodiment for controlling a PTM transmission in a PTM-enabled network comprises the steps of receiving and storing redundancy data at a dedicated redundancy data storage in a radio access network, wherein the redundancy data are provided for a correction of transmission errors in the content data resulting from the transmission of the content data without the redundancy data over one or more radio interfaces; receiving a request for redundancy data from a redundancy data control node; and responding to the redundancy data request by providing at least a portion of the redundancy data. | 12-23-2010 |

20100205505 | SYSTEMS AND METHODS FOR MESSAGE ENCODING AND DECODING - Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a selected characteristic according to a predetermined protocol, and changes to the data are recorded in a longitudinal check code (LCC) word, which is used by the receiver to decode the data message and restore the original data. | 08-12-2010 |

20120246538 | APPLICATION OF FOUNTAIN FORWARD ERROR CORRECTION CODES IN MULTI-LINK MULTI-PATH MOBILE NETWORKS - A method and apparatus are described including receiving content, applying fountain codes to symbols of the content to generate fountain encoded symbols at one of a transport layer and an application layer and transmitting the generated fountain encode symbols via a mobile network that uses a multi-link delivery system. Also described are a method and apparatus including receiving data packets of fountain encoded symbols via a mobile network that uses a multi-link delivery system, decoding the received data packets of fountain encoded symbols to content data, attempting to recover any corrupted content data and determining if the content data was recovered. | 09-27-2012 |

20130246880 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes. | 09-19-2013 |

20110246850 | Techniques To Control Power Consumption In An Iterative Decoder By Control Of Node Configurations - A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, receiving information regarding the iterative decoding, and based on the information controlling a number of nodes of the iterative decoder to enable during a next iteration of the iterative decoding. | 10-06-2011 |

20120042223 | FORWARD ERROR CORRECTION SCHEME FOR HIGH RATE DATA EXCHANGE IN A WIRELESS SYSTEM - A transmitter/receiver system for high data transfer in a wireless communication system includes a physical layer processor that comprises an FEC coder, a demultiplexer and a plurality of modem processors. The FEC coder applies error correction codes to the high data rate signal. Thereafter, the demultiplexer distributes portions of the coded high data rate signal to the modem processors. Each modem processor processes its respective portion of the coded signal for transmission in an independent channel. | 02-16-2012 |

20100162074 | APPARATUS AND METHOD FOR CODING QC-LDPC CODE - A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format includes: a parity bit generation unit configured to generate an arbitrary parity bit; a temporary parity bit generation unit configured to constitute the inputted information with circulants, and shift and combine the respective circulants at each row to generate a temporary parity bit; a corrected bit generation unit configured to generate corrected bits of parity bits by using an output of the temporary parity bit generation unit; and a parity bit correction unit configured to correct the temporary parity bit by reflecting an output of the corrected bit generation unit to the output of the temporary parity bit generation unit. | 06-24-2010 |

20110041032 | Hybrid Message Decoders for LDPC Codes - Two hybrid message decoders for low-density parity-check (LDPC) codes are proposed. One decoder uses a posteriori probability ratio (APPR) and a posteriori probability difference (APPD), and the other decoder uses a logarithm a posteriori probability ratio (LAPPR) and a logarithm a posteriori probability difference (LAPPD) as hybrid message. Since the variable node and check node processing can be readily done using APPR and APPD, respectively, the proposed decoders have lower complexity than the conventional decoder that uses LAPPR only as a message. | 02-17-2011 |

20110041028 | Systems and Methods for Retimed Virtual Data Processing - Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples | 02-17-2011 |

20110041029 | Method and System for Decoding Graph-Based Codes Using Message-Passing with Difference-Map Dynamics - A code to be decoded by message-passing is represented by a factor graph. The factor graph includes variable nodes indexed by i and constraint nodes indexed by a connected by edges for transferring messages m | 02-17-2011 |

20110126074 | TRANSPORT NETWORK SYSTEM WITH TRANSPARENT TRANSPORT AND METHOD OF OPERATION THEREOF - A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy. | 05-26-2011 |

20090327832 | DECODER AND RECORDING/REPRODUCING DEVICE - A decoder and recording/reproducing device for preventing an increase in power consumption, has a multi-step iterative decoder. The decoder includes an iterative decoder in which a decoder constituted by a channel decoder and an outer code decoder is installed in multiple steps; an iterative decoding control circuit which estimates an error symbol count after decoding using likelihood information obtained from the outer decoder, stops the interactive decoding, if the estimated error symbol count exceeds an error symbols count, and corrects the residual errors that can be corrected by ECC using the ECC decoder. Therefore if a multi-step iterative decoder is used, the number of times of iterative decoding can be decreased and low power consumption can be implemented. | 12-31-2009 |

20110083051 | INTERLEAVED CORRECTION CODE TRANSMISSION - An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units. | 04-07-2011 |

20110087946 | LOW COMPLEXITY FINITE PRECISION DECODERS AND APPARATUS FOR LDPC CODES - In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented. | 04-14-2011 |

20100064196 | DATA PROCESSING SYSTEMS AND METHODS FOR LOADING DATA FROM NON VOLATILE MEMORY TO A MEMORY - A data processing method for loading data from a non volatile memory to a memory is disclosed. A template data and a data block corresponding thereto in the non volatile memory are loaded to a buffer. A reference value of the template data and a corresponding reference value of the data block are compared to determine whether the reference value and the corresponding reference value are matched. If not, a modification algorithm is performed to adjust the data format of the loaded data block based on the reference value of the template data. Then, system related information is generated and stored to the memory according to data in the template data and the adjusted data block in the buffer. | 03-11-2010 |

20100180178 | Minimal hardware implementation of non-parity and parity trellis - Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis. | 07-15-2010 |

20120173948 | APPARATUS AND METHOD FOR CHANNEL ENCODING AND DECODING BASED ON LOW-DENSITY PARITY CHECK CODE IN MULTIPLE ANTENNA COMMUNICATION SYSTEM - Methods and apparatuses are provided for achieving maximum diversity gain through channel coding based on a Low-Density Parity-Check (LDPC) code in a multiple antenna communication system. A method includes determining a parity-check matrix; generating a codeword using the parity-check matrix; puncturing a part of an information word; dividing a parity into a plurality of partial parities based on a number of transmit antennas; transmitting an unpunctured part of the information word and a partial parity over a first antenna; and transmitting at least one other partial parity over at least one other transmit antenna. | 07-05-2012 |

20110258509 | Multi-Level Signal Memory with LDPC and Interleaving - Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed, | 10-20-2011 |

20100058140 | CHECK-MATRIX GENERATING METHOD, ENCODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND ENCODER - A regular quasi-cyclic matrix is generated in which specific regularity is given to cyclic permutation matrices. A mask matrix capable of supporting a plurality of encoding rates is generated. A specific cyclic permutation matrix in the regular quasi-cyclic matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix with an LDGM structure is generated in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. | 03-04-2010 |

20140006895 | ERROR CORRECTION ENCODING METHOD, DECODING METHOD AND ASSOCIATED DEVICES | 01-02-2014 |

20090217132 | Parity Check Matrix Generation Method, Data Transmission System, Encoding Device, Decoding Device, and a Parity Check Matrix Generation Program - A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor ( | 08-27-2009 |

20090217130 | METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES - A method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code is provided. The method includes determining a number of parity bits for puncturing; dividing the parity bits at predetermined intervals, and determining a number of puncturing parity bits, which are subjected to puncturing within the predetermined intervals; determining a modulation scheme; determining positions of puncturing parity bits corresponding to the determined number of the puncturing parity bits within the predetermined intervals according to the modulation scheme; repeatedly performing puncturing on puncturing parity bits corresponding to the determined positions at the predetermined intervals; and transmitting remaining bits except for the punctured bits according to the modulation scheme. | 08-27-2009 |

20090217128 | Low complexity decoding of low density parity check codes - An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. Counts of the number of input weak and medium variable messages can be included in the determination of check node output messages. | 08-27-2009 |

20090217126 | GENERATION OF TANNER GRAPHS FOR SYSTEMATIC GROUP CODES FOR EFFICIENT COMMUNICATION - A computer implemented method of communicating includes receiving systematic group codes representative of one or more messages. A Tanner graph is used to decode such systematic group codes. A method of forming a communication decoder includes obtaining a dual code for a systematic group code, obtaining a Tanner graph from the dual code, and reducing vertex complexity of the Tanner graph to provide a decoding Tanner graph for the communication decoder. | 08-27-2009 |

20090217124 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 08-27-2009 |

20090217123 | Method and System for Encoding a Data Sequence - A communication method and a communication system including a first entity ( | 08-27-2009 |

20110154148 | SPECTRAL CONTENT BASED DECODING AND FREQUENCY OFFSET ESTIMATION - Methods and systems to identify a codeword associated with samples of a signal from spectral content of the samples, and to estimate a frequency offset from the spectral contents. The samples may correspond to a physical layer header of a data frame. Modulation may be removed from the samples in accordance with each of a plurality of modulation sequences, each sequence associated with a corresponding codeword. Power levels in spectral contents of the modulation-removed samples are examined to identify a peak power level indicative of a match between a modulation sequence and the samples. The corresponding codeword is identified as being associated with the header, and transmission parameters associated with the identified codeword are used to decode a corresponding frame. An estimated frequency offset may be determined from a frequency associated with the peak power level. | 06-23-2011 |

20100064195 | ENCODING AND DECODING A DATA SIGNAL AS A FUNCTION OF A CORRECTING CODE - The invention relates to correcting codes for encoding and decoding a data signal. A signal including data variables is coded into a signal including the data variables and parity variables. The encoding and decoding operations are based on a parity check matrix comprised of a systematic matrix and a parity matrix and having rows corresponding coefficients of parity equations and distributed into decoding windows of same size. In order to increase convergence of the iterative decoding, the elements of at least one column of the systematic matrix associated with a decoding window are “0s”, except for a single element which is a “1”. A data variable is only involved in one equation of the window and not involved in solving the equations of other windows as long as the solving of equations of the window is not achieved. | 03-11-2010 |

20100058141 | STORAGE DEVICE AND CONTROL DEVICE - A storage device stores identification information for identifying a pseudo-uncorrectable error sector, which is treated in a pseudo manner as a sector including an uncorrectable error, in the pseudo-uncorrectable error sector. The storage device further performs data processing on the sector by using the identification information stored in the sector. Moreover, the storage device stores log process information indicating whether an error log is registered in the pseudo-uncorrectable error sector in an error process related to the uncorrectable error that is treated to be included in a pseudo manner in the pseudo-uncorrectable error sector. In addition, the storage device performs data processing by using the log process information and the identification information. | 03-04-2010 |

20110252285 | Low Density Parity Check Encoding Method And Low Density Parity Check Encoder - A low density parity check (LDPC) encoding method and an LDPC encoder are provided. The LDPC encoding method includes generating a H matrix and a He matrix. The H matrix includes a first section (H1) matrix and a second section (H2) matrix. The He is based on a ratio of the H matrix and a zero matrix to a C matrix and a D matrix. The method further includes generating a H1row matrix columnwise for each of a plurality of input vectors based on the H1 matrix and generating parity vectors for each of the plurality of input vectors based on the H1row matrix. | 10-13-2011 |

20110083052 | METHOD AND SYSTEM FOR ENCODING AND DECODING LOW-DENSITY-PARITY-CHECK (LDPC) CODES - A method for encoding data, the method comprising: creating m parity bits from k data bits based on a parity-check matrix ( | 04-07-2011 |

20090044070 | SYSTEM AND METHOD FOR TRELLIS DECODING IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword. | 02-12-2009 |

20090044069 | TRANSMITTER APPARATUS AND MULTIANTENNA TRANSMITTER APPARATUS - A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. There are included an encoding part ( | 02-12-2009 |

20130086443 | ITERATIVE DECODING METHOD FOR ENCODED SIGNAL AND ITERATIVE DECODING APPARATUS FOR ENCODED SIGNAL - A iterative decoding method for iteratively carrying out a decoding process for an encoded segmented and signal transmitted in a plurality of (N | 04-04-2013 |

20110099449 | METHOD AND APPARATUS FOR FEC ENCODING AND DECODING - A method for Forward Error Correction (FEC) encoding in a transmitter, the method comprising: receiving a data stream from a data source; generating a first Forward Error Correction data for respective data block with a first block size of the data stream; and generating a second Forward Error Correction data for respective data block with a second block size of the data stream, wherein the second block size is different with the first block size and wherein the data blocks of the first block size form the data stream, and the data blocks with the second block size form the data stream. | 04-28-2011 |

20110107172 | DOCSIS MAC-PHY Downstream Convergence Layer - Techniques are provided herein for transmitting data across multiple carriers using Motion Picture Experts Group (MPEG) Transport Stream (TS) packet multiplexing. At a processing device coupled to at least one subscriber device data associated with the at least one subscriber device are received. The data are encapsulated into MPEG-TS packets, where the MPEG-TS packet headers identify a single data channel for the at least one subscriber device. The MPEG-TS packets are multiplexed across a plurality of radio-frequency (RF) carriers for transmission, and the MPEG-TS packets are transmitted using the plurality of RF carriers. Each of the plurality of RF carriers have the same RF modulation, use the same symbol rate, and are driven by the same clock such that the carriers are synchronous. Techniques are also provided recover the data at the subscriber device. | 05-05-2011 |

20140006894 | Systems and Methods for Enhanced Bit Correlation Usage | 01-02-2014 |

20110083054 | HIGH-RATE REVERSE-ORDER RUN-LENGTH-LIMITED CODE - A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control. | 04-07-2011 |

20120304035 | TRANSMISSION APPARATUS AND TRANSMISSION METHOD - In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna. | 11-29-2012 |

20110191649 | SOLID STATE DRIVE AND METHOD OF CONTROLLING AN ERROR THEREOF - The present general inventive concept relates to a solid state drive and a method of controlling an error thereof. A flash translation layer includes a parity managing module to correct errors. A block address of a storage medium including error data that can be recovered is managed through the parity managing module. Parity data of a block including error data is generated through the parity managing module. The generated parity data is managed through the parity managing module. The generated parity data can be stored in an assigned area of the storage medium. When data of a block managed by the parity managing module is not recovered by an error correction code unit, error data is recovered with reference to the generated parity data. | 08-04-2011 |

20110191648 | INFORMATION PROCESSING APPARATUS, INFORMATION TRANSMITTING METHOD, AND INFORMATION RECEIVING METHOD - A transmitting-side device and a receiving-side device are connected to each other with a parallel bus that carries transmit data and an error-correcting code based on this transmit data in parallel. The transmitting-side device includes a signal inversion unit for inverting a signal to be sent to the parallel bus. The receiving-side device includes a signal inversion unit for inverting a received signal from the parallel bus, and an error detection unit for performing error detection and error correction based on a signal output from the signal inversion unit. The signal inversion unit of the transmitting-side device inverts a signal to be sent to all bus lines of the parallel bus and the signal inversion unit of the receiving-side device inverts the signal received from the all bus lines, which enables the error detection unit to perform error check on the parallel bus. | 08-04-2011 |

20110078532 | METHOD AND SYSTEM FOR LOW-LATENCY TRANSFER PROTOCOL - A method and system for providing computer-generated output and in particular graphical output. The system includes a network configured to carry digital information. The system includes a server in communication with the network, the server configured to execute an application and a cloud engine module. The application provides a graphical output. The output capturing and encoding engine module is further configured to intercept the graphical output from the application on the server. The output capturing and encoding engine module is further configured to convert the graphical output into at least one of: graphical commands and video codec data. The output capturing and encoding engine module is further configured to transmit the converted output over the network. The system includes a client in communication with the server over the network, the client configured to execute a graphics and video decoding and rendering engine module. The graphics and video decoding and rendering engine module is configured to, responsive to receiving the transmitted converted output, rendering the graphical output. The graphics and video decoding and rendering engine module is configured to intercept graphics and video decoding and rendering inputs at the client. The graphics and video decoding and rendering engine module is configured to transmit the intercepted user inputs to the output capturing and encoding engine module. | 03-31-2011 |

20110072328 | NONVOLATILE MEMORY CONTROLLER WITH SCALABLE PIPELINED ERROR CORRECTION - A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface. | 03-24-2011 |

20100199142 | ENCODING SCHEME, AND A DECODING SCHEME USING A SERIES OF LDPC CODES BASED ON FINITE INVERSIVE SPACES - There is disclosed a method of creating an LDPC code that is defined by a parity-check matrix H. The parity-check matrix H is derived from a (0,1)-geometry which is induced by a finite inversive space. This inversive space has an order q where every circle in the inversive space contains exactly q+1 points, q is preferably even, and most preferably equal to 2. Where the inversive space has a dimension n. Where the (0,1)-geometry is formed as a derived geometric structure based on pencils of degree m≦n in the inversive space. The method includes construction of a binary K by N matrix H labelled by K circles and N pencils of the inversive space, wherein the (i, j)-entry of the matrix is 1 if circle i belongs to pencil j, and 0 otherwise. If the degree of the pencil is given by 2 then the parity-check matrix H needs to be transposed, i.e. H | 08-05-2010 |

20100325513 | INTEGRATED CONTROL ELECTRONICS (ICE) FOR A HOLOGRAPHIC STORAGE SYSTEM - Integrated control electronics for a holographic storage system that is adapted for controlling read/write logic in a holographic storage device. The control electronics may control beam steering devices, SLM devices, shutters, optical sensor arrays and lasers. | 12-23-2010 |

20100325516 | SYMBOL ENCODING FOR TOLERANCE TO SINGLE BYTE ERROR - The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol. | 12-23-2010 |

20100281328 | HIGH SPEED LOW DENSITY PARITY CHECK CODES ENCODING AND DECODING - Certain aspects of the present disclosure relate to a method for generating a single rate or multi-rate highly structured low density parity check, encoding a data stream with the generated LDPC matrix for transmission in a wireless communication system, and for efficient LDPC decoding at a receiver. | 11-04-2010 |

20100275093 | Secure Communication Using Error Correction Codes - Systems and methods for selecting a puncturing pattern for a low density parity check (LDPC) code are disclosed. One such method comprises: selecting a puncture pattern distribution for the LDPC code; calculating a security threshold and a reliability threshold for the LDPC, the LDPC having the selected puncture pattern distribution and also described by a degree distribution; storing the selected puncture pattern distribution responsive to a security gap for the LDPC being a lowest value encountered in any prior iterations; selecting another puncture pattern distribution for the LDPC code; and repeating the calculating, the storing, and the selecting another puncture pattern distribution steps. | 10-28-2010 |

20100269009 | ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD - There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder ( | 10-21-2010 |

20100269007 | DIGITIZED RADAR INFORMATION REDUNDANCY METHOD AND SYSTEM - The present invention relates to a real time radar data transmission system and process for transmitting forward error correctable data to a plurality of parallel communication channels. | 10-21-2010 |

20140325303 | Systems and Methods for Protected Data Encoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets. | 10-30-2014 |

20120204076 | Broadcasting of digital video to mobile terminals - A method for communication includes encoding data using at least one Error Correction Code (ECC) to generate first and second output data streams. The first output data stream is processed to generate a first output signal, which has a first acquisition time. The second output data stream is processed to generate a second output signal, which has a second acquisition time that is smaller than the first acquisition time. The first and second output signals are transmitted simultaneously over a communication channel. | 08-09-2012 |

20090204868 | METHOD AND APPARATUS FOR SIGNAL TRANSMISSION/RECEPTION IN A COMMUNICATION SYSTEM USING AN HARQ SCHEME - An apparatus and method for transmitting a signal in a communication system using a Hybrid Automatic Repeat reQuest (HARQ) scheme are provided. The method includes generating a codeword vector by encoding an information vector by using a first parity check matrix of Low Density Parity Check (LDPC) codes, generating a transmission vector by processing the codeword vector, and transmitting the transmission vector. When the first parity check matrix includes a plurality of square matrix columns, each square matrix includes a size of L×L, the first parity check matrix is one of p parity check matrixes stored in the signal transmission apparatus, the p parity check matrixes support different numbers of information vector square matrix columns, and each of the numbers of information vector square matrix columns indicates the number of square matrix columns corresponding to the information vector from among the plurality of square matrix columns. The first parity check matrix is a parity check matrix supporting the number of information vector square matrix columns determined by using the length of the information vector and the value L from the p parity check matrixes, and the value L is determined by using p and the length of the information vector. | 08-13-2009 |

20100174963 | Method and device for decoding LDPC encoded codeworks with a fast convergence speed - The method includes defining from all the check nodes at least one group of check nodes mutually connected through at least one second variable node defining an internal second variable node. The method includes performing for each group the joint updating of all the check nodes of the group via a Maximum-A-Posteriori (MAP) type process, and the updating of all the first variable nodes and all the second variable nodes connected to the group except the at least one internal second variable node. The method may include iteratively repeating the updates. | 07-08-2010 |

20080320358 | Encoding and Decoding Method, and Encoding and Decoding Devices with a Two-Stage Error Protection Process - An encoding method for a series of data packets transmitted in the framework of a combined streaming and downloading application by a two-stage error protection process and only one unidirectional transmission channel. According to said method, a partial block of successive data packets is protected against at least some of the transmission errors occurring during streaming with the aid of a first error protection process while all data packets are protected against the transmission errors remaining after streaming is completed with the aid of a second error protection process. In a decoding method by which a series of data packets that are encoded according to the encoding method are decoded. Also disclosed is an encoding and decoding device for carrying out the method. | 12-25-2008 |

20150039959 | METHOD FOR DECODING A CORRECTING CODE WITH MESSAGE PASSING, IN PARTICULAR FOR DECODING LDPC CODES OR TURBO CODES - A method for iteratively decoding a word of a correcting code by an iterative decoding algorithm in the course of which, for each bit of said code word, at least one extrinsic information item is generated at each iteration, includes the following steps: an initial step of decoding by means of said iterative decoding algorithm; simultaneously, for each bit of said code word, a step of developing a criterion representing the number of oscillations of at least one extrinsic information item or of one extrinsic information item with regard to another extrinsic information item; if the decoding does not converge; a step of modifying the value of the bit of said code word for which said number of oscillations is highest; and, an additional step of decoding said at least one modified code word by means of said iterative decoding algorithm. | 02-05-2015 |

20090083605 | RADIO COMMUNICATION APPARATUS - A radio communication apparatus of the present invention aims at improving an error rate characteristic in the end receiver. A repeater (radio relay device) RS | 03-26-2009 |

20110161771 | METHOD AND APPARATUS FOR PROVIDING RESOURCE UNIT BASED DATA BLOCK PARTITION - A method of providing resource unit based data block partitioning may include determining, for a bit stream to be encoded in a coding scheme including an upper layer coding and a physical layer coding, whether upper layer coding is enabled. The method may further include, in response to the upper layer coding being enabled, partitioning the bit stream into one or more blocks for forward error correction coding. The one or more blocks may have a block size determined based on a size of a resource unit. The resource unit size may correspond to one or more units predefined in the physical layer for the resource allocation. A corresponding apparatus is also provided. | 06-30-2011 |

20110161770 | LOW DENSITY PARITY CHECK CODEC AND METHOD OF THE SAME - The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced. | 06-30-2011 |

20100192038 | CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR MULTIPLE-INPUT MULTIPLE-OUTPUT CHANNELS - Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality of parallel accumulation engines, a number of the plurality of parallel accumulation engines equal to M, accumulating a first information bit at a first set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. | 07-29-2010 |

20110047434 | WIRELESS COMMUNICATION OF TURBO CODED ATSC M/H DATA WITH TIME DIVERSITY - In an ATSC M/H wireless broadcast system, data for transmission is turbo encoded into turbo-encoded data blocks. The turbo-coded data blocks are processed for transmission by scheduling a plurality of portions of the block for transmission during respectively corresponding transmit intervals that are temporally separated from one another. The portions of the turbo-encoded blocks may then be transmitted during the respectively corresponding transmit intervals according to the schedule. The turbo-encoded blocks may be interleaved before portions of the blocks are scheduled for transmission. | 02-24-2011 |

20110047433 | SYSTEM AND METHOD FOR STRUCTURED LDPC CODE FAMILY WITH FIXED CODE LENGTH AND NO PUNCTURING - A family of low density parity check (LDPC) codes is generated based on a mother code having a highest code rate. The low density parity check (LDPC) codes include a codeword size of at least 1344. The LDPC codes also include a plurality of parity bits in a lower triangular form. The mother code is constructed by: selecting m number of rows and n number of columns; setting maximum column weights and row weights; designing a protograph matrix based on the set column weights and row weights and selected m and n; and selecting circulant blocks based on the protograph matrix. | 02-24-2011 |

20110047432 | APPARATUS AND METHOD FOR CODING IN COMMUNICATION SYSTEM - Disclosed is a method and apparatus for coding in a communication system. The coding method includes generating an information codeword vector from an information vector, generating a first vector in the information vector from an information part of a parity check matrix, generating a first parity codeword vector by performing an exclusive OR operation of the first vector and a second vector corresponding to a cyclically shifted version of the first vector, and generating a second parity codeword vector by performing an exclusive OR operation of the first vector, the first parity codeword vector, and a third vector. The third vector is a cyclically shifted version of a vector resulting from the exclusive OR operation of the first vector, the first parity codeword vector, and a fed-back third vector. | 02-24-2011 |

20100192037 | RADIO COMMUNICATION APPARATUS AND REDUNDANCY VERSION TRANSMISSION CONTROL METHOD - Optimal error rate performance can always be obtained and the number of retransmissions can be minimized in IR-type HARQ using an LDPC code as an error correction code. An LDPC encoding section | 07-29-2010 |

20100192036 | SYSTEMS AND METHODS FOR EFFICIENT LOW DENSITY PARITY CHECK (LDPC) DECODING - A system for low density parity code decoding according to one embodiment includes a plurality of variable node (vnode) logic modules for sequentially processing groups of vnode values associated with a codeword and outputting updated vnode values; a vnode memory for storing the vnode values and updated vnode values; a plurality of check node (cnode) logic modules for sequentially processing groups of cnode values and outputting updated vnode values; a cnode memory for storing the cnode values and updated cnode values; and logic for checking the codeword using the updated vnode values and the updated cnode values. Additional systems and methods are also presented. | 07-29-2010 |

20120311398 | EFFICIENT SOFT VALUE GENERATION FOR CODED BITS IN A TURBO DECODER - Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums. | 12-06-2012 |

20120311397 | METHOD FOR DETERMINING TRANSPORT BLOCK SIZE AND SIGNAL TRANSMISSION METHOD USING THE SAME - A method and device for determining a size of a transport block based on modulation and coding related information, and resource information. | 12-06-2012 |

20120311396 | MRAM FIELD DISTURB DETECTION AND RECOVERY - A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error. | 12-06-2012 |

20120311395 | STORING PORTIONS OF DATA IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module generating preliminary dispersed storage network (DSN) storage information for data to be stored in a DSN. The method continues with the DS processing module accessing DSN storage information regarding other data stored in the DSN and comparing the preliminary DSN storage information for the data with the DSN storage information regarding the other data. When at least a portion of the data has compatible preliminary DSN storage information with DSN storage information of at least a portion of the other data, the method continues with the DS processing module generating DSN storage information for remaining portions of the data to produce remaining portions DSN storage information and generating DSN storage information for the data based on the DSN storage information of the at least the portion of the other data and the remaining portions DSN storage information. | 12-06-2012 |

20140013180 | CODING METHOD AND CODING DEVICE - The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1 | 01-09-2014 |

20110055655 | Hardware-Efficient Low Density Parity Check Code for Digital Communications - A network element receiving signals from the network over a communications channel via transceiver circuitry. The network element has a host interface for communicating to a host system, decoded signals corresponding signals received from the network. Demodulator circuitry demodulates the signals into a data stream. Circuitry for decoding the data stream according to a sequence of operations is provided. The sequence of operations includes receiving a set of input values corresponding to input nodes of the macro parity check matrix. Estimating a check node value using values of other input nodes contributing to the parity check sum. Evaluating a probability value using the estimates of the check node values for that input node. The The operations are repeated until termination point is reached. | 03-03-2011 |

20090037790 | RECORDING METHOD AND REPRODUCTION METHOD SUITABLE FOR RECORDING/REPRODUCTION OF AV DATA, AND RECORDING DRIVE AND REPRODUCTION DRIVE, INFORMATION RECORDING SYSTEM AND INFORMATION REPRODUCTION SYSTEM, AND INFORMATION RECORDING MEDIUM FOR SUCH METHODS - In an information recording medium for recording and reproducing data thereon on a sector-by-sector basis, the recorded data being managed as at least one file by using a file structure, the file structure includes unused space management information for identifying a used region and an unused region. At least one defective region is registered as an unused region in the unused space management information, the at least one defective region being a region on the information recording medium which is incapable of proper reproduction of the recorded data. | 02-05-2009 |

20110258508 | Systems and Methods for Dynamic Scaling in a Data Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value. | 10-20-2011 |

20110264981 | ERROR CORRECTION DECODING BY TRIAL AND ERROR - A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. | 10-27-2011 |

20110264980 | Systems and Methods for Low Density Parity Check Data Decoding - Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight. | 10-27-2011 |

20100287440 | MATRIX STRUCTURE FOR BLOCK ENCODING - A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices. | 11-11-2010 |

20110041030 | STORAGE OF DATA AND SIGNATURE FORMED FROM DATA AND ADDRESS IN A MEMORY - A programmable device employs an address and data corruption logic for data written to a memory. A first signature is computed from the data stored in the memory and the address at which it is stored. The signature is stored with the data in the memory. When data is read from the memory, the first signature stored in the memory is also read and compared with a second signature computed from the data read from the memory and the address from which it is read. If the first and second signatures do not match, an error condition is indicated. | 02-17-2011 |

20140258802 | METHODS AND SYSTEMS FOR ENHANCED DETECTION OF E-NAVIGATION MESSAGES - Methods and systems for enhancing the detectability of maritime e-Navigation messages are provided. Transmitters apply error protection encoding to the payload portion of messages to be transmitted, which are wrapped in a standard e-Navigation message format such as that used by the Automatic Identification System. Transmitted messages are received by a satellite or other surveillance platform employing a compatible radio frequency receiver to collect message signals over a large area or great distance. Candidate messages are identified and the error protection encoding decoded to recover messages. | 09-11-2014 |

20110119554 | METHOD FOR TRANSMITTING NON-BINARY CODES AND DECODING THE SAME - The invention relates to a decoding method for non-binary codes, in particular non-binary LDPC codes, amenable to representation by a bipartite graph representing N variables and M constraints. The invention also relate to a transmission method for transmitting non-binary codes, in particular non-binary LDPC codes, and to a reception to receive the same. The invention can be applied in particular to an IR-HARQ or a cooperative network using a non-binary code, in particular a non-binary LDPC code. | 05-19-2011 |

20100185918 | Message-based management of variable-rate communication links - A method for communication includes transmitting data from a transmitter to a receiver using Adaptive Coding and Modulation (ACM). The data rate is set by selecting, based on feedback, an ACM profile defining a Forward Error Correction code and a modulation scheme. Upon detecting that the feedback is unusable, an operation of the transmitter is changed independently of the feedback. | 07-22-2010 |

20100122141 | METHOD AND SYSTEM FOR SENSING AVAILABLE BANDWIDTH OVER A BEST EFFORT CONNECTION - A bandwidth sensing system operates to sense the existence of additional bandwidth available for transmitting data over a best effort communication. The operations include receiving an original block of data from a transmitting node and calculating error correction data based on the original block of data. The original block of data and the error correction data is then transmitted toward a receiving node. The data may be simply appended or, the entire block may be modified during the error correction data process. When the original block of data and error correction data is received at the receiving end associated with the receiving node, the data is analyzed to determine if any errors occurred in the transmission. If so, the error correction data is used to maintain the integrity of the transmitted data by restoring the original block. However, if no errors are detected, because the error correction data inherently requires the transmission of additional data, the receiving end can conclude that additional bandwidth is available over the channel. Thus, the transmitting node can be notified of the available bandwidth so that additional bandwidth can be utilized on subsequent transmissions. | 05-13-2010 |

20110138248 | METHOD FOR ARRANGING MEMORIES OF LOW-COMPLEXITY LDPC DECODER AND LOW-COMPLEXITY LDPC DECODER USING THE SAME - A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption. | 06-09-2011 |

20110083053 | METHOD AND APPARATUS FOR CONTROLLING DISPERSED STORAGE OF STREAMING DATA - A method begins by a processing module determining properties of streaming data. The method continues with the processing module determining required dispersed storage resources based on the properties of the streaming data, identifying a plurality of sets of dispersed storage resources, and establishing first error coding dispersed storage function parameters for a first set of dispersed storage resources of the plurality of sets of dispersed storage resources when the required dispersed storage resources requires the plurality of sets of dispersed storage resources. In addition, the method continues with the processing module enabling partitioning of the streaming data into a plurality of data streams and enabling routing of a first data stream of the plurality of data streams to the first set of dispersed storage resources, wherein the first set of dispersed storage resources converts the first data stream into pluralities of error coded data slices. | 04-07-2011 |

20140344640 | Interactive Event Cast to Multiple Mobile Devices - Systems and devices for, and methods of, interactive event casting, by: (a) scheduling a plurality of transactions, where the scheduling may be based on passing a system time and a channel usage schedule; (b) aggregating the plurality of transactions, where the aggregating results in minimizing data transfer traffic; (c) executing a data compression and error correction scheme, where the data compression scheme may be based on dynamically changing bitrate of a video data stream according to local access point data traffic; and (d) communicating between network devices using multi-cast for compressed video streams with error-correction code and (e) initiating an application, where the initiated application performs error correction, decompresses the received video data stream, and where the decompressed video data stream may be spooled. | 11-20-2014 |

20110197105 | ENCODER, TRANSMISSION DEVICE, AND ENCODING METHOD - Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit ( | 08-11-2011 |

20130111289 | SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING | 05-02-2013 |

20110264979 | ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 10-27-2011 |

20090100313 | METHODS AND APPARATUSES OF MATHEMATICAL PROCESSING - Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols. | 04-16-2009 |

20090100312 | APPARATUS AND METHOD FOR DECODING LOW-DENSITY PARITY CHECK CODE - There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold. | 04-16-2009 |

20090100311 | Method of Constructing Low Density Parity Check Code, Method of Decoding the Same and Transmission System For the Same - The present invention relates to a method of constructing a low density Parity Check code, a method of decoding the same and a transmission system using the same. The method comprises steps of: constructing a low density Parity Check matrix of the low density Parity Check code by using a fixed pattern; blocking data sent from an information source ( | 04-16-2009 |

20090106622 | RECEIVING APPARATUS AND METHOD AND PROGRAM - A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding. | 04-23-2009 |

20090177939 | Method for Coding Biometric Data, Method for Controlling Identity and Devices for Carrying Out said Methods - The invention relates to a coding method consisting of the following steps: biometric data associated with an individual is obtained; a word, relating to an error correction code, selected in older to correct a quantity of errors in a relation to a statistical quantity of errors between two biometric measurements relating to the same individual, is generated, said word dissimulating information relating to said individual with the aid of a private function; and a combination is created between the biometric data thus obtained and the word thus generated. | 07-09-2009 |

20100031113 | METHOD AND APPARATUS OF CANDIDATE LIST AUGMENTATION FOR CHANNEL CODING SYSTEM - The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems. | 02-04-2010 |

20100031118 | Accumulating LDPC (Low Density Parity Check) decoder - Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 02-04-2010 |

20100031117 | Method for specifying transport block to codeword mapping and downlink signal transmission method using the same - A method for specifying a transport block-to-codeword mapping relationship and a method for transmitting a downlink signal using the same are described. If a swap flag has a first logic value, a first transport block is mapped to a first codeword and a second transport block is mapped to a second codeword. If the swap flag has a second logic value, the first transport block is mapped to the second codeword and the second transport block is mapped to the first codeword. If the size of any one of two transport blocks is 0, the swap flag is not used. | 02-04-2010 |

20100031116 | METHOD FOR ENCODING LOW DENSITY PARITY CHECK CODES USING RESULT OF CHECKING PREVIOUSLY SPECIFIED PARITY BITS - There is provided to a method for encoding an LDPC (Low Density Parity Check) code using the result of checking a previously specified parity, including the steps of: forming a parity bit check matrix having a dual diagonal structure consisting of (N-K) rows for check nodes and (N-K) columns on the basis of the H matrix; calculating the values of all the parity bits by inserting a given binary value in sub-blocks, with the parity bit check matrix formed on the H matrix; if the values of the parity bits are incorrect, checking the parity bit corresponding to the sub-block located in the last part of the H matrix; searching the parity bit parts where the parity bit check result is represented as “1”; performing an XOR operation in sub-blocks on the parity bit part obtained through a simultaneous equation between the parity bits of the searched parity bit parts and the parity bit parts; and determining the value of the parity bit satisfying the condition that the value obtained by multiplying the H matrix by a code word vector. | 02-04-2010 |

20100031115 | LOW DENSITY PARITY CHECK DECODER USING MULTIPLE VARIABLE NODE DEGREE DISTRIBUTION CODES - A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations. | 02-04-2010 |

20100031114 | LOW DENSITY PARITY CHECK (LDPC) DECODER USING BROADCAST MESSAGING - In a decoder implementing a belief propagation algorithm for iteratively decoding a Low Density Parity Check (LDPC) encoded data block, a method of computing messages to be sent by a first node of the decoder to at least one neighbour node of the decoder. The method comprises: processing messages received by the first node to remove an echo of a previous message sent by the first node to the at least one neighbour node in a previous iteration, to yield corresponding modified messages; computing a message for a current iteration using the modified messages; and broadcasting the computed message for the current iteration to each of the at least one neighbour nodes. | 02-04-2010 |

20100031112 | Method and device for determining indices assigned to correction symbols - A determination of indexes allocated to error correcting symbols is provided. Encoded code symbols are generated by means of a generator matrix of a block code from number of source symbols and the encoded transmission errors occur in the received code symbols, the indexes of the error correcting symbols are determined by unambiguously identifying the area of the encoded code symbols by means of first and second parameters, which can be requested in the form of at least one error correcting symbol by the receiving device from the transmitting device for reconstructing the source symbols in an error-free manner. | 02-04-2010 |

20130111291 | Low Complexity and Power Efficient Error Correction Coding Schemes | 05-02-2013 |

20090094500 | Dynamic generator of unique world wide numbers - A method and system generates World Wide Numbers for devices and LUNs which are not provided with such number. The method extracts from the devices of information data which when treated in combination is device unique. A CRC is then generated using the combination of information data. The bit length of the CRC is selected to match the WWN standard required and the CRC is used in the WWN in place of vendor. | 04-09-2009 |

20120144260 | Apparatus and Method for Detecting an Error Within a Coded Binary Word - An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word. | 06-07-2012 |

20090172494 | DATA PROCESSING APPARATUS AND METHOD, AND PROGRAM - In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector. | 07-02-2009 |

20090172493 | METHOD AND DEVICE FOR DECODING LOW DENSITY PARITY CHECK CODE - An apparatus for decoding a Low Density Parity Check (LDPC) is provided. The apparatus includes a variable node message memory for storing a variable node message vector, a controller for controlling a node computing unit to read from and write to the variable node message memory and controlling an iteration process for the apparatus, and a node computing unit for updating a check node message and a variable node message, and determining a hard decision message, the node computing unit includes a variable node message generation unit for determining the variable node message for use in a check node message calculation unit according to the variable node message vector, a check node message calculation unit for updating the check node message, a variable node message updating unit for updating a corresponding variable node message, a hard decision calculation unit for determining the hard decision message for a corresponding variable node, and a parity check unit for determining a parity bit and outputting the parity bit to a decoding termination controller. | 07-02-2009 |

20130254618 | PADDING AFTER CHANNEL ENCODING REPETITION AND INTERLEAVING - Described herein are techniques related to the generation of data blocks that collectively include padding appended before a first or after a last of the data blocks. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 09-26-2013 |

20130254616 | Systems and Methods for Variable Rate Coding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system. | 09-26-2013 |

20100318876 | DECODING DEVICE, DECODING METHOD, DECODING PROGRAM, RECEPTION DEVICE, AND COMMUNICATION SYSTEM - A decoding device which decodes error correction coded information by iterating a decoding process. The decoding device includes an iteration quantity determination unit which calculates a mutual information indicating a relationship with transmission information of the coded information and determines the number of iterations of the decoding process based on the calculated mutual information. | 12-16-2010 |

20150046766 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |

20130139022 | Variable Sector Size LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data. | 05-30-2013 |

20090187804 | LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems - LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11 | 07-23-2009 |

20120210188 | HANDLING CORRUPTED BACKGROUND DATA IN AN OUT OF ORDER EXECUTION ENVIRONMENT - Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected. | 08-16-2012 |

20100115370 | METHOD AND APPARATUS FOR ERROR CONCEALMENT OF ENCODED AUDIO DATA - A method of frame error concealment in encoded audio data comprises receiving encoded audio data in a plurality of frames; and using saved one or more parameter values from one or more previous frames to reconstruct a frame with frame error. Using the saved one or more parameter values comprises deriving parameter values based at least part on the saved one or more parameter values and applying the derived values to the frame with frame error. | 05-06-2010 |

20120047414 | ADDRESS GENERATION APPARATUS AND METHOD FOR QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER - An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f | 02-23-2012 |

20120005553 | TRANSMITTING APPARATUS AND TRANSMISSION METHOD - A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit. | 01-05-2012 |

20120005551 | BREAKING TRAPPING SETS USING TARGETED BIT ADJUSTMENT - In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial. | 01-05-2012 |

20120210189 | ERROR CORRECTION ENCODING METHOD AND DEVICE, AND COMMUNICATION SYSTEM USING THE SAME - An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively. | 08-16-2012 |

20090049359 | CIRCULAR BUFFER BASED RATE MATCHING - Systems and methodologies are described that facilitate employing circular buffer based rate matching. Encoded block(s) that include systematic, parity 1, and parity 2 bits can be generated using turbo code. Bit type can be identified to separate bits into distinct groups. Systematic bits can be interleaved together to generate a randomized sequence of systematic bits, parity 1 bits can be interleaved together to yield a randomized sequence of parity 1 bits, and parity 2 bits can be interleaved together to output a randomized sequence of parity 2 bits. The randomized sequences of parity 1 bits and parity 2 bits can be interlaced together in an alternating manner. The randomized sequence of systematic bits can be inserted into a circular buffer, and upon inserting the entire sequence, the interlaced parity bits can be inserted into the circular buffer (e.g., until reaching capacity). Bits inserted into the circular buffer are transmitted. | 02-19-2009 |

20130346823 | ENCODING OF DATA FOR TRANSMISSION - A data encoding method for encoding a sequence of N input blocks of bits into an output block for transmission includes adding an L-bit control indicator, indicating whether the sequence contains any control blocks, and if so, producing an output block in which the order of data and control blocks is preserved by deleting a set of bits from the block-type field of at least one control block, adding to the sequence an N-bit position indicator indicating positions of data and control blocks in the sequence, and providing in bit positions of remaining bits of the block-type field of the at least one control block an indication of the type of that control block; wherein the position indicator bits are added at bit-positions such that, in a header-first transmission order of the output block, all data and control blocks succeed the position indicator bits indicating positions of those blocks. | 12-26-2013 |

20130339817 | UPDATING VARIABLE NODES ASSOCIATED WITH AN ITERATIVE DECODER - Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for data decoding and/or error correction. In various embodiments, an iterative decoder may compute, from sign bits of log likelihood ratios associated with x bits of a plurality of bits of encoded data, a first combination of the x bits having a higher associated log density ratio than any other combination of the x bits. In various embodiments, the iterative decoder may further be configured to compute m combinations of the x bits having m highest associated log density ratios, based on reductions in log density ratios associated with one or more sub-combinations of the x bits and the computed first combination of the x bits. In various embodiments, a variable node associated with the iterative decoder may be updated with the m combinations of the x bits. Other embodiments may be described and/or claimed. | 12-19-2013 |

20130339814 | Method for Processing Messages for Outsourced Storage and Outsourced Computation by Untrusted Third Parties - A message is stored and processed by an untrusted third party by generating a codeword using a selected one of a set of error correcting codes (ECC). The selected ECC depends on a weight rate of the block, and each codeword satisfies a minimum distance criterion with respect to the codewords of all possible ECCs and all possible weight rates. Each symbol of the codeword is modifying explicitly, randomly and independently according to parameters of a channel to obtain a randomized codeword. Then, an encoded result of an operation performed on the randomized codeword by the untrusted third party is decoded. | 12-19-2013 |

20120117439 | System and method of decoding LDPC code blocks - A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved. | 05-10-2012 |

20140201588 | Low density parity check (LDPC) coding in communication systems - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 07-17-2014 |

20140281785 | ERROR-CORRECTION DECODING WITH CONDITIONAL LIMITING OF CHECK-NODE MESSAGES - An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method may include determining whether participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation. The method may further include determining, based on whether the particular parity-check equation is satisfied, a magnitude of a reliability modification to one or more reliability values associated with at least one of the participating bits. The method may also include modifying the one or more reliability values by the magnitude of the reliability modification. | 09-18-2014 |

20130111292 | SEMICONDUCTOR MEMORY DEVICE AND DECODING METHOD | 05-02-2013 |

20110225474 | METHOD AND APARATUS FOR ERASURE DECODING AN ECC CODED BITSTREAM - The error correction capability of block codes can be doubled if error locations are known. Prior art approaches for error location detection always involve adding dedicated redundant data which then are evaluated to yield error location information. The present invention proposes and describes how error location information in the form of clues is derived from given DC control bits that are anyway present in a data stream. | 09-15-2011 |

20090172492 | Method and apparatus for interleaving low density parity check (LDPC) codes over mobile satellite channels - Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions. | 07-02-2009 |

20110119553 | SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices. | 05-19-2011 |

20130073920 | IMPLEMENTATION-ORIENTED METHOD OF BICM BASED ON LDPC CHECK MATRIX - An IMPLEMENTATION-ORIENTED METHOD of Bit Interleaved Coded Modulation (BICM) based on a Low-Density Parity-Check (LDPC) check matrix including constructing an LDPC code having a block check matrix or providing an existing LDPC, where the block check matrix is divided into one or more sub-matrixes H | 03-21-2013 |

20140258803 | Forward Error Correction (FEC) to Support Successive Interference Cancellation (SIC) - Forward Error Correction (FEC) techniques that generate independently decodable resource blocks are beneficial for Successive Interference Cancellation (SIC) demodulation. One FEC technique for generating independently decodable resource blocks includes mapping locally decodable FEC codeblocks into unique resource blocks such that substantially all of the bits of the FEC codeblock are carried within a single resource block. The locally decodable FEC codeblocks can be generated from different FEC encoding modules or from a common FEC encoding module. Another technique for generating independently decodable resource blocks includes encoding a stream of information bits into low-density parity-check (LDPC) codeblocks having high ratios of inward peering parity bits. These high ratios of inward peering parity bits allow substantial portions of each LDPC codeblock to be decoded independently from information carried by other LDPC codeblocks. | 09-11-2014 |

20100185912 | APPARATUS AND METHOD FOR PROCESSING OPTICAL INFORMATION USING LOW DENSITY PARITY CHECK CODE - An apparatus and method for processing optical information using a low density parity check code are suggested. An optical information recording method includes the steps of encoding data to record into a low density parity check code; representing the data, which is encoded into the low density parity check code, to a spatial light modulator in the unit of a data page; and modulating a recording beam into the data page representing the spatial light modulator to be recorded in the form of hologram in a recording medium. By blocking inexact probability information from being concentrated in the LDPC code block, by achieving exact probability information through effective allocation of a mark, and by improving average accuracy of the pixel, which corresponds to the LDPC code, failure rate of decoding can be minimized so that decoding performance can be improved. | 07-22-2010 |

20140047295 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. | 02-13-2014 |

20130061108 | Self-Repair System and Method - The present invention discloses a self-repair system for three-dimensional mask-programmed read-only memory (3D-MPROM). Most of the 3D-MPROM data are not checked in the factory, but checked and repaired in the field. This self-repair system comprises a playback device with a re-writable memory (RWM). The RWM temporarily stores new contents. After a user receives a 3D-MPROM card storing the same contents, the playback device checks the 3D-MPROM data. When bad data are detected, the good data to replace the bad data are fetched from the RWM. | 03-07-2013 |

20100174965 | LDPC CODES WITH SMALL AMOUNT OF WIRING - The embodiments herein relate to Low Density Parity Check (LDPC) codes, their corresponding matrices, and with an LDPC decoder architecture used to decode those codes. Embodiments herein relate to methods to generate a set of LDPC codes (typically of different rates) that share their wires as much as possible and therefore reduce the silicon area and ease the routing. | 07-08-2010 |

20100122140 | Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices - Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code. | 05-13-2010 |

20110078533 | SERIAL CONCATENATION OF TRELLISCODED MODULATION AND AN INNER NON-BINARY LDPC CODE - A concatenated coded modulation communication system and method combines Trellis Coded Modulation with non-Gray code constellation mapping, interleaving, and non-binary Low Density Parity Check coded channel modulation with Gray code constellation mapping to improve error performance. | 03-31-2011 |

20110107175 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 05-05-2011 |

20130013973 | LOW DENSITY PARITY CHECK (LDPC) CODE - Example methods are disclosed for decoding low-density parity-check (LDPC) encoded data, involving applying an expanded parity check matrix to generate decoded data, wherein −1 represents an 81×81 all-zero square matrix, and any other integer, S | 01-10-2013 |

20100153814 | METHOD BASED ON ERROR CORRECTOR CODES, APPLICABLE TO A VARIABLE RATE MULTIMEDIA DATASTREAM - A method and apparatus are provided for creating a matrix for correcting errors of transmission of multimedia data packets at a non-constant rate between a sender terminal and at least one receiver terminal. The multimedia data packets constitute elements of the correction matrix. The correction matrix has dimensions that are determined as a function of a maximum rate of the multimedia data packets at the input of the sender terminal, and the multimedia data packets are placed in the correction matrix at regular time slots. A noted absence of any multimedia data packets for a given time slot is represented in the correction matrix by an empty location. | 06-17-2010 |

20100153813 | COMMUNICATION METHOD AND APPARATUS USING LDPC CODE - An encoding method using a Low Density Parity Check (LDPC) matrix having a codeword length of N and an information word length K is provided to improve coding efficiency, and includes generating a first parity bit vector ( | 06-17-2010 |

20100153812 | METHODS AND APPARATUS FOR ENCODING LDPC CODES - Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph. | 06-17-2010 |

20100153811 | METHOD FOR DECODING USING DYNAMIC SCHEDULING SCHEME FOR LOW DENSITY PARITY CHECK CODES AND APPARATUS THEREOF - Disclosed is a decoding method and device for low density parity check codes using dynamic scheduling. The low density parity check codes are sequentially decoded, and the messages are scheduled in the descending order of the difference between values before and after updating the message transmitted from the variable node to the check node. | 06-17-2010 |

20100153810 | DECODING DEVICE AND RECEIVING DEVICE - A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations. | 06-17-2010 |

20110131465 | SETS OF RATE-COMPATIBLE UNIVERSAL TURBO CODES NEARLY OPTIMIZED OVER VARIOUS RATES AND INTERLEAVER SIZES - A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code. The Turbo Codes have rate-compatible puncturing patterns. The method comprises: encoding a signal at a first and second encoder using a best rate 1/2 constituent code universal with higher code rates, the first encoder and the second encoder each producing a respective plurality of parity bits for each information bit; puncturing the respective plurality of parity bits at each encoder with a higher rate best puncturing patterns; and puncturing the respective plurality of parity bits at each encoder with a lower rate best puncturing pattern. In a variation, the best rate 1/2 constituent code represents a concatenation of polynomials 1+D | 06-02-2011 |

20110131462 | MATRIX-VECTOR MULTIPLICATION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector. | 06-02-2011 |

20110004803 | EXECUTION DECISION APPARATUS, RECEIVING APPARATUS, RADIO COMMUNICATION SYSTEM, AND EXECUTION DECISION METHOD - An execution decision apparatus decides whether to execute a detection process for a turbo equalization apparatus which detects data before coding, by repeating processes performed on transmission data coded by error correction coding, by an equalization unit for compensating distortion by a propagation path and a decoding unit for performing an error correction process, and includes an equalization unit I/O characteristic acquisition unit which acquires an I/O characteristic of the equalization unit; a decoding unit I/O characteristic acquisition unit which acquires an I/O characteristic of the decoding unit; and a decision unit which decides whether to execute the detection process in the turbo equalization apparatus based on the I/O characteristic acquired for each of the equalization unit and the decoding unit. | 01-06-2011 |

20110004802 | METHOD AND SYSTEM FOR CONTROL OF COMMUNICATION EQUIPMENT BASED ON A BIT ERROR RATE DERIVED FROM A FRAME ALIGNMENT SIGNAL - Consistent with the present disclosure, circuitry may be provided in an optical receiver that can determine a bit error rate (BER) associated with an incoming signal by dividing the number of errored bits in a frame alignment signals (FAS) by the number of bits in the FAS. Accordingly, although an optical signal may be severely degraded and forward error correction (FEC) cannot be performed, a BER may be obtained if the FAS can be identified. The BER can then be used in a feedback loop to control various optical or electrical components in the receiver to improve or reduce the BER to a level, for example, at which FEC can be performed. | 01-06-2011 |

20140310567 | TRANSMISSION APPARATUS INCLUDING ENCODER, RECEPTION APPARATUS INCLUDING DECODER, AND ASSOCIATED METHODS - An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence. | 10-16-2014 |

20140068371 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 03-06-2014 |

20140068368 | LDPC Decoder With Fractional Unsatisfied Check Quality Metric - The present inventions are related to systems and methods for calculating data quality metrics for an LDPC decoder, and particularly for calculating a fractional unsatisfied check quality metric. | 03-06-2014 |

20130262955 | DECODER, RECEIVING APPARATUS, DECODING METHOD, AND RECEIVING METHOD - Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. | 10-03-2013 |

20130262954 | REDUCING PROCESSING COMPLEXITY AND COST ASSOCIATED WITH A SOFT FORWARD ERROR CORRECTION (FEC) OPERATION - A system is configured to receive a word on which to perform forward error correction; identify least reliable positions that correspond to encoded bits, within the word, associated with a lowest level of reliability; generate candidate words based on different combinations of inverted encoded bits; identify a pair of candidate words that includes a candidate word and another candidate word, the candidate word includes an inverted most reliable bit of the encoded bits within the candidate word; identify a quantity of errors within the candidate word; determine whether the quantity of errors corresponds to an odd value; invert a parity bit associated with the candidate word when the quantity of errors corresponds to the odd value; select the other candidate word when the parity bit is inverted; and perform forward error correction, on the word, using the other candidate word based on selection of the other candidate word. | 10-03-2013 |

20130262953 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR DYNAMICALLY CONTROLLING A TURBO DECODING PROCESS IN A LONG TERM EVOLUTION (LTE) MULTI-USER EQUIPMENT (UE) TRAFFIC SIMULATOR - According to one aspect, the subject matter described herein includes a method for dynamically controlling a Turbo decoding process in a long term evolution (LTE) multi-user equipment (UE) traffic simulator. The method includes steps occurring in an LTE traffic simulator configured to simulate plural UE devices. The steps include receiving, from an evolved NodeB under test, a plurality of transport blocks. The steps also include dynamically determining a maximum number of Turbo decoding iterations for each of the transport blocks. The steps further include Turbo decoding each of the transport blocks for no more than its determined maximum number of Turbo decoding iterations. | 10-03-2013 |

20120173949 | METHOD OF CONSTRUCTING PARITY-CHECK MATRIX OF LDPC CODE AND ENCODING METHOD AND ENCODING APPARATUS BASED ON THE METHOD - The embodiments of the present invention provide a method of constructing parity-check matrix of LDPC code. The method comprises the following steps of: constructing a M | 07-05-2012 |

20120173947 | METHOD AND DEVICE FOR ENCODING SYMBOLS WITH A CODE OF THE PARITY CHECK TYPE AND CORRESPONDING DECODING METHOD AND DEVICE - A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N−K first nodes (NC | 07-05-2012 |

20120324309 | DECODING METHOD AND DECODING APPARATUS - A decoding device allowing a high-speed decoding operation. In a decoding section ( | 12-20-2012 |

20120324308 | WIRELESS COMMUNICATION SYSTEM, COMMUNICATION DEVICE, PROGRAM, AND INTEGRATED CIRCUIT - A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths. | 12-20-2012 |

20120324307 | Systems and Methods for Retimed Virtual Data Processing - Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. | 12-20-2012 |

20120266041 | SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER - The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another. | 10-18-2012 |

20120266040 | METHOD OF ERROR FLOOR MITIGATION IN LOW-DENSITY PARITY-CHECK CODES - A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude. | 10-18-2012 |

20120266039 | METHOD AND DEVICE FOR COMMUNICATING DATA ACROSS NOISY MEDIA - A method and a device for communicating data via noisy media in order to improve the protection against errors in the transmission of information via a noisy channel or transmission medium. The method and improved device involve using a new type of structure of the parity matrix for the low density parity check codes technology in the coding and decoding of data, which improves the correction of errors without increasing the complexity of the hardware implementation. | 10-18-2012 |

20100299574 | Systems and methods for LDPC coded modulation - Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error floor, no cycles, an equal bit error rate for the information bits and the parity bits, and timely construction of both a parity check matrix with variable codeword size and a generator matrix is possible. | 11-25-2010 |

20140068370 | CONVOLUTIONAL CODE ENCODING METHOD - An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. In the encoder ( | 03-06-2014 |

20140068369 | DIGITAL BROADCASTING SYSTEM AND DATA PROCESSING METHOD - According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups. | 03-06-2014 |

20120272118 | Variable modulation with LDPC (Low Density Parity Check) coding - Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. Variable modulation encoding of LDPC coded symbols is presented. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis. | 10-25-2012 |

20140143628 | Low Density Parity Check Decoder With Flexible Saturation - Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values. | 05-22-2014 |

20100275094 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY CONTROLLER - In a nonvolatile memory device of the present application, when data of each write unit is read from a nonvolatile memory, an all-clear detector detects whether the read data is already cleared, and a control portion judges whether a flag is already written into a written flag area of the data that has been descrambled by a descrambler and then corrected by an error detection and correction portion. Using a scramble pattern that is generated by a scramble pattern generator and corresponds to the written flag area, a predetermined bit pattern is scrambled to a state that differs from the cleared state. | 10-28-2010 |

20100275092 | SIGNAL PROCESSOR AND ERROR CORRECTION PROCESS - A signal processor, which includes: a signal receiving section for receiving signals encoded under a predetermined code rule; a rule violation detecting section for detecting code rule violation included in the signals received by the signal receiving section; an error range specifying section for specifying a range in which an error bit is included out of a bit string which constitutes the signals on the basis of a position of the code rule violation detected by the rule violation detecting section; and an error correcting section for correcting one error bit in the range specified by the error range specifying section so that the code rule violation detected by the rule violation detecting section is eliminated. | 10-28-2010 |

20100275090 | RADIO COMMUNICATION APPARATUS AND PUNCTURING METHOD - A radio communication apparatus is provided that enables degradation of error rate performance due to puncturing to be minimized when an LDPC code is used as an error correcting code. In this apparatus, a padding bit insertion section | 10-28-2010 |

20130007552 | DATA PROCESSING DEVICES, COMPUTER READABLE STORAGE MEDIA, AND METHODS - A data processing device including a controller configured to control the data processing device to execute steps of: receiving a data packet comprising a group identification information that identifies a restoration group, with which the data packet is associated, and redundant data for restoring a lost data packet, which is associated with the restoration group identified by the group identification information; determining whether a received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than a predetermined value; and restoring the lost data packet associated with the restoration group identified by the group identification information when the received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than the predetermined value. | 01-03-2013 |

20090089642 | LOW-DENSITY PARITY-CHECK (LDPC) ENCODER - The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder. | 04-02-2009 |

20120179948 | METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A BROADCASTING/COMMUNICATION SYSTEM USING LOW DENSITY PARITY-CHECK CODES - An apparatus and a method are provided for encoding and decoding in a broadcasting/communication system using a Low Density Parity Check (LDPC) code. A weight-1 position sequence conversion procedure is performed on an initial parity check matrix. Shortening is applied on an information word. A codeword is generated by LDPC encoding the information word using a parity check matrix generated by performing the weight-1 position sequence conversion procedure. Puncturing is then applied to the codeword. | 07-12-2012 |

20120254684 | RECEIVER AND RECEIVING METHOD FOR RECEIVING DATA IN A BROADCAST SYSTEM USING INCREMENTAL REDUNDANCY RECEIVED THROUGH A UNICAST SYSTEM - A receiver includes: a broadcast receiver receiving a receiver input data stream segmented into frames, wherein basic codeword portions of codewords are mapped onto the frames, a codeword including at least a basic codeword portion generated from an input data word according to a first code; a data demapper demapping the basic codeword portions; a decoder error correction code decoding the codewords into output data words of at least one output data stream in a regular decoding using the basic codeword portion in a codeword; a check unit checking if the regular decoding of a codeword is erroneous; a unicast request unit requesting, if the regular decoding of a codeword is erroneous, an auxiliary codeword portion of the erroneously decoded codeword for incremental redundancy in an additional decoding; a unicast receiver unit receiving an auxiliary codeword portion of the erroneously decoded codeword. | 10-04-2012 |

20120254683 | APPARATUS AND METHOD FOR MAPPING AND DEMAPPING SIGNALS IN A COMMUNICATION SYSTEM USING A LOW DENSITY PARITY CHECK CODE - An apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code are provided. In the method, LDPC codeword bits are written column-wise and read row-wise, substreams are generated by demultiplexing the read bits using a demultiplexing scheme, and bits included in each of the substreams are mapped to symbols on a signal constellation. The demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams. | 10-04-2012 |

20120084620 | TRANSMISSION DEVICE AND RECEIVING DEVICE - A transmission device according to the present invention splits information bits, calculates two parity bit sequences from the split information bits, combines the parity bit sequences with information bits (encoded information bit) such that the calculated two parity bit sequences are not added to the same information bits. Then, the transmission device changes the order of the combined information, distributes each of the reordered information to levels L | 04-05-2012 |

20120221916 | MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS - Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles. | 08-30-2012 |

20120221915 | SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES - An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates. | 08-30-2012 |

20120221914 | Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks - A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture. | 08-30-2012 |

20120221913 | ERROR CORRECTION CODES FOR INCREMENTAL REDUNDANCY - A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations. | 08-30-2012 |

20120084619 | METHOD AND ARRANGEMENT FOR BLIND DEMULTIPLEXING A POLARISATION DIVERSITY MULTIPLEX SIGNAL - A received optical signal (S | 04-05-2012 |

20120084617 | MODIFIED PROGRESSIVE EDGE-GROWTH LDPC CODES FOR ULTRA-HIGH-SPEED SERIAL OPTICAL TRANSPORT - Systems and methods enabling ultra-high-speed optical transport The systems and methods include receiving a modulated, encoded input stream. Channel impairments are removed using MAP equalization. Symbols are detected in the input stream to produce a stream of encoded data. The stream of encoded data is decoded with one or more low density parity check (LDPC) decoders that use an LDPC code built by modified progressive edge growth. The LDPC code is built by iteratively expanding trees from each variable node until all check nodes are connected to the respective variable node, while controlling both the local girth and the global girth of the code. | 04-05-2012 |

20090313524 | LOW DENSITY PARITY CODE ENCODING DEVICE AND DECODING DEVICE AND ENCODING AND DECODING METHODS THEREOF - A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix. | 12-17-2009 |

20120221912 | OPTICAL TRANSMISSION AND RECEPTION SYSTEM AND OPTICAL RECEPTION DEVICE - An object of the invention of the present patent application is to provide a frame synchronization technique that will not be prone to enter a frame asynchronization state even if a bit error occurs over a transmission path and the technique serves to convert a received optical signal into an electric signal, correct an error of the electric signal so as to cause a frame synchronization establishment state to occur, count the successive number of synchronization words that have bit errors in excess of an allowable value in an error-correction-coded electric signal after the frame synchronization establishment state has occurred, and determine that a frame asynchronization state has occurred when the successive number reaches a predetermined number. | 08-30-2012 |

20120226954 | ERROR CORRECTION DECODER AND STORAGE APPARATUS - According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion. | 09-06-2012 |

20120260143 | METHOD OF DECODING CONTENT DATA BLOCKS, CORRESPONDING COMPUTER PROGRAM PRODUCT AND DECODING DEVICE - When decoding a set of symbols to be decoded, several data blocks representative of the set of symbols to be decoded are received by a decoding node of a communications network. The data blocks are encoded using an error correction code enabling a decoding by erasure. The decoding node performs the following steps: first selecting at least one of the data blocks, first determining first erasures, and checking whether the number of the first erasures is below a given threshold. In a case the check is positive, the decoding node performs first decoding by erasure of the set of symbols to be decoded. In a case the check is negative, the decoding node performs second selecting of at least one of the data blocks, second determining second erasures, and second decoding by erasure of the set of symbols to be decoded from the second erasures. | 10-11-2012 |

20140325304 | ENCODING METHOD, ENCODER, AND DECODER - A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data. | 10-30-2014 |

20140365842 | DECODING METHOD AND DECODING DEVICE FOR POLAR CODE CASCADED WITH CYCLIC REDUNDANCY CHECK - The embodiments of the present invention provide a decoding method and a decoding device for a polar code cascaded with CRC. The decoding method includes: performing SC-List decoding on a Polar code according to the number of survival paths L to obtain L survival paths, where L is a positive integer; performing cyclic redundancy check on the L survival paths respectively; and increasing the number of survival paths when all the L survival paths fail to pass the cyclic redundancy check, and acquiring a decoding result of the Polar code according to the increased number of survival paths. In the embodiments of the present invention, the path number of survival paths is adjusted according to a result of the cyclic redundancy check, so as to output paths as much as possible, where the output paths can pass the cyclic redundancy check, thereby improving decoding performance. | 12-11-2014 |

20140298130 | LDPC MULTI-DECODER ARCHITECTURES - Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity-check matrix includes a plurality of parity check matrices. Each parity check matrix is configured to operate with x check NPEs and y bit NPEs. The numbers n, x, and y, are selected such that ny codeword bits are processed in the single time unit by a high throughput decoder and y codeword bits are processed in the single time unit by a low throughput decoder. | 10-02-2014 |

20100332938 | Techniques for LDPC decoding - An embodiment of the present invention provides an apparatus, including a transceiver operable for communication using LDPC codes for error correction, the transceiver adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission, and wherein the LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of the block dictates a clock cycles budget that the server can use. | 12-30-2010 |

20080301517 | SYSTEMS AND METHODS FOR LDPC DECODING WITH POST PROCESSING - Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a method for post processing error correction in a decoder system is disclosed. The method includes receiving and iteratively decoding a soft input to generate a hard output associated with the soft input. The method further includes post processing when a plurality of parity checks fail. At least one bit of the hard output is identified as being potentially incorrect. The identified bit is modified, and the plurality of parity checks is thereafter repeated. | 12-04-2008 |

20090217127 | TURBO DECODING APPARATUS AND METHOD - A turbo decoding method and apparatus for performing iterative decoding on a received signal is provided. A decoder receives a signal and an (N−1) | 08-27-2009 |

20090217122 | Coding Apparatus and Coding Method - The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder | 08-27-2009 |

20140173375 | LDPC ENCODING/DECODING METHOD AND DEVICE USING SAME - Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented. | 06-19-2014 |

20150058692 | LOW-DENSITY PARITY-CHECK DECODING METHOD AND LOW-DENSITY PARITY-CHECK DECODER USING THE SAME - A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph. | 02-26-2015 |

20110231729 | APPARATUS AND METHOD FOR OPTIMIZING AN ITERATIVE FEC DECODER - Consistent the present disclosure, errored bits are inserted into a data stream, which is carried by an optical signal. The optical signal is transmitted over an optical link that may induce additional errors, i.e., add additional errored bits to the data stream. At the receive end, the optical signal is converted into a corresponding electrical signal that carries the data stream. The data stream is subject to forward error correction (FEC) decoding with an iterative decoder, for example. The iterative decoder decodes the data stream over a number of iterations until both the inserted errored bits and the additional errored bits are corrected. Since the number of inserted bits is known, the number of iterations required to correct the inserted bits is also known (“first iterations”). Accordingly, the number of iterations required to correct the additional errored bits caused by tranmission over the optical link may be determined based on the total number of iterations performed and the number of the first iterations. | 09-22-2011 |

20110231728 | PACKET ENCODING METHOD TO PROVIDE UNEQUAL ERROR PROTECTION TO USERS AND/OR APPLICATIONS DATA - Embodiments of the invention provide a packet encoding scheme to ensure unequal error protection to different bits in a packet or in multiple packets. In one embodiment, a method to process bits in a bit stream comprises scrambling the bit stream; separating the scrambled bit stream into a high priority bit stream with an order of high priority bits from left to right and a low priority bit stream with an order of low priority bits from left to right; rearranging the bits by embedding the high priority bits in the low priority bit stream while preserving the two orders, the rearranged bit stream including blocks of bits, each block including one or more high priority bits disposed left of corresponding one or more low priority bits to provide protection for the high priority bits against noise which is at least equal to protection for the low priority bits; and modulating the rearranged bit stream using Gray encoding method to produce an encoded bit stream. | 09-22-2011 |

20110239080 | ERROR DETECTION/CORRECTION CIRCUIT, MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS - An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability β in association with each first address, a check node storage section that stores TMEM variables to calculate an external value α in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units. | 09-29-2011 |

20100235710 | SIGNAL TRANSMISSION METHOD AND TRANSMITTER IN RADIO MULTIPLEX TRANSMISSION SYSTEM - A disclosed signal transmission method in a radio multiplex transmission system comprises the steps of: serial-to-parallel converting serial data to be transmitted into N (N: two or more) parallel data series; independently performing an error-correcting encoding process on the parallel signals of the N data series serial-to-parallel converted; parallel-to-serial converting the parallel signals encoded with error-correcting codes; performing an interleaving process on the parallel-to-serial converted signals; serial-to-parallel converting the interleaved signals into L (L: two or more) parallel data series and transmitting each of the L data series using L antennas; receiving the transmitted signals; separating the received signals into M (M: two or more) data series and parallel-to-serial converting the M data series; performing a deinterleaving process on the parallel-to-serial converted signals; serial-to-parallel converting the deinterleaved signals into N data series; independently performing an error-correcting decoding process on the parallel signals of the N data series serial-to-parallel converted; and parallel-to-serial converting the signals in which the error-correcting codes are decoded, thereby recovering the transmitted data. | 09-16-2010 |

20100235708 | WIRELESS COMMUNICATION METHOD, INFORMATION ACCESS METHOD, AND VIRTUAL ANTENNA RADIATION PATTERN FORMING METHOD - A wireless communication method for transmitting information to the designated region with the boundary defined by the sharp cutoff is provided. Receivers outside the designated region are excluded from retrieving the encoded information. The boundary of designated region is adjustable. The wireless communication method can be applied to clearly defining the accepted region and rejection region in satellite communications. The wireless communication method includes steps of providing an information; encoding the information into an encoded data regarding a designated bit-energy-to-noise-ratio; transmitting the encoded data to form a virtual antenna radiation pattern covering a designated region with boundary defined by the sharp cutoff based on the designated bit-energy-to-noise-ratio; receiving the encoded data; and decoding the encoded data into the original information only when receivers within the designated region with bit-energy-to-noise-ratio no less than the designated bit-energy-to-noise-ratio. The critical feature of the method is clarified by experiments on the communication satellite ST-1. | 09-16-2010 |

20100235707 | Wireless receiver system and method with automatic gain control - A wireless receiver system with automatic gain control, which includes a receiving path, an analog to digital converter, an automatic gain control (AGC) device and a controller. The controller has an adjacent channel interference off mode, an adjacent channel interference acquisition mode and an adjacent channel interference tracking mode to accordingly set the AGC device for adjusting the gains of a plurality of modules of the receiving path. Namely, the strengths of different adjacent channel interferences are appropriately adjusted to thereby obtain the best received signal quality. | 09-16-2010 |

20130290806 | Systems and Methods for Data Decoder State Preservation During Extended Delay Processing - The present invention is related to systems and methods for maintaining additional processing information during extended delay processing. | 10-31-2013 |

20130290805 | Distributed System for Fault-Tolerant Data Storage - Fault-tolerant storage is provided using a distributed data storage system that receives input data from clients and divides that data into data blocks for storage. The data blocks are processed using a coding scheme that generates redundant level one error correction blocks (L1EC Blocks). The L1EC blocks enable the reconstruction of one or more damaged or inaccessible data blocks, so long as sufficient undamaged elements are still accessible. The L1EC blocks and the data blocks are divided into distribution sets and these sets are stored at a plurality of data storage locations. At each data storage location additional level two error correction blocks (L2EC blocks) are generated that provide local data redundancy. The L2EC blocks enable reconstruction of damaged elements at a data storage location without requiring communication with the other data storage locations. | 10-31-2013 |

20150121162 | ENCODING METHOD, ENCODER, DECODING METHOD AND DECODER - An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n−1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using Equation 1 as a g-th (g=0, 1, . . . , q−1) parity check polynomial to satisfy 0. | 04-30-2015 |

20100229069 | DRIVE DEVICE, CONTENT REPRODUCTION DEVICE, RECORDING DEVICE, DATA READOUT METHOD, PROGRAM, RECORDING MEDIUM, AND INTEGRATED CIRCUIT - A drive device is provided to promote copyright protection by preventing playback of copied contents, even if unique identification information on a recording medium, used to generate title keys for decrypting encrypted contents, is revealed, and the contents are independently encrypted and copied using this identification information. Identification information unique to a recording medium | 09-09-2010 |

20100229067 | Cable Interconnection Techniques - Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes. | 09-09-2010 |

20110296269 | RECEIVER WITH CAPABILITY OF CORRECTING ERROR - A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits. | 12-01-2011 |

20130305113 | DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD - When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for an LDPC codes having coding rates of 7/15, b | 11-14-2013 |

20110320906 | ENCODER, DECODER, AND ENCODING METHOD - An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit ( | 12-29-2011 |

20110320902 | CONDITIONAL SKIP-LAYER DECODING - In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder. | 12-29-2011 |

20130151922 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 06-13-2013 |

20140208180 | Systems and Methods for Reusing a Layered Decoder to Yield a Non-Layered Result - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 07-24-2014 |

20130007553 | TRANSMISSION SYSTEM AND ERROR CORRECTION CONTROL METHOD - There is provided an error correction control method of a transmission system on which a signal is transmitted from a first transmission apparatus to a second transmission apparatus, the error correction control method including: transmitting a signal for a mode change request to change an error correction mode from the second transmission apparatus to the first transmission apparatus; transmitting signals having a change timing value in a specific order with a specific period from the first transmission apparatus to the second transmission apparatus when the first transmission apparatus receives the mode change request; changing the error correction mode of the first transmission apparatus when the change timing value to be transmitted becomes a specific value in the first transmission apparatus; and changing the error correction mode of the second transmission apparatus in response to the change timing value received with the specific period from the first transmission apparatus. | 01-03-2013 |

20130007551 | Stochastic Stream Decoding of Binary LDPC Codes - Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes. | 01-03-2013 |

20100146365 | ENCODING AND MODULATING METHOD, AND DECODING METHOD FOR WIRELESS COMMUNICATION APPARATUS - Provided is a bit interleaved coded modulation-iterative decoding (BICM-ID) technique suffering a small loss in a transfer rate. A BICM-ID technique allowing a decoder to treat a small processing quantity is also provided. Encoding is carried out according to a code based on an iterative code. Encoded bits are reordered during interleaving processing, subjected to multi-valued modulation through extended mapping, and then transmitted. The extended mapping includes number-of-bits thinning processing of thinning l bits into m bits (m | 06-10-2010 |

20100146363 | METHOD AND SYSTEM OF SINGLE CARRIER BLOCK TRANSMISSION WITH PARALLEL ENCODING AND DECODING - A Single Carrier Block Transmission (SCBT) system employs an inherently parallel approach to error correction processing. At the transmission system ( | 06-10-2010 |

20100138718 | METHOD AND DEVICE FOR PADDING OPTIMIZATION OF SEGMENTED TURBO CODES - A method for forming a bit sequence having a number of M bits from a bit sequence having a number of N bits, wherein M/2 | 06-03-2010 |

20100131819 | LDPC DECODER VARIABLE NODE UNITS HAVING FEWER ADDER STAGES - In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and w | 05-27-2010 |

20140189458 | SOFT INPUT, SOFT OUPUT MAPPERS AND DEMAPPERS FOR BLOCK CODES - A codebook which includes a plurality of messages and a plurality of codewords, a specified codeword bit value, and a specified message bit value are obtained. The LLR for bit ci in a codeword is generated, including by: identifying, from the codebook, those codewords where bit ci has the specified codeword bit value; for a message which corresponds to one of the codewords where bit ci has the specified codeword bit value, identifying those bits which have the specified message bit value; and summing one or more LLR values which correspond to those bits, in the message which corresponds to one of the codewords where bit ci has the specified codeword bit value, which have the specified message bit value. | 07-03-2014 |

20140289583 | DECODING APPARATUS, DECODING METHOD, AND DECODING PROGRAM - According to one embodiment, a decoding apparatus includes first and second acquisition units, a holding unit, a calculation unit, and a decision unit. The first acquisition unit acquires first measurement values of measurements performed to measure an eigenvalue of an encoded Z operator to a first encoded qubit of the two encoded qubits. The second acquisition unit acquires second measurement values of measurements performed to measure an eigenvalue of an encoded X operator to a second encoded qubit of the two encoded qubits. The holding unit holds error probabilities for the first measurement values and the second measurement values. The calculation unit calculates probabilities for measurement values of an encoded Bell measurement by using the first measurement values, the second measurement values, and the error probabilities. The decision unit decides measurement values of the encoded Bell measurement, based on the calculated probabilities. | 09-25-2014 |

20140289582 | Systems and Methods for Reduced Constraint Code Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 09-25-2014 |

20110239079 | PROGRAMMABLE CIRCUIT FOR HIGH SPEED COMPUTATION OF THE INTERLEAVER TABLES FOR MULTIPLE WIRELESS STANDARDS - A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables. | 09-29-2011 |

20140281784 | Systems and Methods for Data Repair - An embodiment method for data repair in a storage system includes determining, by a processor, a minimum number of missing data blocks needed to repair a corrupted object in a first portion of the storage system, wherein the missing data blocks are not available in the first portion of the storage system, retrieving only the minimum number of missing data blocks needed to repair the corrupted object from a second portion of the storage system, and repairing the corrupted object in the first portion of the storage system using erasure codes and the retrieved minimum number of missing data blocks. | 09-18-2014 |

20140281786 | LAYERED DECODING ARCHITECTURE WITH REDUCED NUMBER OF HARDWARE BUFFERS FOR LDPC CODES - A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained. | 09-18-2014 |

20140372825 | METHOD AND APPARATUS FOR ENCODING AND DECODING OF LOW DENSITY PARITY CHECK CODES - An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column. | 12-18-2014 |

20120102378 | WIRELESS RELAY APPARATUS, WIRELESS RECEIVING APPARATUS, AND DECODING METHOD - In one embodiment, a wireless relay apparatus for replaying a signal processed by first encoding from a transmitting apparatus to a receiving apparatus is disclosed. The apparatus includes a demodulation unit, a decoding unit, a detection unit, an extraction unit, and an encoding unit. The demodulation unit demodulates a received signal. The decoding unit performs error correction decoding corresponding to the first encoding on the demodulated signal. The detection unit detects an error in a decoded signal. The extraction unit extracts a portion pertaining to information data from the demodulated signal by hard decision, if the detection unit detects an error. The encoding unit performs error correcting coding on the extracted portion pertaining to the information data with an error. The information data encoded by the encoding unit is transmitted. | 04-26-2012 |

20130080852 | ERROR CORRECTING METHOD, ERROR CORRECTING APPARATUS, SENDING DEVICE, RECEIVING DEVICE, AND ERROR CORRECTING PROGRAM - Disclosed is an error correcting method for correcting an error of digital data, which includes a plurality of sub-frames including a plurality of block code words, including: extracting and aligning a block code word, which is included in a past sub-frame; and generating a redundant data block code word by use of a block code word, which is included in a latest sub-frame, and the aligned block code word, and adding the redundant data block code word to the latest sub-frame, wherein the redundant data block code word is used for generating a redundant data block code word, which is added to a next sub-frame. | 03-28-2013 |

20110029836 | METHOD AND APPARATUS FOR STORAGE INTEGRITY PROCESSING BASED ON ERROR TYPES IN A DISPERSED STORAGE NETWORK - A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice. | 02-03-2011 |

20110029835 | Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding - Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix including selecting a non-affiliated variable node; identifying a check node of the lowest degree; connecting a first edge of the non-affiliated variable node to the identified check node; and connecting one or more additional edges of the non-affiliated variable node to check nodes in accordance with a quasi-cyclic constraint associated with a circulant is disclosed. | 02-03-2011 |

20090132887 | Communication Apparatus and Decoding Method - A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row. | 05-21-2009 |

20100205504 | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process - A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure. | 08-12-2010 |

20130268821 | DECODING APPARATUS AND DECODING METHOD FOR DECODING DATA ENCODED BY LDPC - A data storage unit receives LDPC encoded data. A min-sum processing unit alternately executes, on the inputted data, check node processing for updating an external value ratio based on a priori value ratio and variable node processing for updating the priori value ratio based on the external value ratio, by executing a min-sum algorithm. A control unit adjusts, in accordance with the magnitude of the priori value ratio to be updated in the variable node processing, the magnitude of a normalization constant to be used in updating the external value ratio in the check node processing. | 10-10-2013 |

20100281330 | Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code - Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform decoding of more than one type of LDPC coded signals. A common basis of decoder hardware (e.g., decoder circuitry) is employed when decoding all of the various types of LDPC coded signals that such a communication device can decode. However, all of the decoder hardware is only employed to decode signals corresponding to the lowest code rate LDPC code supported by the communication device. A first subset of the decoder hardware is employed to decode signals corresponding to the second to lowest code rate LDPC code, a second subset (being less than the first subset) is employed to decode signals corresponding to the third to lowest code rate LDPC code, etc. | 11-04-2010 |

20120240002 | METHOD FOR CONTROLLING A BASIC PARITY NODE OF A NON-BINARY LDPC CODE DECODER, AND CORRESPONDING BASIC PARITY NODE PROCESSOR - A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U | 09-20-2012 |

20080288846 | APPARATUS AND METHOD FOR ENCODING AND DECODING BLOCK LOW DENSITY PARITY CHECK CODES WITH A VARIABLE CODING RATE - An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code. | 11-20-2008 |

20110239078 | ENHANCED BLOCK-REQUEST STREAMING USING COOPERATIVE PARALLEL HTTP AND FORWARD ERROR CORRECTION - A block-request streaming system provides for improvements in the user experience and bandwidth efficiency of such systems, typically using an ingestion system that generates data in a form to be served by a conventional file server (HTTP, FTP, or the like), wherein the ingestion system intakes content and prepares it as files or data elements to be served by the file server, which might or might not include a cache. A client device can be adapted to take advantage of the ingestion process as well as including improvements that make for a better presentation independent of the ingestion process. In the block-request streaming system, the an ingestion system generates data according to erasure codes and the client device, through various selection and timing of requests for media data and redundant data, can efficiently decode media to provide for presentations. | 09-29-2011 |

20120137191 | DECODING DEVICE, DECODING METHOD, AND PROGRAM - A decoding device including a decoding unit which decodes encoded data, an inverse orthogonal transformation unit which performs inverse orthogonal transformation for the encoded data and obtains a time series waveform element in a unit of blocks, a correlation calculation unit which obtains a correlation between a time series waveform element of a block arranged immediately before an error block which is a block in which an error has occurred during decoding by the decoding unit and a time series waveform element of a block arranged a predetermined number of blocks before the block, a cycle calculation unit which obtains a basic cycle of a block unit of the error block based on the correlation obtained by the correlation calculation unit, and a generation unit which generates a substitute signal of the time series waveform element of the error block. | 05-31-2012 |

20120137190 | RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS - An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard. | 05-31-2012 |

20100299573 | Systems and methods for LDPC coded modulation - Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error floor, no cycles, an equal bit error rate for the information bits and the parity bits, and timely construction of both a parity check matrix with variable codeword size and a generator matrix is possible. | 11-25-2010 |

20100299572 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD - A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of ⅔, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by b | 11-25-2010 |

20120260142 | FOUR-DIMENSIONAL NON-BINARY LDPC-CODED MODULATION SCHEMES FOR ULTRA HIGH-SPEED OPTICAL FIBER COMMUNICATION - Systems and methods are disclosed for communicating signals, by receiving a K-symbol-long input block from a 2 | 10-11-2012 |

20110035642 | Secure Transmission With Error Correcting Code - The invention concerns a method and a system for encoding digital data (DATA) represented by source symbols, with an error correcting code generating parity symbols from, for each parity symbol, a plurality of source symbols and at least one parity symbol of preceding rank, including at least encrypting once ( | 02-10-2011 |

20100318875 | Data Transmission Method and Equipment - The present invention discloses a data transmission method and apparatus. The method comprises: segmenting data to be transmitted into information file segments with a length of Tb bits; performing forward error correction (FEC) coding for Tb information bit sequences composed of bits in same positions in a plurality of continuous information file segments to generate Tb check bit sequences, putting each bit of the check bit sequences in the same position in the check file segments as the corresponding information bit sequences; and transmitting each of the information file segments and check file segments according to their order; the number of bits contained in the information bit sequences being less than or equal to the maximum length of K | 12-16-2010 |

20100318873 | Tree Decoding Method For Decoding Linear Block Codes - A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(y)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity. | 12-16-2010 |

20100318872 | Decoding Method for LDPC Code Based on BP Arithmetic - A decoding method for LDPC codes based on BP algorithm, includes initializing LLR (q | 12-16-2010 |

20090164863 | METHOD OF ENCODING AND DECODING USING LOW DENSITY PARITY CHECK MATRIX - A method of encoding and decoding using an LDPC code is disclosed, by which encoding and decoding performance can be enhanced and which can be effectively applied to a communication system employing a variable data rate. In encoding or decoding an input data using a parity check matrix H, the present invention is characterized in that the parity check matrix H has a configuration of H=[H | 06-25-2009 |

20090158117 | METHOD AND SYSTEM FOR PROVIDING LONG AND SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES - An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, n | 06-18-2009 |

20080270867 | Method of Encoding and Decoding Using Ldpc Code and Apparatus Thereof - A method of encoding/decoding using an LDPC code and apparatus thereof are disclosed, by which a memory for storing a parity check matrix can be saved. The present invention includes generating a parity check matrix by expanding a base matrix including a permutation type defining a permutation matrix as at least one element, wherein the permutation matrix is generated from permutating a sequence of at least one of rows and columns of at least one base permutation matrix or rotating the at least one base permutation matrix and encoding or decoding the input data using the parity check matrix. | 10-30-2008 |

20110258510 | CODE GENERATOR AND DECODER FOR COMMUNICATIONS SYSTEMS OPERATING USING HYBRID CODES TO ALLOW FOR MULTIPLE EFFICIENT USES OF THE COMMUNICATIONS SYSTEMS - A method of encoding data for transmissions from a source to a destination over a communications channel is provided. The method operates on an ordered set of source symbols and may generate zero or more redundant symbols from the source symbols, wherein data is encoded in a first step according to a simple FEC code and in a second step, data is encoded according to a second FEC code, more complex than the first FEC code. The first FEC code and/or the second FEC code might comprise coding known in the art. These steps result in two groups of encoded data in such a way that a low-complexity receiver may make use of one of the groups of encoded data while higher complexity receivers may make use of both groups of encoded data. | 10-20-2011 |

20110283160 | TRANSMITTER APPARATUS - A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. | 11-17-2011 |

20080307285 | MEMORY DEVICES AND SYSTEMS INCLUDING ERROR-CORRECTION CODING AND METHODS FOR ERROR-CORRECTION CODING - In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer. | 12-11-2008 |

20120226956 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING IN A COMMUNICATION/BROADCASTING SYSTEM - A method and apparatus for transmitting in a communication/broadcasting system is provided. The method includes determining to use an additional parity technique, generating an Nth parity check matrix, where N is an integer, performing Low Density Parity Check (LDPC) encoding using the Nth parity-check matrix, modulating a codeword corresponding to the Nth parity-check matrix, and transmitting the modulated codeword. | 09-06-2012 |

20130246883 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example. | 09-19-2013 |

20150128005 | TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF - A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. | 05-07-2015 |

20130139024 | HIGH ORDER MODULATION PROTOGRAPH CODES - Digital communication coding methods for designing protograph-based BICM that is general and applies to any modulation. The general coding framework can support not only multiple rates but also adaptive modulation. The method is a two stage lifting approach. In the first stage, an original protograph is lifted to a slightly larger intermediate protograph. The intermediate protograph is then lifted via a circulant matrix to the expected codeword length to form a protograph-based LDPC code. | 05-30-2013 |

20140059401 | HARD-DECISION DECODING METHOD AND LOW-DENSITY PARITY-CHECK DECODER USING SAME - A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node. | 02-27-2014 |

20120110408 | LOW COMPLEXITY DECODING OF LOW DENSITY PARITY CHECK CODES - An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. | 05-03-2012 |

20120290891 | METHOD AND APPARATUS FOR DECODING LOW DENSITY PARITY CHECK CODE - A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm. | 11-15-2012 |

20110320905 | Data Sending/Receiving Method with Forward Error Correction and Related Component and System for Gigabit Ethernet - A method for sending data from a transmitter to a receiver in a transmission network comprising receiving outgoing data that is eight-bits-ten-bits (8b10b) encoded at a Gigabit Ethernet (GE) line rate from a physical medium attachment (PMA) layer, 8b10b decoding the received outgoing data, 64-bits-to-66-bits (64b66b) encoding the 8b10b decoded outgoing data, forward error correction (FEC) encoding the 64b66b encoded outgoing data, and serializing and sending the 64b66b and FEC encoded outgoing data at the GE line rate to a physical medium dependent (PMD) layer. | 12-29-2011 |

20090125779 | CONTINUOUS REDUNDANCY CHECK METHOD AND APPARATUS - A continuous redundancy check method and apparatus receives ( | 05-14-2009 |

20090327833 | MEMORY DEVICE - A memory device includes: a data port for receiving data; a storing unit for storing data; a control signal input port for receiving a command signal; an error correcting unit for performing error correction operation over the data for the data port and the command signal for the control signal input port; and a control unit for controlling the storing unit for storing the data produced by the error correcting unit. | 12-31-2009 |

20110066916 | SYSTEM AND METHOD FOR STRUCTURED LDPC CODE FAMILY - A low density parity check (LDPC) family of codes is constructed by: determining a protograph for a mother code for the LDPC family of codes. The protograph is lifted by a lifting factor to design code specific protograph for a code. The method also includes constructing a base matrix for the code. The base matrix is constructed by replacing each zero in the code specific protograph with a ‘−1’; and replacing each one in the code specific protograph with a corresponding value from the mother matrix. The LDPC code includes a codeword size of at least 1344, a plurality of information bits, and a plurality of parity bits. The LDPC code is based on a mother code of code length 672. | 03-17-2011 |

20110066917 | Method and Apparatus for Elementary Updating a Check Node During Decoding of a Block Encoded with a Non-binary LDPC Code - Method of elementary updating a check node of a non-binary LDPC code during, comprising receiving a first input message (U) and a second input message (V) each comprising n | 03-17-2011 |

20110066915 | ADAPTING BIT ERROR RATE TO A TARGET QUALITY OF SERVICE - Communication frames transmitted over a communication network may have different QoS requirements for each communication session. The required BER for different types of communication session is selected based at least in part on the required QoS for that communication session. When frames are received, the QoS level associated with the frame is determined Based at least in part on the QoS level, the frames are routed toward the destination over a path that provides BER protection commensurate with the required QoS. Prior to transmission to the destination, the processed frames are multiplexed together into a single stream of segment. On the receiving side, the stream of segments is divided in accordance with the QoS level associated with the segments and the segments are routed over a path that is selected, at least in part, on the QoS level. Over this selected path, the original frames are restored and then provided to the destination node. | 03-17-2011 |

20090319861 | USING DAMPING FACTORS TO OVERCOME LDPC TRAPPING SETS - To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N−K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules. | 12-24-2009 |

20090319860 | OVERCOMING LDPC TRAPPING SETS BY DECODER RESET - To decode, in a plurality of iterations, a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N−K check nodes of a graph. If the decoding has failed to converge according to a predetermined failure criterion and if the codeword bit estimates satisfy a criterion symptomatic of the graph including a trapping set, at least a portion of the messages are reset before continuing the iterations. Alternatively, if the decoding fails to converge according to a predetermined failure criterion, at least a portion of the messages that are sent from the bit nodes are truncated before continuing the iterations. | 12-24-2009 |

20090319858 | REDUCED COMPLEXITY LDPC DECODER - To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes. | 12-24-2009 |

20090319857 | Method and apparatus for parallel processing multimode LDPC decoder - A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a decoder configured to perform low density parity check decoding. The decoder includes a number of Context Reconfigurable Instruction Set Processors (CRISPs). The CRISPs are configured to process received data in parallel. The decoder includes a plurality of memory units, and each of the CRISPs includes a plurality of processors. | 12-24-2009 |

20090319856 | Method and apparatus for software-defined radio LDPC decoder - A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a low density parity check (LDPC) decoder. The receiver is configured to receive encoded transmissions and perform low density parity check decoding operations using a CRISP decoder. The CRISP decoder includes a plurality of memory units, and a plurality of processors. | 12-24-2009 |

20110167315 | APPARATUS AND METHOD FOR CODING/DECODING BLOCK LOW DENSITY PARITY CHECK CODE IN A MOBILE COMMUNICATION SYSTEM - A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix. | 07-07-2011 |

20110167314 | Variable forward error correction for optical communication links - A method and system for setting a variable forward error correction overhead in an optical transport network frame for an optical link at a node are disclosed. In one embodiment, a method includes selecting a forward error correction overhead, signaling an optical node the selected forward error correction overhead, and setting the forward error correction overhead in the optical network transport frame for use in transmission of data over the optical link. In one embodiment, the forward error correction overhead is complementary to the data payload to maintain total transmission rate. | 07-07-2011 |

20110167313 | MULTI-CHANNEL STATISTICAL MULTIPLEXING OF FEC DECODERS - A method for dividing a total number of decoders among decoder queues of codewords of different sizes, the codewords transmitted on return communication links from data terminals to a gateway of a satellite communications system, includes for each of K groups, allocating a respective number of decoders dedicated to decoding codewords of a particular size, where K is a number of different sizes of codewords, and the respective number of decoders is allocated from the total number of decoders and allocated in proportion to current offered load of codewords of the particular size. | 07-07-2011 |

20100199143 | TECHNIQUES FOR ENABLING SIMPLIFIED LDPC ENCODING AND DECODING - A method for low density parity check (LDPC) encoding comprises concatenating a predetermined number of zero bits to a scrambled input data word to generate a concatenated binary sequence; computing parity bits to be added to the concatenated binary sequence, wherein the computing is performed using an LDPC encoder; producing an encoded codeword that consists of the concatenated binary sequence and the parity bits; and replacing the predetermined number of zero bits in the encoded codeword with a scrambled binary sequence, thereby discarding the zero bits. | 08-05-2010 |

20080250294 | System and method for wireless communication of uncompressed video having a composite frame format - A system and method for efficiently communicating uncompressed video and for efficiently communicating corresponding acknowledgements in a system for wireless communication of uncompressed video are disclosed. In one embodiment, the method includes aggregating multiple subpackets of different types of data into a composite packet. The different types of data may include video, audio, control data, extraneous data files, and others. A robust composite packet configuration can provide for more flexible and more efficient transmission of data on the high rate channel as well as more efficient transmission of acknowledgements on the low rate channel. | 10-09-2008 |

20140082449 | LDPC Decoder With Variable Node Hardening - The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable node by using check node to variable node (C2V) messages from a previous iteration that are likely to be correct when generating variable node to check node (V2C) messages. | 03-20-2014 |

20140082448 | LDPC Decoder With Dynamic Graph Modification - The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification. | 03-20-2014 |

20090049358 | Methods and systems for terminating an iterative decoding process of a forward error correction block - The invention provides methods and systems for terminating an iterative decoding process of a Forward Error Correction block (FEC). The iterative decoding process of the FEC block is terminated upon determining that the FEC block cannot be decoded successfully. A method comprises calculating a metric based on one or more Log Likelihood Ratios (LLRs) corresponding to a first number of iterations of the iterative decoding process of the FEC block. The method further comprises, formulating one or more stopping criteria for the iterative decoding process based on a variation pattern of the metric over a second predetermined number of iterations of the iterative decoding process. The second predetermined number of iterations is a subset of the first number of iterations. Moreover, the method comprises terminating the iterative decoding process of the FEC block based on the one or more stopping criteria. | 02-19-2009 |

20120066563 | ERROR CORRECTION DECODER, MEMORY CONTROLLER AND RECEIVER - According to an embodiment, an error correction decoder carries out iterative decoding for data coded using an irregular LDPC code. The decoder includes a likelihood control unit. The likelihood control unit is configured to carry out weighting using first extrinsic value weights when a first condition including a condition that a code word cannot be obtained even when number of times the iterative decoding has been carried out is greater than a first iterative times, in order to increase absolute value of a extrinsic value from a check node not satisfying a parity check to a variable node, wherein the first extrinsic value weights are equal to each other or become larger in descending order of column weights of the variable nodes, and a maximum of the first extrinsic value weights is not equal to a minimum of the first extrinsic value weights. | 03-15-2012 |

20090313522 | METHOD AND APPARATUS FOR LOW LATENCY TURBO CODE ENCODING - A method and apparatus for performing low latency Turbo Code encoding of a frame of data is described. The disclosure includes a method for performing Turbo Code encoding on frame of data using by encoding via subsections using multiple constituent encoders in parallel. The information gains during a first encoding pass of the subsections is used to determine the start state for a second pass during which parity bits are generated. Both the interleaved and natural order encoding may be performed in parallel. | 12-17-2009 |

20090313521 | DATA BUS INVERSION USABLE IN A MEMORY SYSTEM - Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state. | 12-17-2009 |

20130091398 | OPTIMUM SIGNAL CONSTELLATION DESIGN FOR HIGH-SPEED OPTICAL TRANSMISSION - Systems and methods for data transport, comprising encoding one or more streams of input data with one or more low density parity check (LDPC) encoders, corresponding to one or more polarization/spatial mode branches. One or more encoded data streams are mapped to symbols, wherein the mapper is configured to assign bits of the symbols to a signal constellation and to associate the bits of the symbols with signal constellation points. A signal constellation is formulated which minimizes a mean-square error of the signal constellation representing the source. The optimum signal constellation size is adjusted to improve transmission quality by adjusting the signal constellation an optical signal to noise ratio (OSNR), wherein the signal constellation is selected using a look-up table (LUT); and the symbols are modulated in accordance with the output of the mapper onto a transmission medium. | 04-11-2013 |

20130091397 | Systems and Methods for Parity Sharing Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is operable to: reconstitute a second encoded sub-codeword from a combination of data including the first encoded sub-codeword and the composite sub-codeword; and correct an error in one of the first encoded sub-codeword and the second encoded sub-codeword based at least in part on a combination of the first encoded sub-codeword, the second encoded sub-codeword, and the composite sub-codeword. | 04-11-2013 |

20120117441 | Processor Architecture for Executing Wide Transform Slice Instructions - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 05-10-2012 |

20120117440 | LOW DENSITY PARITY CHECK (LDPC) CODE - Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown. | 05-10-2012 |

20100169736 | Encoding apparatus, system, and method using Low Density Parity Check (LDPC) codes - A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix. | 07-01-2010 |

20100169734 | BROADCAST RECEIVER AND METHOD FOR OPTIMIZING A SCALE FACTOR FOR A LOG-LIKELIHOOD MAPPER - Embodiments of a broadcast receiver and method for optimizing a scale factor in a log-likelihood ratio (LLR) mapper are generally described herein. In some embodiments, the broadcast receiver includes an LLR mapper to generate LLRs from demodulated data samples, a low-density parity-check (LDPC) decoder to generate decoded data from the LLRs, and an LLR optimizer to dynamically select a scale factor for the LLR mapper based on a number of iterations for convergence of the LDPC decoder. In some embodiments, the LLR optimizer iteratively revises the scale factor during receipt of broadcast signals until the number of iterations of the iterative decoder is either minimized for convergence or minimized for convergence failures. | 07-01-2010 |

20120089887 | DATA TRANSMISSION UTILIZING DATA PROCESSING AND DISPERSED STORAGE ERROR ENCODING - A method begins by a processing module dispersed storage error encoding fundamental component data of data in accordance with dispersed storage error coding parameters to produce a plurality of sets of encoded data slices, wherein the data includes the fundamental component data and enhancement component data. The method continues with the processing module transmitting a set of the plurality of sets of encoded data slices and transmitting a corresponding portion of the enhancement component data substantially concurrently with the transmitting of the set of the plurality of sets of encoded data slices. | 04-12-2012 |

20130151921 | ENCODING APPARATUS, ENCODING METHOD AND SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns. | 06-13-2013 |

20100153815 | Systems and Methods for Decreasing Latency in a Digital Transmission System - Disclosed herein are various embodiments of methods, systems, and apparatus for encoding OFDM packets in a digital communication system. In one exemplary method embodiment, LDPC codewords in an IEEE 802.11 wireless transmission are shortened, decreasing the iterations necessary to insure accurate communications. The codewords are shortened by adding known bits in predetermined locations in the last data symbol of a packet. | 06-17-2010 |

20110173509 | BIT MAPPING SCHEME FOR AN LDPC CODED 16APSK SYSTEM - A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 16APSK system, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel. | 07-14-2011 |

20140136917 | BUFFER MANAGEMENT USING SIDE INFORMATION - Devices and/or methods for managing a buffer containing failed data may utilize side information related to the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors and/or a local host requested status for buffered or unbuffered failed data. | 05-15-2014 |

20100115372 | Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition - Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header. | 05-06-2010 |

20100146361 | Multiple input hardware reuse using LDPC codes. - A network controller receives data substantially simultaneously from multiple client nodes. The network controller assigns to each client node one or more sub-carriers of an orthogonal frequency-division multiplexing access frequency spectrum. The client nodes transmit substantially simultaneously M LDPC codewords that are encoded in a parity check matrix so that the number of rows m′ depend on the code rate and are mapped on its assigned sub-carriers. The network controller computes a bit log-likelihood ratio for each received bit of the codewords and arranges the bit LLR by codeword to align with an equivalent parity check matrix. The network controller decodes the codewords with the equivalent parity check matrix. | 06-10-2010 |

20120272116 | Method and device for bandwidth self-adapting data ranking protection - The present disclosure discloses a method and a device for bandwidth self-adapting data ranking protection. The method comprises: performing redundancy protection computation on a data block to be transmitted so as to generate a redundant code of the data block, and setting a priority for the redundant code; determining whether bandwidth occupied by a redundant code with a highest priority is greater than current residual bandwidth; if the bandwidth occupied by the redundant code with the highest priority is not greater than the current residual bandwidth, carrying the redundant code with the highest priority in the current residual bandwidth; otherwise, according to a descending order of the priority, searching in residual redundant codes for a redundant code whose data amount is less than or equal to the current residual bandwidth, and carrying a found redundant code in the current residual bandwidth. The present disclosure improves the error tolerance of a system. | 10-25-2012 |

20100107032 | BIT LABELING FOR AMPLITUDE PHASE SHIFT CONSTELLATION USED WITH LOW DENSITY PARITY CHECK (LDPC) CODES - An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping. | 04-29-2010 |

20100125770 | DISTRIBUTED OPERATING SYSTEM MANAGEMENT - A system and method are provided for a distributed operating system manager. In one example, the method includes retrieving an internet protocol address of a boot server connected to a client computer via a network; determining whether the boot server is available via the network; transferring to the boot server a description of an operating system on the client computer; validating hardware credentials of the client computer; and determining whether to perform a remote boot process. | 05-20-2010 |

20100125769 | PARITY-CHECK-CODE DECODER AND RECORDING CONTROLLER - A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output. | 05-20-2010 |

20090300461 | DEVICE, METHOD AND COMPUTER PROGRAM PRODUCT FOR COMMUNICATION - A transmitter may include an encoder configured to encode a data bit vector to provide an codeword that includes a first codeword portion and a second codeword portion; wherein the first codeword portion is decodable by a first parity check process to yield the data bit vector; wherein the codeword is decodable by a second parity check process to yield the data bit vector; and a communication module, for transmitting the codeword. | 12-03-2009 |

20130031438 | MULTI-RATE LDPC DECODING - The subject technology provides a decoding solution that supports multiple choices of code rates. A decoder may be configured to receive a selected code rate from a plurality of code rates. On the selection of the code rate, the decoder may determine a circulant size based on the code rate, and, on receiving the codeword, update, during one or more parity-check operations, a number of confidence values proportional to the circulant size in each of a plurality of memory units, each number of confidence values corresponding to a portion of the codeword. | 01-31-2013 |

20110055657 | METHOD AND SYSTEM FOR STOPPING EXECUTION OF A TURBO DECODER - A method for conditionally stopping execution of a turbo decoder is proposed. The decoder has elementary decoders. Each elementary decoder performs a sequence of decoding operations and is arranged to receive an input from at least one other elementary decoder. The method determines for each specific decoding operation if the sequence of elementary decoding operations of the specific elementary decoder has substantially converged or substantially diverged. The method terminates the execution of decoding operations if a number of sequences has substantially converged or substantially diverged. | 03-03-2011 |

20110055656 | Systems, Methods, and Media for Checking Available Bandwidth Using Forward Error Correction - Methods for checking available bandwidth using forward error correction are provided, the methods comprising: identifying data to be transmitted; determining an amount of forward error correction data to be sent to a receiver; creating the forward error correction data based on corresponding data in the data to be transmitted; transmitting to the receiver the forward error correction data and the corresponding data in the data to be transmitted; determining an error level in at least one of the corresponding data and the forward error correction data; and when the error level is below a value, increasing the amount of bandwidth used in a transmission to the receiver of other data in the data to be transmitted over the amount of bandwidth used in the transmission to the receiver of the corresponding data and decreasing the amount of bandwidth used for forward error correction data in the transmission of the other data. | 03-03-2011 |

20110145675 | CALCULATION TECHNIQUE FOR SUM-PRODUCT DECODING METHOD (BELIEF PROPAGATION METHOD) BASED ON SCALING OF INPUT LOG-LIKELIHOOD RATIO BY NOISE VARIANCE - One or more embodiments provide a decoding technique (and its approximate decoding technique) enabling a stable operation even if a noise variance is low at the implementation with a fixed-point arithmetic operation having a finite dynamic range. A technique is provided for causing a computer to perform calculation using a sum-product decoding method (belief propagation method) with respect to LDPC or turbo codes. For calculating an update equation of a log extrinsic value ratio from an input, a (separated) correction term is prepared obtained by variable transformation (scale transformation) of the update equation so that the update equation is represented by a sum (combination) of a plurality of terms by transformation of the equation and a communication channel noise variance is a term separated from other terms constituting a sum of a plurality of terms as a term to be a factor (scale factor) by which a log is multiplied. With an estimated communication channel noise variance as an input, the (separated) correction term is approximated by a simple function so as to cause the computer to make calculation (iteration) on the basis of a fixed point on bit strings of finite length (m,f: m is the total number of bits and f is the number of bits allocated to the fractional part). | 06-16-2011 |

20110289375 | METHOD FOR CONSTRUCTING AN LDPC CODE, TRANSMITTER, AND RECEIVER - Disclosed are: a method for constructing a low-density parity-check (LDPC) code for use in next-generation mobile communication and deep-space communication by using a cyclic distribution; a transmitter; a receiver; and a system. The method includes a block cycle determination step in which the distribution of a block cycle constructed from non-zero cyclic shift element values is determined for the basic matrix of the LDPC code, a priority determination step in which the priorities of the non-zero cyclic shift element values included in each block cycle are determined on the basis of the determined block cycle distribution, and a calculation step in which the greatest common divisor is determined for the permutation elements of all magnitudes in the check matrix of the LDPC code, and the divisor is factored. According to this method, short cycles will not be included in any actual check matrix of an LDPC code constructed by using all different permutation elements. | 11-24-2011 |

20090150746 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the | 06-11-2009 |

20140298129 | Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder - A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′. | 10-02-2014 |

20090265600 | TEST MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ENCODER AND DECODER - A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. | 10-22-2009 |

20140281787 | Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder - Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder. | 09-18-2014 |

20130145228 | ENCODING METHOD - An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. The encoder exhibits encoding rates realized with a small circuit-scale and a high data reception quality. In the encoder ( | 06-06-2013 |

20110154151 | CHECK MATRIX CREATION DEVICE, CHECK MATRIX CREATION METHOD, CHECK MATRIX CREATION PROGRAM, TRANSMITTER, RECEIVER, AND COMMUNICATION SYSTEM - A check matrix creation device includes a circulant permutation matrix setting unit | 06-23-2011 |

20110154150 | FAST STOCHASTIC DECODE METHOD FOR LOW DENSITY PARITY CHECK CODE - Provided is a fast stochastic decoding method for a low density parity check (LDPC) code. The decoding method may include decoding the LDPC code based on an LDPC decoding scheme, using a message expressed by a log-likelihood ratio (LLR) value. | 06-23-2011 |

20110154149 | PARITY GENERATING APPARATUS AND MAP APPARATUS FOR TURBO DECODING - An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit. | 06-23-2011 |

20090031186 | Error correction coding apparatus - An error correction coding apparatus is disposed to generate a low-density parity-check code | 01-29-2009 |

20090049357 | Decoding Method for Quasi-Cyclic Low-Density Parity-Check Codes and Decoder for The Same - A decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes sequentially decodes a plurality of block codes defined by an identical parity-check matrix derived from a parity-check matrix of the QC-LDPC codes, wherein size of the identical parity-check matrix is smaller than size of the parity-check matrix. | 02-19-2009 |

20140380113 | ENHANCED BLOCK-REQUEST STREAMING USING COOPERATIVE PARALLEL HTTP AND FORWARD ERROR CORRECTION - A block-request streaming system provides for improvements in the user experience and bandwidth efficiency of such systems, typically using an ingestion system that generates data in a form to be served by a conventional file server (HTTP, FTP, or the like), wherein the ingestion system intakes content and prepares it as files or data elements to be served by the file server, which might or might not include a cache. A client device can be adapted to take advantage of the ingestion process as well as including improvements that make for a better presentation independent of the ingestion process. In the block-request streaming system, the an ingestion system generates data according to erasure codes and the client device, through various selection and timing of requests for media data and redundant data, can efficiently decode media to provide for presentations. | 12-25-2014 |

20140122961 | METHOD AND APPARATUS FOR CHANNEL CODING AND DECODING IN A COMMUNICATION SYSTEM USING A LOW-DENSITY PARITY-CHECK CODE - An apparatus and method are provided for channel coding in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes determining degrees for each of a plurality of column groups of an information part; determining a shortening order based on the degrees; generating a parity check matrix based on the shortening order; and performing coding using the parity check matrix. | 05-01-2014 |

20140122960 | TRAPPING-SET DATABASE FOR A LOW-DENSITY PARITY-CHECK DECODER - A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated. | 05-01-2014 |

20140122959 | Load Balanced Decoding of Low-Density Parity-Check Codes - A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated. | 05-01-2014 |

20090276683 | DATA TRANSMISSION EQUIPMENT AND GENERATING METHOD FOR TRANSMISSION CODE - A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit | 11-05-2009 |

20140331100 | SELECTING STORAGE UNITS TO REBUILD AN ENCODED DATA SLICE - A method begins with a processing module of a dispersed storage network (DSN) identifying an encoded data slice of a set of encoded data slices that requires rebuilding and identifying storage units of the DSN that store the set of encoded data slices. The method continues with the processing module determining a rebuilding metric regarding the identified encoded data slice and selecting a sub-set of the storage units for retrieving a decode threshold number of encoded data slices of the set of encoded data slices based on the rebuilding metric. When the decode threshold number of encoded data slices have been retrieved, the method continues with the processing module decoding the decode threshold number of encoded data slices to produce a reconstructed data segment and generating a rebuilt encoded data slice from the reconstructed data segment. | 11-06-2014 |

20110060960 | Decoding method and device for low density generator matrix codes - A decoding method for low density generator matrix codes is disclosed, which decodes a bit information sequence that is transmitted after encoding with LDGC, the method comprises: S | 03-10-2011 |

20110060959 | Method and Apparatus for Data Receiving - A method and apparatus for receiving data is provided. A data receiving terminal processes each received file block as follows: performing forward error correction decoding for Tb bit sequences to be decoded of the file block respectively, obtaining Tb decoded information bit sequences with a length of K, wherein, the i | 03-10-2011 |

20110060958 | METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES IN SUPPORT OF BROADBAND SATELLITE APPLICATIONS - An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite. | 03-10-2011 |

20120233517 | Data Processing Apparatus and Method - A process for generating a number representative of an analogue data source (ADS) in which during enrolment a distinctive characteristic of the ADS is measured to obtain physical data (PD). Part of the PD is used to generate a physical value (PV) representative of the ADS. An error correction algorithm (ECA) is applied to the PV to generate error correction data (ECD), which is transformed, using another part of the PD, to generate transform data. During subsequent regeneration of the PV, the distinctive characteristic is re-measured to generate a new set of PD, and a PV is generated using the same part of the PD physical data as was used during enrolment. ECD is generated by transforming the transform data, using the same part of the PD as was used to transform the ECD during enrolment. The ECA uses the regenerated ECD to correct errors in the PV representative of the ADS. | 09-13-2012 |

20110320903 | Latch Arrangement for an Electronic Digital System, Method, Data Processing Program, and Computer Program Product for Implementing a Latch Arrangement - An improved latch arrangement for an electronic digital system is disclosed. The latch arrangement comprises a certain number of standard latches configured as configuration-switch latches which are modified only by shift operation and/or during Error Checking and Correction (ECC) action, and a corresponding number of standard latches configured as Error Checking and Correction (ECC) latches storing Error Checking and Correction (ECC) bit data used to check latch data of said configuration-switch latches. | 12-29-2011 |

20090217129 | METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY-PARITY-CHECK CODES - A method and apparatus for encoding and decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The encoding method includes determining a modulation scheme for transmitting a symbol; determining a shortening pattern in consideration of the determined modulation scheme; grouping columns corresponding to an information word in a parity-check matrix of the LDPC code into a plurality of column groups; ordering the column groups; determining a range of a resulting information word desired to be obtained by shortening the information word; based on the range of the resulting information word, performing column group-by-column group shortening on the ordered column groups of the information word, according to the determined shortening pattern; and LDPC-encoding the shortened information word. | 08-27-2009 |

20090113271 | Method and apparatus for parallel structured latin square interleaving in communication system - A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix. | 04-30-2009 |

20090113270 | Data processing method of decoding coded data and data processor for the same - For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution. | 04-30-2009 |

20120023383 | ERROR CORRECTING DECODING APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK CODES | 01-26-2012 |

20090113269 | DATA DESCRAMBLING APPARATUS AND DATA DESCRAMBLING METHOD - When performing data descrambling for data including errors, a countermeasure against an error in a seed value that is required for the descrambling is realized in a system having no CPU. | 04-30-2009 |

20100088571 | HIGH SPEED LDPC DECODING - An optical probability-domain LDPC decoder suitable for implementation at 100 Gb/s and above provides large coding gains when based on large-girth LDPC codes. A basic building block, the probabilities multiplier circuit, used to implement both check node and probability node update circuits can be implemented using Mach-Zehnder delay interferometer. | 04-08-2010 |

20130297983 | Data Processing System with Failure Recovery - Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors. | 11-07-2013 |

20080301518 | LDPC Check Matrix Generation Method, Check Matrix Generator, and Code Retransmission Method - A check matrix generation method for generating a check matrix H | 12-04-2008 |

20140281788 | SYSTEMS AND METHODS FOR DECODING USING PARTIAL RELIABILITY INFORMATION - Systems and methods are provided for decoding data. A decoder receives a plurality of variable node values for a plurality of variable nodes and processed reliability data for at least a subset of the plurality of variable nodes. Circuitry updates the variable node values based on the variable node values and the processed reliability data. The processed reliability data represents a version of the reliability data for at least the subset of the plurality of variable nodes. | 09-18-2014 |

20140019821 | ERROR CORRECTING DECODING APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK CODES | 01-16-2014 |

20140019820 | ECC POLAR CODING AND LIST DECODING METHODS AND CODECS - A method of decoding data encoded with a polar code and devices that encode data with a polar code. A received word of polar encoded data is decoded following several distinct decoding paths to generate a list of codeword candidates. The decoding paths are successively duplicated and selectively pruned to generate a list of potential decoding paths. A single decoding path among the list of potential decoding paths is selected as the output and a single candidate codeword is thereby identified. In another preferred embodiment, the polar encoded data includes redundancy values in its unfrozen bits. The redundancy values aid the selection of the single decoding path. A preferred device of the invention is a cellular network device, (e.g., a handset) that conducts decoding in accordance with the methods of the invention. | 01-16-2014 |

20120278678 | FORWARD ERROR CORRECTION FOR A DATA FLOW ASSOCIATED WITH A CONNECTIONLESS PACKET NETWORK SERVICE - Examples are disclosed for forwarding or receiving a data flow associated with a connectionless packet network service. In some examples the data flow may have been split into a plurality of data streams separately or jointly including forward error correction. | 11-01-2012 |

20120246534 | APPARATUS AND METHOD FOR TRANSMITTING SIGNAL USING BIT GROUPING IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed. | 09-27-2012 |

20110078535 | CHANNEL EQUALIZER AND METHOD OF PROCESSING BROADCAST SIGNAL IN DTV RECEIVING SYSTEM - A channel equalizer includes a first transformer, an estimator, an average calculator, a second transformer, a coefficient calculator, a compensator, and a third transformer. The first transformer converts normal data into frequency domain data, where a known data sequence is periodically repeated in the normal data. The estimator estimates channel impulse responses (CIR) during known data intervals adjacent to each normal data block. The average calculator calculates an average value of the CIRs. The second transformer converts the average value into frequency domain data. The coefficient calculator calculates equalization coefficients using the average value, and the compensator compensates channel distortion of each normal data block using the coefficients. The third transformer converts the compensated data block into time domain data. | 03-31-2011 |

20110246849 | Reducing Power Consumption In An Iterative Decoder - A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal. | 10-06-2011 |

20100083070 | SENDING AND RECEIVING METHOD AND APPARATUS FOR IMPLEMENTING SERVICE DATA RECOVERY - A sending method, a receiving method, a sending apparatus, and a receiving apparatus for implementing service data recovery are disclosed, a channel protection method for channels which fail, and a channel protection system with the corresponding sending apparatus and receiving apparatus are disclosed. The channel protection method includes: performing in-band redundancy coding for each service channel that transmits service information; using at least one out-band channel as a protection channel; performing error correction for the service channel through in-band redundancy coding when the service channel generates random or correctible errors; and correcting errors of the service channel through a protection channel when the service channel fails or generates non-correctible errors. | 04-01-2010 |

20100083069 | Selecting Erasure Codes For A Fault Tolerant System - A technique for selecting an erasure code from a plurality of erasure codes for use in a fault tolerant system comprises generating a preferred set of erasure codes based on characteristics of the codes' corresponding Tanner graphs. The fault tolerances of the preferred codes are compared based at least on the Tanner graphs. A more fault tolerant code is selected based on the comparison. | 04-01-2010 |

20100083068 | Allocation Of Symbols Of An Erasure Code Across A Plurality Of Devices - A technique is provided for determining an allocation of the symbols of an erasure code across a plurality of devices. A list of erasure patterns is provided for the erasure code and, based on the list, minimal erasures of minimal weight are identified for the code's symbols. Precedences of the symbols are determined based on the size of the corresponding MEMW. An allocation of the symbols across a plurality of devices is determined based on the precedences. | 04-01-2010 |

20100306615 | Receiving Apparatus, Receiving Method and Program, and Receiving System - Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode an low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section. | 12-02-2010 |

20100306613 | METHOD OF MULTIUSER PRECODING AND SCHEDULING AND BASE STATION FOR IMPLEMENTING THE SAME - The present invention provides a method of multiuser precoding and scheduling, comprising: feeding channel state information (CSI) and statistic properties of CSI error back to a base station (BS) from a user equipment (UE); generating multiuser precoding matrix and scheduling scheme by the BS, according to the feedback CSI and the statistic properties of CSI error; and performing multiuser precoding and scheduling on user data by using the generated multiuser precoding matrix and scheduling scheme. | 12-02-2010 |

20090313525 | METHOD OF DECODING BY MESSAGE PASSING WITH SCHEDULING DEPENDING ON NEIGHBOURHOOD RELIABILITY - The invention relates to an iterative method by message passing for decoding of an error correction code that can be displayed in a bipartite graph comprising a plurality of variable nodes and a plurality of check nodes. For each iteration in a plurality of decoding iterations of said method: | 12-17-2009 |

20090313523 | ENCODERS AND METHODS FOR ENCODING DIGITAL DATA WITH LOW-DENSITY PARITY CHECK MATRIX - A method for encoding digital data with a low-density parity check (LDPC) matrix includes: indirectly storing a non-regular portion of the LDPC matrix by storing a plurality of indices corresponding to a plurality of non-zero sub-matrices of the non-regular portion, and by storing a plurality of distance/location parameters respectively corresponding to numbers of zero sub-matrices between adjacent non-zero sub-matrices of the non-regular portion or respectively corresponding to distances between adjacent non-zero sub-matrices of the non-regular portion; generating at least one address according to at least one distance/location parameter; accessing information bits corresponding to the address; and recovering at least one element of the LDPC matrix according to at least one index and the information bits to encode the digital data according to the LDPC matrix. | 12-17-2009 |

20130198581 | METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) CODING FOR SCRAMBLED CODED MULTIPLE ACCESS (SCMA) - A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals. | 08-01-2013 |

20130198580 | Symbol Flipping Data Processor - Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector. | 08-01-2013 |

20130227372 | ENCODING APPARATUS AND COMMUNICATION APPARATUS - According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type. | 08-29-2013 |

20120284582 | DECODING APPARATUS AND DECODING METHOD - A decoding apparatus for performing decoding processing of encoded data by using non-binary LDPC codes, includes: a logarithmic Fourier transform processing section, a variable node processing section, an edge coefficient processing section, and a check node processing section, wherein the logarithmic Fourier transform processing section performs Fourier transform processing and logarithmization processing on a probability vector of a symbol of an encoded frame data to output an initial value of logarithmic Fourier domain probability vector, and the variable node processing section, the edge coefficient processing section, and the check node processing section perform iteration processing by using a logarithmic Fourier domain probability vector. | 11-08-2012 |

20130139026 | ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER - The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 05-30-2013 |

20130139025 | CONSTRUCTION OF MULTI RATE LOW DENSITY PARITY CHECK CONVOLUTIONAL CODES - The present disclosure is directed to a device that allows the construction of multi-rate accumulative LDPC convolutional codes (LDPC CCs) based on a mother code with an arbitrary code rate. Related methods for constructing the multi-rate ALDPC-CCs are also disclosed. In one embodiment the multi rate ALDPC-CC includes an encoder for generating a first part of a codeword according to an LDPC code having a first code rate. A plurality of programmable accumulators is coupled to the encoder. The parity bit sequence produced at the output of the programmable accumulators is combined with the first part of the codeword to generate the codeword. The codeword has a second code rate that is lower than the first rate of the LDPC code. The second code rate is defined by the number of accumulators being enabled to connect to the encoder. Puncturing and rate matching techniques can further adjust the coder rate of the second codeword to a higher rate. | 05-30-2013 |

20130311845 | SYSTEMS AND METHODS FOR NON-BINARY LDPC ENCODING - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 11-21-2013 |

20110107173 | APPARATUS AND METHOD FOR GENERATING A PARITY CHECK MATRIX IN A COMMUNICATION SYSTEM USING LINEAR BLOCK CODES, AND A TRANSMISSION/RECEPTION APPARATUS AND METHOD USING THE SAME - A method and apparatus are provided for generating a parity check matrix used to generate a linear block code in a communication system. The method includes determining a basic parameter of a second parity check matrix satisfying a rule predetermined with respect to a given first parity check matrix, generating a submatrix corresponding to a parity part of the second parity check matrix, using the basic parameter; and generating a submatrix corresponding to an information word part of the second parity check matrix, using the first parity check matrix and the basic parameter. | 05-05-2011 |

20110307756 | RATE-COMPATIBLE PROTOGRAPH LDPC CODES - Digital communication coding methods resulting in rate-compatible low density parity-check (LDPC) codes built from protographs. Described digital coding methods start with a desired code rate and a selection of the numbers of variable nodes and check nodes to be used in the protograph. Constraints may be set to satisfy a linear minimum distance growth property for the protograph. All possible edges in the graph are searched for the minimum iterative decoding threshold and the protograph with the lowest iterative decoding threshold is selected. Protographs designed in this manner may be used in decode and forward relay channels. | 12-15-2011 |

20110307755 | STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODE - A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[H | 12-15-2011 |

20110307754 | FAMILY OF LDPC CODES FOR VIDEO BROADCASTING APPLICATIONS - A family of quasi cyclic irregular low density parity check codes for video broadcasting applications. The parity check matrices of the constructed low density parity check codes have quasi-cyclic structures to facilitate hardware implementation and have proper check/bit degree distributions to offer frame error rate performance lower than 10 | 12-15-2011 |

20120124445 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed. | 05-17-2012 |

20120036409 | EFFICIENT ENCODING AND DECODING METHODS FOR REPRESENTING SCHEDULES AND PROCESSING FORWARD ERROR CORRECTION CODES - A sequence of symbol operations (a “schedule representation”) within a data storage device, wherein the operations are those used to process encoding or decoding operations of a forward error correction code (an “FEC code”) upon an arbitrary block of data of a given size (where size can be measured in numbers of symbols). The method is such that the schedule representation can be used to direct the processing of these operations upon a block of data in a way that is computationally efficient. Preferably, the same method can be applied to represent schedules derived from multiple different algorithms for the encoding or decoding of a code or for multiple different codes. | 02-09-2012 |

20140019819 | RECEIVER AND RECEIVING METHOD - According to an embodiment, a receiver includes a generation unit and a scheduler. The generation unit generates a convergence indicator for evaluating a convergence status of the iterative decoding process based on reliability information. The scheduler controls execution of local iteration includes the iterative decoding process terminates and controls execution of global iteration includes alternation between a symbol de-mapping process and an iterative decoding process, based on the convergence indicator. | 01-16-2014 |

20110126076 | SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES - An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates. | 05-26-2011 |

20110126075 | ROM LIST-DECODING OF NEAR CODEWORDS - Certain embodiments of the present invention are methods for the organization of trapping-set profiles in ROM and for the searching of those profiles during (LDPC) list decoding. Profiles are ranked by dominance, i.e., by their impact on the error-floor characteristics of a decoder. More-dominant trapping-set profiles contain information about both unsatisfied check nodes (USCs) and mis-satisfied check nodes (MSCs), while less-dominant trapping-set profiles contain information about only USCs. Trapping-set profile information is organized into a number of linked, hierarchical data tables which allow for the rapid location and retrieval of most-dominant matching trapping-set profiles using a pointer-chase search. | 05-26-2011 |

20110126073 | Error Correction in an Electronic Circuit - An electronic circuit has a data producing circuit ( | 05-26-2011 |

20150082112 | LOW DENSITY PARITY CHECK ENCODER AND ENCODING METHOD - The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes. | 03-19-2015 |

20150082113 | TRANSMITTING APPARATUS, AND PUNCTURING METHOD THEREOF - There is provided a transmitting apparatus. The transmitting apparatus includes an encoder configured to perform Low Density Parity Check (LDPC) encoding with respect to input data, based on a parity check matrix, a parity interleaver configured to interleave parity bits from among LDPC codewords generated by the LDPC encoding, and a puncturer configured to puncture at least a part of the interleaved parity bits, and the puncturer groups the parity bits based on an interval at which a pattern of columns is repeated in an information word sub matrix constituting the parity check matrix and perform puncturing based on the number of punctured parity bits and a position of punctured parity bit groups from among the grouped parity bit groups. | 03-19-2015 |

20120060070 | MODULATION - FORWARD ERROR CORRECTION (MFEC) CODES AND METHODS OF CONSTRUCTING AND UTILIZING THE SAME - Embodiments of the present invention generally relate to binary block transmission codes for high-speed network transmissions. More specifically, embodiments of the present invention relate to bounded-disparity run-length-limited forward error correction codes and methods of constructing and utilizing same. In one embodiment, a method for generating binary block bounded-disparity run-length-limited forward error correction transmission codes comprises selecting an existing base code, deriving a sub-code from the existing base code, having properties indicated by disparity bound, run-length limit and minimum distance, ascertaining a plurality of codewords and control characters from within the sub-code, encoding Messages to be transmitted with at least one codeword from the plurality of codewords, transmitting codewords from a transmitter to a receiver, and decoding the codewords into Messages. | 03-08-2012 |

20120060069 | GENERATION AND APPLICATION OF A SUB-CODEBOOK OF AN ERROR CONTROL CODING CODEBOOK - There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding. | 03-08-2012 |

20110173510 | Parallel LDPC Decoder - An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations. | 07-14-2011 |

20100115371 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding - Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows. | 05-06-2010 |

20100064194 | REMOTE COMMUNICATION METHOD OF A NETWORK - A remote communication method of a network includes a main controller and a plurality of control units, wherein each control unit is serially connected to the main controller and the control unit at next stage through a transmission terminal and a transmitter. Each control unit receives the data sent from the main controller and identifies the received data as one of a first, a second and a third packet. If it is the first packet and the main controller attempts to read data from each control unit, a switch in the control unit is turned on and a response data is transmitted to the main controller. If it is the second packet and a connection index is equal to a target unit address, then data is written to a corresponding single control unit. If it is the third packet and a target unit address is zero, data is written to all control units. | 03-11-2010 |

20120084618 | JOINTLY ENCODING A SCHEDULING REQUEST INDICATOR AND ACKNOWLEDGMENTS/NEGATIVE ACKNOWLEDGMENTS - A User Equipment (UE) configured for jointly encoding a Scheduling Request Indicator (SRI) and Acknowledgments/Negative Acknowledgments (ACK/NACKs) is disclosed. The UE includes a processor and instructions stored in memory. The UE generates a Scheduling Request Indicator (SRI) bit and a plurality of Acknowledgement/Negative Acknowledgement (ACK/NACK) bits. The UE also encodes the SRI bit and the plurality of ACK/NACK bits with unequal error protection to generate a jointly-encoded SRI and ACK/NACK message and transmits the jointly-encoded SRI and ACK/NACK message. | 04-05-2012 |

20110191650 | Cyclic Shift Device, Cyclic Shift Method, LDPC Decoding Device, Television Receiver, and Reception System - The present invention relates to a cyclic shift device, a cyclic shift method, an LDPC decoding device, a television receiver, and a reception system, whereby reduction in size of a device can be realized. | 08-04-2011 |

20090070652 | APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION SYSTEM USING VARIABLE-LENGTH LDPC CODES - A method and apparatus for generating Low-Density Parity Check (LDPC) codes of various block lengths from a structured LDPC code in a communication system is provided. To support various block lengths, predefined rules are applied to a parity check matrix of an LDPC code, and then shortening is selectively applied to the parity check matrix. Subsequently, if information data bits are input, the input data information bits are encoded into an LDPC codeword by using the parity check matrix according to a preset encoding scheme, and then the encoded LDPC codeword is transmitted after puncturing is selectively applied. | 03-12-2009 |

20090070651 | STORAGE SUBSYSTEM CAPABLE OF ADJUSTING ECC SETTINGS BASED ON MONITORED CONDITIONS - A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system. To enable blocks of data to be properly checked when read from memory, the storage subsystem stores ECC metadata indicating the particular error correction setting used to store particular blocks of data. The storage subsystem may be in the form of a solid-state non-volatile memory card or drive that attaches to the host system. | 03-12-2009 |

20100107034 | INFORMATION PROCESSING DEVICE, PROGRAM AND RECORDING MEDIUM - The present invention intends to hold safely string information such as secret information, or the like, and also to lessen user's burden of storing the information in connection to the string information. In registering the secret information, a coding section | 04-29-2010 |

20130283118 | LAUNCH DELAY OFFSET DATA FLOW PROTECTION - A signal protector utilizes a dual data path delay offset enabling signal recovery on both paths following simultaneous data loss on both paths. | 10-24-2013 |

20120166905 | METHOD AND APPARATUS FOR CONTROLLING DECODING IN RECEIVER - Methods and apparatus are provided for controlling decoding in a receiver. A codeword is received and decoded. It is determined whether the decoding is a decoding success or a decoding failure. A number of unreliable bits of the codeword is determined when the decoding is the decoding failure. Iterative decoding is performed when the number of unreliable bits is less than a first threshold value. | 06-28-2012 |

20120089884 | ERROR CORRECTION ENCODING APPARATUS, DECODING APPARATUS, ENCODING METHOD, DECODING METHOD, AND PROGRAMS THEREOF - Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain. | 04-12-2012 |

20120089883 | Systems and Methods for Error Correction Using Irregular Low Density Parity Check Codes - Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated. | 04-12-2012 |

20140208181 | ZERO SUM SIGNALING IN A DIGITAL SYSTEM ENVIRONMENT - Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling. | 07-24-2014 |

20140089757 | LDPC Decoder With Fractional Local Iterations - The present inventions are related to systems and methods for an LDPC decoder with fractional local iterations that may be used in a data processing system with an LDPC decoder and data detector to better balance processing times in the LDPC decoder and data detector. | 03-27-2014 |

20100077277 | Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes - Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit. | 03-25-2010 |

20100077278 | Method and System for Authenticating Reliable Biometric Data - A method for authenticating biometric data. Comprising of a processor that measures the reliability of each bit in enrollment biometric data; by arranging the bits; encoding the enrollment biometric data in the decreasing order to produce an enrollment syndrome; arranging the bits in the authentication biometric; decoding the authentication enrollment syndrome to produce an estimate of the enrollment biometric data; generating an output signal indicating that the estimate of the authentication biometric data is substantially the same as the enrollment biometric data. | 03-25-2010 |

20150019931 | ERROR CORRECTING DECODING APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK CODES | 01-15-2015 |

20130173982 | METHOD OF DECODING LDPC CODE FOR PRODUCING SEVERAL DIFFERENT DECODERS USING PARITY-CHECK MATRIX OF LDPC CODE AND LDPC CODE SYSTEM INCLUDING THE SAME - Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit. | 07-04-2013 |

20130173981 | NON-BINARY QC-LDPC CODE DECODING DEVICE AND ASSOCIATED METHOD - A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j | 07-04-2013 |

20100070824 | System and Method for Improving Transport Protocol Performance in Communication Networks Having Lossy Links - Providing transport protocol within a communication network having a lossy link. The receiver distinguishes between packets received with non-congestion bit errors and packets having been not at all received due to congestion. When packets are received with non-congestion bit errors, the receiver sends selective acknowledgments indicating that the packets were received with bit errors while suppressing duplicate acknowledgments to prevent the invocation of a congestion mechanism. | 03-18-2010 |

20100070823 | METHOD AND DEVICE FOR INFORMATION BLOCK CODING AND SYNCHRONIZATION DETECTING - A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting may be performed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization may be effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization. | 03-18-2010 |

20100070822 | METHOD AND APPARATUS FOR ENCODING AND DECODING DATA - The present invention relates to the communication field, and discloses a method and an apparatus for encoding, decoding, receiving and transmitting data to improve the encoding gain of the FEC encoding without increasing transmission overhead. In the present invention, no FEC encoding is performed for the minor bits in the block header of the information blocks. The block header may be a sync header. The bit indicative of the data type serves as a major bit, and is protected through FEC encoding; the bit for the only purpose of block synchronization serves as a minor bit, which is not involved in the FEC encoding and decoding. When the buffered data are deficient, padding blocks are padded into the buffer to trigger the FEC encoding in time; after the FEC encoding, the padding block is removed from the encoding result, thus avoiding transmission of unnecessary data. | 03-18-2010 |

20100070821 | METHOD AND APPARATUS FOR DETECTING FREE PAGE AND A METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE USING THE METHOD AND APPARATUS FOR DETECTING FREE PAGE - A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value. | 03-18-2010 |

20100070820 | CODING APPARATUS, CODING METHOD, CODING AND DECODING APPARATUS, AND COMMUNICATION APPARATUS - When carrying out puncturing of some redundant bits in an LDPC code having a check matrix of QC structure and LDGM structure, a puncture rule for preventing redundant bits which are chained to one another from being punctured is set up, and some redundant bits out of an LDPC-coded signal are punctured out of the LDPC-coded signal according to the puncture rule. As a result, redundant bits which are chained to one another can be left. | 03-18-2010 |

20100070819 | Channel adaptive iterative turbo decoder system and method - A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits. | 03-18-2010 |

20100070818 | NODE PROCESSOR FOR USE WITH LOW DENSITY PARITY CHECK DECODER USING MULTIPLE VARIABLE NODE DEGREE DISTRIBUTION CODES - A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes. | 03-18-2010 |

20130185610 | JOINT ENCODING AND DECODING METHODS FOR IMPROVING THE ERROR RATE PERFORMANCE - Joint encoding and decoding methods for improving the error rate performance are described. In one aspect, the systems and methods determine values and positions of L desired symbols. In encoding unit receives data symbols for encoding. The encoding unit calculates, responsive to receiving the data symbols, values and positions of H help symbols. The encoding unit inserts the help symbols into the data symbols at respective help symbols positions, thereby generating new data symbols. Encoding unit encodes the new data symbols to produce a codeword C′ that contains the L desired symbols. The codeword C′ is communicated to a decoder that is instructed to explore some or all L desired symbols in C′. | 07-18-2013 |

20120096327 | JOINT CARRIER PHASE ESTIMATION AND FORWARD ERROR CORRECTION - Methods and systems for processing an optical signal in a communication system are disclosed. The disclosed methods yield benefits for estimation and tracking of carrier phase of received signals at a digital coherent receiver without the use of differential coding. Specifically, phase ambiguity is removed by calculating the slope of the CPE at a location where the CPE begins to lose track of the received carrier phase signal. As such, a CPE offset adjustment may be applied in accordance with the calculated slope to reduce the number of ones and zeros corrected by a FEC decoder. Thus, the FEC aided CPE scheme may be a feed forward scheme that requires no training. | 04-19-2012 |

20130173983 | GENERATION OF PROGRAM DATA FOR NONVOLATILE MEMORY - A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data. | 07-04-2013 |

20130104000 | NIBBLE ENCODING FOR IMPROVED RELIABILITY OF NON-VOLATILE MEMORY - A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles. | 04-25-2013 |

20140095954 | MODIFIED TARGETED SYMBOL FLIPPING FOR NON-BINARY LDPC CODES - A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set. | 04-03-2014 |

20130124938 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE IN A MULTIMEDIA COMMUNICATION SYSTEM - An apparatus and method are provided for transmitting and receiving a quasi-cyclic Low Density Parity Check (LDPC) code in a multimedia communication system. In the method, a signal transmission apparatus generates a quasi-cyclic LDPC code, and transmits the quasi-cyclic LDPC code to a signal reception apparatus. The quasi-cyclic LDPC code is generated by encoding an information word vector using a child parity check matrix, generated by performing one of a scaling operation, a row separation operation, and a row merge operation on a parent parity check matrix. In the scaling operation, a size of the child parity check matrix is determined. In the row separation operation, each of rows included in the parent parity check matrix is separated. In the row merge operation, the rows included in the parent parity check matrix are merged. | 05-16-2013 |

20130124939 | METHOD AND DEVICE FOR PADDING OPTIMIZATION OF SEGMENTED TURBO CODES - A method for forming a bit sequence having a number of M bits from a bit sequence having a number of N bits, wherein M/2 | 05-16-2013 |

20130238951 | HOLEVO CAPACITY ACHIEVING JOINT DETECTION RECEIVER - An optical receiver may include a unitary transformation operator to receive an n-symbol optical codeword associated with a codebook, and to perform a unitary transformation on the received optical codeword to generate a transformed optical codeword, where the unitary transformation is based on the codebook. The optical receiver may further include n optical detectors, where a particular one of the n optical detectors is to detect a particular optical symbol of the transformed optical codeword, and to determine whether the particular optical symbol corresponds to a first optical symbol or a second optical symbol. The optical receiver may also include a decoder to construct a codeword based on the determinations, and to decode the constructed codeword into a message using the codebook. The optical receiver may attain superadditive capacity, and, with an optimal code, may attain the Holevo limit to reliable communication data rates. | 09-12-2013 |

20130132790 | Probability-Based Multi-Level LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for probability-based multi-level LDPC decoding. For example, in one embodiment an apparatus includes a horizontal updater in a low density parity check decoder operable to iteratively perform row processing to update probabilities of multi-level symbol values, a vertical updater in the low density parity check decoder operable to iteratively perform column processing to update the probabilities of the multi-level symbol values, and a check sum calculation circuit operable to calculate total soft values for the multi-level symbol values. | 05-23-2013 |

20150026535 | APPARATUS AND METHOD FOR GENERATING INTERLEAVER INDEX - Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider. | 01-22-2015 |

20130159809 | Error Detection And Correction Of A Data Transmission - Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word. | 06-20-2013 |

20130246879 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 09-19-2013 |

20130246882 | DECODING APPARATUS AND DECODING METHOD FOR DECODING LDPC-ENCODED DATA - A min-sum processing unit executes a min-sum algorithm on input data so as to alternately execute check node processing in which an extrinsic value ratio is updated based on prior value ratios and variable node processing in which a prior value ratio is updated based on the extrinsic value ratios. Here, an initializing unit calculates the total product of the signs of the prior value ratios associated with the row to be processed. A deriving unit derives the sign for an extrinsic value ratio associated with the row to be processed, based on the sign of the prior value ratio that is unused in the updating of the extrinsic value ratio and the total product of the signs thus calculated. An updating unit updates an extrinsic value ratio associated with the row to be processed, using the sign thus derived. | 09-19-2013 |

20130246881 | Apparatus and Method for Reconstructing a Bit Sequence with Preliminary Correction - A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF A | 09-19-2013 |

20130246878 | STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING - A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device. | 09-19-2013 |

20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 09-19-2013 |

20110078534 | METHOD AND APPARATUS FOR OBFUSCATING SLICE NAMES IN A DISPERSED STORAGE SYSTEM - A method begins by a processing module receiving a data segment for dispersed storage. The method continues with the processing module encoding the data segment in accordance with an error coding dispersed storage function to produce a plurality of error coded data slices. The method continues with the processing module generating a slice name for an error coded data slice of the plurality of error coded data slices, wherein the slice name includes a dispersed storage routing information section and a data identification section. The method continues with the processing module performing a securing function on at least the data identification section to produce a secure data identification section. The method continues with the processing module replacing, within the slice name, the data identification section with the secure data identification section to produce a secure slice name. | 03-31-2011 |

20130254617 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder | 09-26-2013 |

20140095955 | Efficient Way to Construct LDPC Code by Comparing Error Events Using a Voting Based Method - A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level. | 04-03-2014 |

20120226955 | METHOD AND APPARATUS FOR FORWARD ERROR CORRECTION (FEC) IN A RESOURCE-CONSTRAINED NETWORK - An electronic device may utilize or support adaptive use of forward error correction (FEC) in a resource-constrained network. The adaptive FEC use may comprise determining whether use of FEC encoding in transmissions from another electronic device to the electronic device is necessary, desirable, and/or feasible, and when use of FEC encoding is deemed feasible and either necessary or desirable, instructing the another electronic device to utilize FEC encoding when transmitting signals destined for the electronic device. Use of FEC encoding may be determined to be feasible, necessary and/or desirable based on power loss associated with the communications from the another electronic device; based on determination of latency associated with the communications from the another electronic device; and/or based on power and/or processing related resources in the electronic device. The electronic device may separately and selectively apply FEC encoding to transmissions to the another electronic device. | 09-06-2012 |

20140215286 | SOFT ERROR PROTECTION DEVICE - A soft error protection device is disclosed, which comprises a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level. | 07-31-2014 |

20140215287 | DECODER, RECEPTION APPARATUS, DECODING METHOD, AND RECEPTION METHOD - Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. | 07-31-2014 |

20140215285 | INTEGRATED-INTERLEAVED LOW DENSITY PARITY CHECK (LDPC) CODES - Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H | 07-31-2014 |

20150033092 | CHAIN ENCODING AND DECODING OF HIGH SPEED SIGNALS - A method of recovering a value of a symbol received through an optical communications system. A multi-bit estimate of the symbol is subdivided into a first part and a second part, each part including at least one respective bit of the estimate. A most likely value of the first part is detected. The most likely value of the first part is processed using a Forward Error Correction (FEC) decoder to generate a corrected first part value, which is used to detect a most likely value of the second part. The most likely value of the second part is then processed by the FEC decoder to generate a corrected second part, which is combined with the corrected first part to recover the value of the symbol. | 01-29-2015 |

20150033093 | ADVANCE CLOCKING SCHEME FOR ECC IN STORAGE - A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal. | 01-29-2015 |

20090049360 | OPTIMAL CIRCULAR BUFFER RATE MATCHING FOR TURBO CODE - Optimal circular buffer rate matching for turbo code. An offset index, δ, of 3 and a skipping index, σ, of 3 is employed in accordance with circular buffer rate matching. This allows less puncturing of information bits and more puncturing of redundancy/parity bits (e.g., which can provide for a higher rate). Multiple turbo codes may be generated from a mother code such that each generated turbo code can be employed to encode information bits. For example, a first turbo coded signal can be generated using a first turbo code generated from the mother code, and a second turbo coded signal can be generated using a second turbo code generated from the mother code. Any of these turbo coded signal can be decoded using parallel decoding processing or a single turbo decoder (when each turbo coded signal undergoes processing to transform it back to the mother code format). | 02-19-2009 |

20130091399 | HIGH-SPEED LONG CODEWORD QC-LDPC SOFT DECISION DECODER - A Quasi-Cyclic, LDPC, large girth, soft-decision decoder and accompanying methods. | 04-11-2013 |

20110087947 | Regenerative Relay System and Regenerative Relay Apparatus - A regenerative relay method includes the steps of: i) calculating an error rate of a transmission path between the first half apparatus and a main apparatus; ii) calculating an error rate of a transmission path between the main apparatus and the latter apparatus; iii) adding the error rates; iv) selecting the error correction code and data before the error is corrected in the main apparatus so as to be supplied to the latter apparatus if the added error rates are lower than a designated error correction threshold; and v) selecting data after the error is corrected in the main apparatus and the other error correction code generated from the data so as to be supplied to the latter apparatus if the added error rates are higher than the designated error correction threshold. | 04-14-2011 |

20130061107 | Multi-Level LDPC Layer Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding. | 03-07-2013 |

20130111293 | Storing data in a dispersed storage network | 05-02-2013 |

20130111290 | Systems and Methods for Ambiguity Based Decode Algorithm Modification | 05-02-2013 |

20140032989 | Symbol Selective Scaling With Parity Forcing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing. | 01-30-2014 |

20140157077 | DECODER BASED DATA RECOVERY - Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to decode codewords and decoder firmware configured to control one or more decoding parameters of the decoder. The decoder includes a recovery unit configured to store recovery instructions. The decoder is further configured to execute the stored recovery instructions without interaction with the decoder firmware when the decoding fails. | 06-05-2014 |

20130275828 | CODE-ASSISTED ERROR-DETECTION TECHNIQUE - A circuit, wherein an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. An error-detection circuit coupled to the encoder circuit generates and stores error-detection information associated with the set of M symbols, facilitating subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. A receiver circuit receives feedback information from the other circuit, which includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Control logic performs remedial action based on the feedback information. | 10-17-2013 |

20130326302 | Error Injection for LDPC Retry Validation - The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation circuit in the data processing circuit is operable to inject errors in the data set to trigger the at least one retry feature. | 12-05-2013 |

20130332792 | Symbol mapping for binary coding - The present disclosure presents symbol mapping for any desired error correction code (ECC) and/or uncoded modulation. A cross-shaped constellation is employed to perform symbol mapping. The cross-shaped constellation is generated from a rectangle-shaped constellation. Considering the rectangle-shaped constellation and its left hand side, a first constellation point subset located along that left hand side are moved to be along a top of the cross-shaped constellation while a second constellation point subset located along that left hand side are moved to be along a bottom of the cross-shaped constellation. For example, considering an embodiment having four constellation point subsets along the left hand side of the rectangle-shaped constellation, two of those subsets are moved to be along the top of the cross-shaped constellation while two other subsets of the constellation points along the left hand side are moved to be along the bottom of the cross-shaped constellation. | 12-12-2013 |

20130031437 | TIME VARYING DATA PERMUTATION APPARATUS AND METHODS - Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations. | 01-31-2013 |

20130332791 | DATA PROTECTION METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged. | 12-12-2013 |

20130332793 | ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS - A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output. | 12-12-2013 |

20130283117 | LOW-DENSITY PARITY-CHECK CODE DECODER AND DECODING METHOD - Provided is a low-density parity-check (LDPC) code decoder and a decoding method. The decoding method may include calculating a message of a variable node (V-node), calculating a message of a check node (C-node), and calculating log-likelihood ratio (LLR) data of a channel using the message of the V-node and the message of the C-node. | 10-24-2013 |

20130283119 | Method and Apparatus for Elementary Updating a Check Node During Decoding of a Block Encoded with a Non-binary LDPC Code - Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising n | 10-24-2013 |

20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |

20130283116 | METHOD AND SYSTEM FOR ERROR CORRECTION IN TRANSMITTING DATA USING LOW COMPLEXITY SYSTEMATIC ENCODER - A systematic encoder such as a systematic polar encoder for channel encoding to ameliorate the effects of noise in a transmission channel. The codeword carries a data word to be transmitted transparently, and also carries a parity part derived from the data word and a fixed word. Implementations advantageously reduce coding complexity to the order of N log(N), wherein N is the dimension of a matrix of the n th Kronecker power associated with a matrix effectively employed by the encoder. | 10-24-2013 |

20140157076 | DATA ERROR-DETECTION SYSTEM AND METHOD THEREOF - The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved. | 06-05-2014 |

20140351667 | METHOD OF DECODING A CORRECTING CODE, FOR EXAMPLE A TURBO-CODE, BY ANALYSIS OF THE EXTENDED SPECTRUM OF THE WORDS OF THE CODE - An improved decoding method is provided making it possible to solve the problem of the error floor of a turbo-code or of an LDPC code, or more generally of a correcting code from the family of “turbo-like codes”, while preserving the same spectral efficiency, without any decrease in the useful throughput of the encoded stream. This result is obtained by an identification, on input to the decoder, of the bits on which an error has a strong impact, and a modification of the likelihoods corresponding to these bits so as to improve the convergence of the decoder. | 11-27-2014 |

20150095735 | Integrated-Interleaved Low Density Parity Check (LDPC) Codes - Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H | 04-02-2015 |

20140053039 | TIME VARYING DATA PERMUTATION APPARATUS AND METHODS - Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations. | 02-20-2014 |

20110099450 | Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof - An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits. | 04-28-2011 |

20110099448 | SPLIT-ROW DECODING OF LDPC CODES - A method of decoding a low density parity check (LDPC) encoded block, with the LDPC code being defined by a parity check matrix including rows, includes processing the rows of the parity check matrix. The processing includes updating data in the rows using a split-row decoding algorithm. The updating includes partitioning each row into a plurality of partitions, and determining for each partition a first local minimum of the data of the partition. The method also includes comparing for each partition the first local minimum with a threshold, and updating at least some of the data of all partitions of the row using the local minimums or the threshold depending on the results of the comparing. | 04-28-2011 |

20140173374 | METHODS AND APPARATUS FOR ERROR CODING - Methods and apparatus are described for implementing low-density parity-check codes. These may be used in electronic communications, such as wireless communication systems. A number of processes are implemented for each vector in a plurality of vectors of a coding matrix associated with a low-density parity-check code. These include retrieving, from one or more interleavers, one or more addresses, using the or each retrieved address to retrieve one or more symbols from data and determining a parity-check operation corresponding to a particular said vector using said one or more symbols retrieved from said data. This enables an encoded block to be generated using said data and each of the parity-check operations. It also enables a received code vector to be decoded. | 06-19-2014 |

20130139021 | ERROR CORRECTION CODING (ECC) DECODE OPERATION SCHEDULING - A method includes receiving, at an error correction coding (ECC) controller, information indicating one or more data chunks to be decoded, populating a schedule according to an order of decoding of the data chunks, and initiating decode of the data chunks according to the schedule. | 05-30-2013 |

20120317456 | Method and Apparatus for N+1 Packet Level Mesh Protection - Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN−1, to generate a codeword that includes the message symbols, m0 through mN−1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN−1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN−1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN−1, and the one or more check symbols through the linear feedback shift register. | 12-13-2012 |

20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |

20140059402 | METHOD AND APPARATUS FOR CONTROLLING THE DECODING OF CODEWORDS RECEIVED BY A LINEAR BLOCK CODE PIPELINED DECODER FROM AN INPUT BUFFER - A computer implemented method of controlling the decoding of codewords received by a linear block code pipelined decoder from an input buffer, the pipelined decoder comprising at least two decoding stages. The method comprises iteratively: loading the decoding stages of the pipelined decoder, executing a decoding step, determining the number of residual errors in the codewords and outputting error free codewords. The method allows the different decoding stages to be loaded with any codeword coming from the buffer or from any decoding stage of the decoder. Accordingly, the occupation rate of the pipeline is improved. | 02-27-2014 |

20140108880 | Systems and Methods for Enhanced Local Iteration Randomization in a Data Decoder - systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. | 04-17-2014 |

20140223253 | METHOD OF EARLY TERMINATION OF CHANNEL DECODING BY RE-ENCODING - A method of early termination for channel decoding by re-encoding according to the invention at least includes a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and the encoding unit; by means of the configuration of the above units, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding; the re-encoded words are compared to the decoded codewords by the checking unit; and if they are completely the same, then terminate the decoding action of the decoding unit. It achieves saved power consumption, simplified structure, improved decoding throughput and less hardware complexity. | 08-07-2014 |

20150143194 | REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM - Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector. | 05-21-2015 |

20090019332 | SISO DECODER WITH SUB-BLOCK PROCESSING AND SUB-BLOCK BASED STOPPING CRITERION - The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising: | 01-15-2009 |

20130275827 | Multi-Section Non-Binary LDPC Decoder - Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages. | 10-17-2013 |

20140173373 | DECODING METHOD FOR LOW DENSITY PARITY CHECK AND ELECTRONIC DEVICE USING THE SAME - A decoding method for low density parity check (LDPC) and an electric device using the decoding method are provided. The decoding method includes: receiving a message and executing an iteration decoding to the message; obtaining first belief values of the message in an (i−1) | 06-19-2014 |

20140181612 | LOW DENSITY PARITY CHECK DECODER - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 06-26-2014 |

20130283115 | DATA PROCESSING APPARATUS USING IMPLICIT DATA STORAGE AND A METHOD OF IMPLICIT DATA STORAGE - A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code. | 10-24-2013 |

20140237314 | Systems and Methods for Skip Layer Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. | 08-21-2014 |

20100017679 | RECORDING AND REPRODUCING DATA TO/FROM A RECORDING MEDIUM HAVING A USER DATA AREA AND AN INFORMATION AREA FOR STORING INFORMATION ABOUT THE RECORDING MEDIUM - If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention. | 01-21-2010 |

20100017678 | Hierarchical Trellis Coded Modulation - A system and method for encoding information is disclosed. In one embodiment, information is encoded using a high protection code for the least significant bit and a low protection code for the next three most significant bits. The remaining bits are uncoded. The high protection code may be a turbo code and the low protection code may be a trellis coded modulation code. In this embodiment, the collection of bits is then mapped according to a diagonally shifted QAM constellation technique. | 01-21-2010 |

20100017677 | DECODING DEVICE AND DECODING METHOD - To provide a decoder capable of efficiently dealing with various Z, even when in-block parallel degree is fixed in MP decoding of quasi-cyclic LDPC codes. A reception value aligning device keeps the first S or less reception value data from the block head. If block size Z is not a multiple of S, (S−(Z mod S)) data of the block head are added to the end of the reception value data of the block so that the block size Z is a multiple of S. The block size is written into reception value memory. A message aligning device performs cyclic permutation. If Z is not a multiple of S, the first (S−(Z mod S)) messages from the block output head are added to the end of the output message of the block so that the Z is a multiple of S and is outputted to the message memory. | 01-21-2010 |

20100017676 | DECODING OF LINEAR CODES WITH PARITY CHECK MATRIX - A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol. | 01-21-2010 |

20130311846 | Systems and Methods for Hardware Flexible Low Density Parity Check Conversion - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 11-21-2013 |

20150100845 | TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF - A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part. | 04-09-2015 |

20150100844 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 7/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME - A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). | 04-09-2015 |

20120185746 | METHOD AND APPARATUS OF ENCODING AND DECODING DATA USING LOW DENSITY PARITY CHECK CODE IN A WIRELESS COMMUNICATION SYSTEM - A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’. | 07-19-2012 |

20120185745 | MULTI-CSI (Cyclic Shifted Identity) SUB-MATRIX BASED LDPC (Low Density Parity Check) CODES - Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit. | 07-19-2012 |

20120185744 | LDPC MULTI-DECODER ARCHITECTURES - Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix that corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder, The super-parity-check matrix includes n parity check matrices, each including x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows and ny columns. The numbers n, x, and y are selected so that ny codeword can be processed in single time unit by the high throughput decoder and y codeword bits can be processed in a single time unit by the low throughput decoder. | 07-19-2012 |

20100005362 | SOUND DATA DECODING APPARATUS - A sound data decoding apparatus based on a waveform coding method includes a loss detector, sound data decoder, sound data analyzer, parameter modifying section and sound synthesizing section. The loss detector detects whether a loss exists in a sound data. The sound data decoder decodes the sound data to generate a first decoded sound signal. The sound data analyzer extracts a first parameter from the first decoded sound signal. The parameter modifying section modifies the first parameter based on a result of the detection of loss. The sound synthesizing section generates a first synthesized sound signal by using the modified first parameter. Thus, a deterioration of sound quality is prevented in the error compensation of sound data. | 01-07-2010 |

20090319862 | HIGH SPEED TURBO CODES DECODER FOR 3G USING PIPELINED SISO LOG-MAP DECODERS ARCHITECTURE - A MIMO system with Diversity processing is provided having Turbo Codes Decoders for computing orthogonal signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the Wireless system to deliver data rates from up to 200 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A Turbo Codes Decoder block is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for pipeline operations. In a pipeline mode, a first decoder A decodes block N data from a first source, while a second decoder B decodes block N data from a second source during the same clock cycle. Pipelined max-Log-MAP decoders provide high speed data throughput and one output per clock cycle. | 12-24-2009 |

20080313523 | ENCODING LOW DENSITY PARITY CHECK (LDPC) CODES THROUGH AN LDPC DECODER - An approach is providing for supporting broadcast transmission of low density parity check (LDPC) coded signals. A receiver includes a decoder configured to decode an LDPC signal to output a decoded signal. The decoder is further configured to operate as an encoder; as such, interference cancellation can be implemented by the encoder re-encoded the received decoded signal. The above approach has particular applicability to satellite broadcast systems. | 12-18-2008 |

20150149851 | SYSTEM AND METHOD FOR COMMUNICATING WITH LOW DENSITY PARITY CHECK CODES - The present invention provides an approach for FEC encoding based on intermediate code block lengths not associated with any supported mother FEC code. A first string of k | 05-28-2015 |

20120240003 | Method, Apparatus, Computer Program Product and Device Providing Semi-Parallel Low Density Parity Check Decoding Using a Block Structured Parity Check Matrix - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described. | 09-20-2012 |

20080294960 | MEMORY-EFFICIENT LDPC DECODING - To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes. | 11-27-2008 |

20080294959 | Decoder - An H-ARQ system wherein the transmission of two consecutive, or sequential, blocks of information bits are considered jointly; i.e., one of the blocks of information being embedded within the other one of the blocks of information. If a retransmission for the first block is necessary, the system processes both blocks jointly. The system is provided with cross-packet coding which extends current H-ARQ schemes for point-to-point communications wherein the transmission of two consecutive block of information bits is considered jointly. If a retransmission for the first block is necessary, the system processes both blocks jointly. This allows both blocks to be decoded without errors at the receiver after the retransmission. | 11-27-2008 |

20130132791 | INTERRUPTION CRITERIA FOR BLOCK DECODING - While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified. | 05-23-2013 |

20130132789 | VIDEO TRANSMISSION SYSTEMS AND METHODS OVER CARRIER ETHERNET - The present disclosure provides video transmission systems and methods with video data flows transmitted over a Carrier Ethernet Network at Layer 2 with redundancy in order to provide hitless protection switching and uninterrupted video service delivery, such as during periods of asymmetric congestion or hard network failures. In an exemplary embodiment, the video transmission systems and methods provide the redundancy in a manner similar to 1+1 linear protection with hit-less protection switching. In another exemplary embodiment, the video transmission systems and methods provide encapsulated video signals over Ethernet using standardized Carrier Ethernet frames with additional sequencing information. Optionally, the video transmission systems and methods may also include packet-based forward error correction information for additional resiliency. These video transmission systems and methods provide uninterrupted and error-free video during broadcast despite network events such as fiber breaks, equipment failures, congestion, etc. | 05-23-2013 |

20140258804 | REDUCED UNCORRECTABLE MEMORY ERRORS - Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively. | 09-11-2014 |

20140372826 | APPARATUSES AND METHODS FOR ENCODING AND DECODING OF PARITY CHECK CODES - An encoding apparatus is provided. The encoding apparatus includes: a low density parity check (LDPC) encoder configured to generate an LDPC codeword formed of 16200 bits by performing LDPC encoding based on a parity check matrix, wherein the parity check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix being formed of a plurality of column groups each including 360 columns and being defined as a table indicating a position of one (1) present in each 360-th column. | 12-18-2014 |

20140053038 | Method for Selecting a LDPC Candidate Code - A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk. | 02-20-2014 |

20130139027 | System and Method for Achieving Greater Than 10 Gbit/s Transmission Rates for Twisted Pair Physical Layer Devices - A system and method for achieving greater than 10 Gbit/s transmission rates for twisted pair physical layer devices. An architecture is provided that enables transmission at the next standardized transmission rate over structured cabling. | 05-30-2013 |

20130139023 | Variable Sector Size Interleaver - Various embodiments of the present invention are related to methods and apparatuses for interleaving data, and more particularly to methods and apparatuses for interleaving variably sized blocks of data. For example, in one embodiment an apparatus includes a data partitioner operable to partition the block of data into a real data portion and a missing bits portion. The real data portion is adapted to contain data bits from the variably sized block of data and the missing bits portion is adapted to be filled with a variable number of the data bits. The apparatus also includes at least one local interleaver operable to apply a permutation across each of a plurality of sub-portions of the real data portion and the missing bits portion, and a global interleaver operable to apply a global permutation across the real data portion. | 05-30-2013 |

20150019930 | APPARATUS AND METHOD FOR DESIGNING QUANTUM CODE - Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error channel as at least one binary error by using a standard form codeword stabilized quantum (CWS) code, a code generating unit for generating a binary error-correcting code which corrects the at least one binary error, a word operator generating unit for generating at least one word operator of the CWS code by using the at least one binary error-correcting code, and a codeword generating unit for generating at least one codeword including at least one entangled qubit (ebit) by using the at least one word operator. | 01-15-2015 |

20080235554 | DEVICE AND METHOD FOR IMPROVED LOST FRAME CONCEALMENT - Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame. | 09-25-2008 |

20080229169 | DATA RECOVERY CIRCUIT - A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A second parity generation circuit writes backup data of the actual data with odd parity to the copy region. A read circuit reads data from the actual data region and the copy region. An even parity checker detects a parity error in the actual data based on the data read from the actual data region. An odd parity checker checks whether the data read from the copy region is backup data. | 09-18-2008 |

20110271163 | Method and a device for adapting error protection in a communication network, and a method and device for detecting between two states of a communication network corresponding to different losses of data - A method for adapting error protection in a communication network includes: a step of determining periods of time that are homogeneous as regards the distribution law of losses over the network, a step of classifying the homogeneous periods of time into at least two classes, on the basis of information representing losses over the network and/or representing a corresponding level of protection, during these periods of time, a step of determining a probability of alternation between two of said classes, and a step of selecting a protection strategy on the basis of said probability of alternation. A method of detecting transition between two states of a communication network corresponding to different loss rates of sent data includes: a step of determining a probability of transition, and a step of determining the existence of a transition on the basis of said probability. | 11-03-2011 |

20100287439 | ENCODING METHOD AND DEVICE TO DETERMINE TLDPC CODES - Encoding method ( | 11-11-2010 |

20100287438 | METHOD AN APPARATUS FOR LOW DENSITY PARITY CHECK CODES ENCODING AND DECODING - Certain aspects of the present disclosure relate to a method for generating a single rate or multi-rate highly structured low density parity check, encoding a data stream with the generated LDPC matrix for transmission in a wireless communication system, and for efficient LDPC decoding at a receiver. | 11-11-2010 |

20100287437 | Fast Encoding and Decoding Methods and Related Devices - A method of low latency encoding of an input bit sequence (S | 11-11-2010 |

20100287436 | System for Error Decoding with Retries and Associated Methods - A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue. | 11-11-2010 |

20110276856 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 11-10-2011 |

20110276855 | METHOD AND APPARATUS FOR CHANNEL CODING AND DECODING IN A COMMUNICATION SYSTEM USING A LOW-DENSITY PARITY-CHECK CODE - A channel coding method in a communication system using a Low-Density Parity-Check (LDPC) code. The channel coding method includes determining a degree distribution for a plurality of column groups of an information part and a plurality of column groups of a parity part; determining degrees for the plurality of column groups of the information part based on the degree distribution; determining a shortening order based on the degrees for the plurality of column groups of the information part; generating a parity check matrix based on the shortening order; and performing coding using the generated parity check matrix. | 11-10-2011 |

20110276854 | Methods and Systems for Rapid Error Correction by Forward and Reverse Determination of Coding States - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor. | 11-10-2011 |

20110276853 | TERMINAL DEVICE, TERMINAL DEVICE CONTROL METHOD, AND STORAGE MEDIUM - It is possible to provide a terminal device, a terminal device control method, and a recording medium which enables an error correction without modifying hardware. The terminal device receives a data stream formed in the NAL Unit by a hard decoder based on the H.264 standard. The terminal device includes error correction means which analyzes data encoded in the data stream by software and performs an error correction before inputting the data to the hard decoder. | 11-10-2011 |

20100293430 | DRIVING CIRCUIT FOR DRIVING READING OPERATION OF OPTICAL DRIVE AND METHOD FOR READING INFORMATION FROM OPTICAL DATA STORAGE MEDIUM - The invention provides a method for reading information of an optical data storage medium. First, one sector of the optical data storage medium is obtained. The sector is then decoded to check if the sector is reliable. When the sector is not reliable, a data rescue process referring to spec-defined or pre-defined information of the physical specification of the sector is performed in order to obtain disc fundamental information of the optical data storage medium. | 11-18-2010 |

20100293429 | PACKET INTERLEAVING METHOD - The packet interleaving method includes selecting successive input sets of consecutive input packets (X | 11-18-2010 |

20120284583 | OVERLAPPING SUB-MATRIX BASED LDPC (LOW DENSITY PARITY CHECK) DECODER - Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved. | 11-08-2012 |

20100306617 | DECODER DEVICE, DECODING METHOD AND MAGNETIC DISK DEVICE - According to one embodiment, a decoder device includes a decoder configured to decode a to-be-decoded sequence by performing an iterative decoding process and to perform a parity check of a decoding result using a check matrix, a detector configured to detect that the to-be-decoded sequence is a non-code word based on a parity check result for each row of the check matrix by the decoder, and a controller configured to control the decoder according to a detection result of the detector. | 12-02-2010 |