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Digital data error correction

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714752000 Forward correction by block code 2624
714748000 Request for retransmission 659
714786000 Forward error correction by tree code (e.g., convolutional) 192
714747000 Substitution of previous valid data 25
714797000 Majority decision/voter circuit 6
Entries
DocumentTitleDate
20110191646Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips - The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.08-04-2011
20090193309DEVICE AND METHOD FOR CORRECTING A DATA ERROR IN COMMUNICATION PATH - There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an interleaver performs interleave. The transmission device transmits a signal which has been subjected to FM modulation by an FM modulation unit. In the reception device, a symbol decision unit performs a symbol decision at a Nyquist point for a signal which has been FM-demodulated by an FM demodulation unit; a bit conversion unit performs bit conversion according to the result of symbol decision; and a frame recovery unit deletes the redundant bit added by the redundant bit addition unit of the transmission device, from the bit string de-interleaved by a de-interleaver. Thus, it is possible to surely perform an error correction with a simple configuration even when the communication state is not in a preferable environment.07-30-2009
20090193308Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel - Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.07-30-2009
20120246533SCALABLE HIERARCHICAL SPARSE REPRESENTATIONS SUPPORTING PREDICTION, FEEDFORWARD BOTTOM-UP ESTIMATION, AND TOP-DOWN INFLUENCE FOR PARALLEL AND ADAPTIVE SIGNAL PROCESSING - A method and apparatus for parallel and adaptive signal reconstruction from a multitude of signal measurements. Algorithms and hardware are disclosed to denoise the measured signals, to compress the measured signals, and to reconstruct the signal from fewer measurements than standard state-of-the-art methods require. A parallel hardware design is disclosed in which the methods that are described can be efficiently executed.09-27-2012
20100325501DATA PROCESSING METHOD AND DATA PROCESSOR - A data processing method includes checking an error on a first header, and determining whether or not to correct the error on the first header based on an error correction count for an first error correction processing block including the first header.12-23-2010
20090158108ERROR DETECTION AND RECOVERY USING AN ASYNCHRONOUS TRANSACTION JOURNAL - Illustrative embodiments provide a computer implemented method, an apparatus, and a computer program product for error detection and recovery using an asynchronous transaction journal. In an illustrative embodiment the computer implemented method receives a request message from a requester, stores the request message in the asynchronous transaction journal and determines whether a sequence number contained within the request message is equal to a predetermined number. When the sequence number is equal, the computer implemented method performs a request in the request message to obtain a result and returns the result to the requester; otherwise the computer implemented method detects an error. The computer implemented method then attempts recovery from the error; otherwise the computer implemented method notifies the requestee.06-18-2009
20100095180RECEIVING DEVICE, RECEIVING METHOD, PROGRAM AND WIRELESS COMMUNICATION SYSTEM - A receiving device is provided that includes a radio receiving unit to receive radio signals transmitted from multiple transmitting antennas by multiple receiving antennas and output received signals being digital signals, a frequency control unit to detect and correct a frequency error contained in the received signals, a channel estimation unit to estimate a channel matrix of which each element corresponds to respective pair of each transmitting antenna and each receiving antenna, an equalization unit to equalize the received signals by using the estimated channel matrix, a demodulation and decoding unit to demodulate and decode the equalized received signals, and an error estimation unit to estimate a channel variation component indicating temporal variation of characteristics of each channel and a phase error component remaining in the received signals based on the channel matrix, the received signals, and a decoding result or an equalization result.04-15-2010
20120166904DATA BUS INVERSION USING SPARE ERROR CORRECTION BITS - In a memory system, a spare error correction bit is produced by processing data to be stored in sufficiently large chunks that the number of error correction bits required to protect each chunk are fewer than the available error correction signal lines on a memory bus and storage device. The spare bit is then used for an inversion bit in a parallel data bus inversion scheme, wherein data is selectively inverted to minimize bus switching. The transmission of data and error correction bits are spread over multiple phases, wherein parallel data bus inversion is applied to each phase. Alternatively, the transmission of data and error correction bits may be transmitted and stored in a single transaction. In either case, the spare bit is transmitted on a conventional memory bus and stored in a conventional memory module along with data and error correction bits.06-28-2012
20130047050CORRECTION APPARATUS, CORRECTION METHOD, AND COMPUTER PRODUCT - A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.02-21-2013
20090319844Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof - A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.12-24-2009
20120192023Clock Data Recovery System - A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h07-26-2012
20090271678INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION - A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.10-29-2009
20090031182Information Communication Terminal, Radio Communication Apparatus and Radio Communication Network System Capable of Performing Communication Corresponding to Purpose - An information communication terminal performs communications with another information communication terminal over a radio communication network system. In the information communication terminal, a receiving unit receives an externally transmitted frame. In a state where error correction is to be performed, a correction processing unit outputs data after performing error correction according to correction information in the frame on data in the frame received by the receiving unit. In a state where the error correction is not to be performed, the correction processing unit outputs the data without performing the error correction on the data in the frame received by the receiving unit. A determining unit determines whether the error correction is to be performed by the correction processing unit or not.01-29-2009
20090013231Multi-bit error correction scheme in multi-level memory storage system - A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value.01-08-2009
20130166980ERROR RECOVERY IN A DATA PROCESSING APPARATUS - A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.06-27-2013
20080294957Communication Apparatus - A communication apparatus for converting signal between differential interchange circuit and multiple devices having input and output terminals comprising: 11-27-2008
20080294956Encryption Via Induced Unweighted Errors - A method for encrypting data is provided. The method includes formatting data represented in a weighted number system into data blocks. The method also includes converting the data blocks into a residue number system representation. The method further includes generating a first error generating sequence and inducing errors int he data blocks after converting the data blocks into a residue number system representation. It should be understood that the errors are induced in the data blocks by using the first error generating sequence. After inducing errors into the data blocks, the data of the data blocks is formatted into a form to be sorted or transmitted. The method also includes generating a second error generating sequence synchronized with and identical to the first error generating sequence and correcting the errors in the data blocks using an operation which is an arithmetic of a process used in inducing errors.11-27-2008
20110283156Processing Transport Packets - Method, relay node and computer program product for processing transport packets, the transport packets conveying: (i) data stream units forming a data stream, and (ii) correction data units relating to the data stream units, where each transport packet contains information identifying the content of units in that transport packet. Transport packets are received at the relay node, the data stream units in the transport packets received at the relay node being insufficient to constitute the data stream. At least some of the correction data units and the data stream units in the received transport packets are used to generate substitute data stream units thereby to substantially recover the data stream at the relay node. The relay node packetises the data stream units of the substantially recovered data stream with correction data units to form output transport packets for transmission from the relay node, and then the output transport packets are transmitted from the relay node.11-17-2011
20110283155APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING DATA IN A COMMUNICATION SYSTEM - A data transmission apparatus in a wireless communication system includes: a data field generation unit configured to generate a data field for transmitting data; a signal field generation unit configured to generate a signal field for transmitting information on the data field; and a transmission unit configured to transmit a data packet containing the data field and the signal field. The signal field includes a rate bit, a reservation bit, a length bit, a parity check bit, and a tail bit, and the data transmission apparatus transmits a check bit for checking whether the signal field is normal or not through two or more bits of the bits of the signal field.11-17-2011
20110296267Reducing Electromagnetic Interference in a Received Signal - Embodiments of methods and apparatus for reducing electromagnetic interference of a received signal are disclosed. One method includes receiving a signal over at least two conductors, extracting a common-mode signal from the at least two conductors, processing the common-mode signal, and reducing electromagnetic interference of the received signal by summing the processed common-mode signal with the received signal.12-01-2011
20100031106RELAY CONNECTION UNIT MOUNTED IN VEHICLE - A Relay connection unit which is connected with a plurality of buses and relays a message to a different bus. The relay connection section comprises a data check section for detecting an error in a data section of a received message, a storage section for storing set data or/and the previously sent data for message rewriting use for each ID (identifier) attached to the message, and a data rewrite portion for rewriting the data section of the message in which the error is detected into the set data or the previously sent data stored in the storage section.02-04-2010
20100023826CLOCK DATA RECOVERING CIRCUIT AND CONTROL METHOD OF THE CLOCK DATA RECOVERING CIRCUIT - A clock data recovering circuit solving a problem in which a stable clock signal cannot be extracted is provided. A phase comparator includes a main-signal-discriminator. The main-signal-discriminator discriminates a reception signal by a clock signal to generate recovery data indicating the discrimination result. Phase comparator 01-28-2010
20100169730PHASE ERROR DETECTION DEVICE, PHASE ERROR DETECTING METHOD, INTEGRATED CIRCUIT AND OPTICAL DISC DEVICE - A phase error detection device detects a phase error, based on an output from an A/D conversion section that performs A/D conversion on an analog input signal in accordance with a sampling clock to generate a digital reproduction signal. The phase error detection device includes a phase error generation section that generates the phase error from the output from the A/D conversion section, and a phase error correction section that corrects the phase error. Herein, the phase error correction section determines a phase error detection range from past phase errors and, when the phase error generated by the phase error generation section is out of the phase error detection range, corrects the phase error.07-01-2010
20100169729ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures.07-01-2010
20100218064SEMICONDUCTOR MEMORY DEVICE INCORPORATING CONTROLLER - A semiconductor memory device includes a first nonvolatile memory, a second nonvolatile memory, a controller and an input/output bus. The first nonvolatile memory includes a plurality of memory cells having a first memory cell configuration. The second nonvolatile memory includes a plurality of memory cells having a second memory cell configuration different from the first memory cell configuration. The controller includes a first controller which controls the first nonvolatile memory, and a second controller which controls the second nonvolatile memory. An input/output bus is connected to the controller and is configured to exchange signals between an external apparatus and the controller. In accordance with a signal input via the input/output bus, the controller performs at least one of an operation of accessing the first nonvolatile memory by the first controller, and an operation of accessing the second nonvolatile memory by the second controller.08-26-2010
20100269005APPARATUS AND METHOD FOR IMPROVED RELIABILITY OF WIRELESS COMMUNICATIONS USING PACKET COMBINATION-BASED ERROR CORRECTION - Various techniques are disclosed for improved reliability of wireless communications using packet combination-based error correction. For example, a method includes receiving a first message transmitted wirelessly, where the first message contains a first copy of a data packet and has at least one error. The method also includes receiving a second message transmitted wirelessly, where the second message contains a second copy of the data packet and has at least one error. The method further includes identifying a set of bit positions based on where the first and second copies of the data packet differ and modifying the set of bit positions to produce a modified set of bit positions. In addition, the method includes modifying one or more bit values in the modified set of bit positions to produce at least one modified copy of the data packet and determining if the at least one modified copy of the data packet is error-free.10-21-2010
20110264974METHOD FOR OPERATING A COMMUNICATION SYSTEM HAVING A PLURALITY OF NODES, AND A COMMUNICATION SYSTEM THEREFOR - In a method for operating a communication system having a plurality of nodes which have access to a shared channel, a transmission process for transmitting a message via the channel is monitored for bit errors, and when a bit error occurs, a signaling message is transmitted via the channel in order to signal the bit error. In order to allow communications processes between the nodes to be controlled as a function of a bit error rate of the channel, a signaling rate of the signaling messages is measured and a bit error rate of the channel is determined as a function of the signaling rate.10-27-2011
20110107166Error recovery within integrated circuit - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.05-05-2011
20100088566ANALYZING APPARATUS AND DATA STORAGE METHOD - An analyzing apparatus includes a result-data storing unit that determines whether result data that is calculated as a result of analysis is restorable by linear interpolation. If the result data is determined to be unrestorable by the linear interpolation, the result-data storing unit stores the result data in a predetermined storage unit. Moreover, the analyzing apparatus includes a data restoring unit that reads the result data from the storage unit. The data restoring unit performs the linear interpolation using the result data acquired, thereby restoring the result data.04-08-2010
20120239997WIRELESS COMMUNICATION SYSTEM, WIRELESS RELAY STATION APPARATUS, WIRELESS TERMINAL STATION APPARATUS, AND WIRELESS COMMUNICATION METHOD - Provided is a wireless communication system employing network coding which can set transmission quality for each destination of packets and improve throughput. The wireless communication system is provided with a wireless relay station apparatus and wireless terminal station apparatuses. The wireless relay station apparatus selects coding rates to be used for a first packet and a second packet in accordance with communication quality required for the first packet and the second packet, generates error correction encoded packets having the same data length from the first packet and the second packet using the selected coding rates, performs network encoding on the error correction encoded first and second packets to generate a network encoded packet, and transmits the generated network encoded packet. The wireless terminal station apparatus performs error correction encoding on a third packet equal to one of the first and second packets, performs network decoding on a received network encoded packet using the error correction encoded third packet to generate a decoded packet, and performs error correction decoding.09-20-2012
20120239996MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING MEMORY CONTROLLER - A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.09-20-2012
20090063923System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel - A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.03-05-2009
20100083065Method and apparatus for error detection and correction - A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.04-01-2010
20110173507Interleaving/De-Interleaving Method, Soft-In/Soft-Out Decoding Method and Error Correction Code Encoder and Decoder Utilizing the Same - An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.07-14-2011
20090276669Method for processing and redirecting misdirected advanced shipping notices (ASNs) - A method is disclosed for correcting misdirected Advanced Shipping Notices (ASNs). In one embodiment, the method receives, from a product supplier, a first set of data associated with an ASN, where the first set of data includes an ASN receiving facility identifier. The method also determines a Purchase Order (PO) that is associated with the ASN, where the PO includes a second set of data. The method further compares one or more fields of the first set of data with one or more fields of the second set of data. In addition, the method determines if the ASN was misdirected based on the comparison, and corrects the ASN, when it is determined that the ASN was misdirected.11-05-2009
20090282308Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, at least one error detection circuit, and a controller configured to control a read operation to read state information from the at least one memory cell by reading a memory cell state information bypassing the at least one error correction circuit, or by reading the memory cell state information and supplying it to the at least one error correction circuit.11-12-2009
20080209295APPARATUS AND METHOD FOR PRE-PROCESSING ON LAYER 2 IN DIGITAL BROADCASTING RECEIVING DEVICE - A method of correcting an error in a transport stream (TS), and a digital broadcasting receiving method are provided. The TS is transmitted from a physical layer. It is determined whether a pointer included in the TS has an error. The pointer is corrected if it is determined that the pointer has an error. It is determined whether a frame buffer value is correct. The frame buffer value is corrected if it is determined that the frame buffer value is not correct. In the TS error correcting method, a pointer error or an erroneous frame buffer value existing in a TS is corrected before the TS is transmitted to an upper layer (e.g., a link layer), and IP data can be transmitted to the upper layer. Accordingly, performance degradation due to Doppler shift can be addressed.08-28-2008
20090113267Error detection method and apparatus - To identify errored bits in a binary data set, an ordered plurality of modulo-2 summations of respective selections of the data-set bits are compared with a target syndrome. The selections of data-set bits are defined by the connection of sum nodes to variable nodes in a logical network of nodes and edges where each variable node is associated with a respective data-set bit and each sum node corresponds to a respective modulo-2 summation. Any sum node for which the corresponding summation of selected data-set bits is found to be inconsistent with the target syndrome is identified as errored. Predetermined patterns of errored sum nodes are then looked for to identify one or more associated errored data-set bits. The identified errored data-set bits can then be flipped to correct them04-30-2009
20090276670RECEPTION APPARATUS, RECEPTION METHOD, AND PROGRAM - A reception apparatus that receives a signal, including, a correction section, an error detection section, a filtering section, and a setting section is provided.11-05-2009
20090287975Memory device and method of managing memory data error - Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.11-19-2009
20100162067Memory scrubbing in third dimension memory - A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.06-24-2010
20080244349MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.10-02-2008
20080276146INCOMPLETE WRITE PROTECTION FOR DISK ARRAY - The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block.11-06-2008
20080250292Memory Module with Ranks of Memory Chips - A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks.10-09-2008
20090265598USING PROGRAMMING-TIME INFORMATION TO SUPPORT ERROR CORRECTION - Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, first data is written to the memory, and a value(s) of an operational parameter(s) that is a consequence of the writing of the first data is determined. Second data is read from the memory, and the value(s) of the operational parameter(s) may be used when correcting errors in the second data. In some embodiments, the first data is the same as the second data. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.10-22-2009
20080288844Data Communication Module Providing Fault Tolerance and Increased Stability - A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.11-20-2008
20100138712APPARATUS AND METHOD FOR VERIFYING TRAINING DATA USING MACHINE LEARNING - An apparatus for verifying training data using machine learning includes: a training data separation unit for separating provided initial training data into N training data and N verification data, where N is a natural number; a machine learning unit for performing machine learning on the separated training data to generate a training model; an automatic tagging unit for automatically tagging an original text of the verification data using the generated training model to provide automatic tagging results; and an error determination unit for comparing the verification data to the automatic tagging results to determine error candidates of the training data.06-03-2010
20100138711Equipment protection method and apparatus - Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M06-03-2010
20100269004State Retention using a variable retention voltage - A data processing apparatus is provided with state retention circuits 14 into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry 10-21-2010
20090138773METHOD AND DEVICE FOR PROCESSING A HIERARCHICAL MULTIMEDIA DATA STREAM TRANSMITTED OVER A NETWORK WITH LOSS - The invention relates to a method of processing a multimedia data stream coded according to a plurality of hierarchical levels and transmitted over a communication network with loss, the hierarchy levels being ordered so that a so-called higher hierarchy level is coded in a way that is dependent on at least one so-called lower hierarchy level, at least one portion of multimedia data of a lower hierarchy level having suffered losses, the method comprising a step (05-28-2009
20120198297NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.08-02-2012
20090063922System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module - A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises error correction logic integrated in the memory hub device and coupled to the link interface. The error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.03-05-2009
20090144596DECODER WITH RESILIENCY TO HANDLE ERRORS IN A RECEIVED DATA STREAM - A decoder provided according to an aspect of the present invention determines a type of each network abstraction layer (NAL) unit, and discards a NAL unit when the size of the NAL unit is inconsistent with the size according to the determined type. According to another aspect, a decoder corrects for errors in the non-pay load portions and uses the corrected non-pay load portions to recover the original data contained in the payload portions of the data stream. In an embodiment, various global parameters (which are applicable to the data stream unless changed further in the data stream) and the values in the slice headers are examined to correct the parameters in the slice headers. According to one more aspect, an end of frame is reliably detected by using an expected number of macro-blocks in a frame and a set of logical conditions of slice header parameters.06-04-2009
20110145668FLASH MEMORY DEVICE, FLASH MEMORY SYSTEM, AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE - A flash memory device comprises a plurality of memory cells each configured to store k-bit data, where k is a natural number greater than one. The device is programmed by a method comprising reading (i−1)-th order data from a selected memory cell connected to a selected wordline before programming i-th order data in one or more adjacent memory cells connected to an adjacent wordline, wherein i is a natural number between two and k, storing as read data the (i−1)-th order data read from the selected memory cell, and programming i-th order data in the selected memory cell based on the stored read data.06-16-2011
20090055700METHOD OF DETERMINING BINARY SIGNAL OF MEMORY CELL AND APPARATUS THEREOF - A method and apparatus to determine a binary signal of a memory cell capable of decreasing an error rate of binary signal determination that occur due to neighboring cells and noise, the apparatus including: a data collection unit to collect target data stored in a target cell in a memory and binary neighboring data of data stored in at least one neighboring cell that neighbors the target cell; a data correction unit to correct the target data collected from the target cell by using the target data and the binary neighboring data collected by the data collection unit and a parameter; and a binary signal determination unit to determine a binary signal of a corrected signal output from the data correction unit.02-26-2009
20120079335Large scale parallel computing system - A new computer system is invented for handling large scale calculation.03-29-2012
20090100307SYSTEMS AND METHODS FOR PROVIDING NONVOLATILE MEMORY MANAGEMENT IN WIRELESS PHONES - The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.04-16-2009
20110225473READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.09-15-2011
20110231724SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a NAND flash memory, an input/output unit, a switch, and a controller. The input/output unit includes an ECC unit configured to perform an ECC process on data input to the NAND flash memory, and/or data output from the NAND flash memory, and an interface configured to exchange data with an external apparatus, and controls input/output of data between the NAND flash memory and the external apparatus. The switch is connected to the NAND flash memory and the input/output unit. The controller controls the NAND flash memory and the input/output unit, and switches a connection between the NAND flash memory and the ECC unit, and a connection between the NAND flash memory and the interface via the switch.09-22-2011
20090259905SYSTEM AND METHOD FOR QUANTUM COMPUTER CALIBRATION AND PERFORMANCE ESTIMATION - A system and method for characterizing noise in a quantum system includes determining pulse sequences for unitary twirling operations. Twirling processes are applied to a quantum system to calibrate errors and to determine channel parameters. Noise characteristics are determined from calibration data collected to calibrate the errors and to determine the channel parameters. The noise characteristics are characterized to determine if the noise is independent relaxation of qubits or collective relaxation of qubits.10-15-2009
20090254789CODING A SIGNAL - An apparatus, a base station and user equipment are provided. The apparatus is configured to code a first given number of symbols from the beginning of a transmission period and/or a second given number of symbols from the end of the transmission period with a stronger error correcting code than the rest of the symbols in the transmission period.10-08-2009
20100162066Acceleration of header and data error checking via simultaneous execution of multi-level protocol algorithms - An error detection system and methodology where the undesirable consequence of encapsulation (additional latency or delay) for virtualization applications such as i-PCI or iSCSI is minimized for the vast majority of data transactions. Cyclic Redundancy Checks (CRCs) and checksums are executed simultaneously in parallel, immediately on reception of a data packet regardless of the relative processing order in relation to the OSI model.06-24-2010
20100162065Protecting integrity of data in multi-layered memory with data redundancy - Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.06-24-2010
20100262880QUADRATURE DECODER FILTERING CIRCUITRY FOR MOTOR CONTROL - The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.10-14-2010
20100199138NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.08-05-2010
20100146351ERROR CORRECTING SCHEME FOR WIRELESS COMMUNICATION - A system for implementing self aggregating communication operations. Wireless communication transports may utilize basic radio transmission units for communication (e.g., such as a symbol, groups of symbols, etc.). Radio transmission units may comprise, for example, one or more message packets. The one or more message packets may be added to a radio transmission unit in preparation for wireless transmission. If unused space exists in the radio transmission unit after the one or more packets have been added, copies of the one or more the packets may also be inserted into the radio transmission unit. Any unfilled space remaining in the radio transmission unit that cannot accommodate complete copies of the one or more message packets may be filled utilizing zero padding. Radio transmission units composed in this manner (e.g., including multiple occurrences of each packet) may be deemed “self aggregated.”06-10-2010
20100241918CLOCK AND DATA RECOVERY FOR DIFFERENTIAL QUADRATURE PHASE SHIFT KEYING - In one embodiment, a method includes receiving a first input stream, generating a first clock, sampling the first input stream based on the first clock, detecting a first phase difference between the first input stream and the first clock to generate a clock-correction signal and a first select signal, and generating a first recovered stream based on the first select signal. The method may additionally include receiving a second input stream, generating a second clock, sampling the second input stream based on the second clock, detecting a second phase difference between the second input stream and the second clock to generate a clock-correction signal and a second select signal, and generating a second recovered stream based on the second select signal. The method may further include adjusting the clocks based on the first and second clock-correction signals and combining the first and second recovered data streams to generate an output.09-23-2010
20120131405METHOD AND APPARATUS FOR DEFECT RECOVERY - A signal processing circuit includes a plurality of processing-circuit modules and a logic control circuit. The plurality of processing-circuit modules is configured to process an electrical signal. The plurality of processing-circuit modules has at least one processing parameter that is adaptively adjusted based on the electrical signal. The logic control circuit is configured to receive signals from the plurality of processing-circuit modules, validate the processing based on the received signals, and control a storage circuit to sample and store a value of the processing parameter when the processing is validated. Further, the logic control circuit is configured to control the storage circuit to maintain the value of processing parameter when the processing fails validation, and to control the storage circuit to recover the processing parameter in the plurality of processing-circuit modules to the stored value when the plurality of processing-circuit modules is disturbed by a defect.05-24-2012
20100251050TIME-DIVISION DUPLEX TRANSMIT-RECEIVE APPARATUS - There is provided a time-division duplex transmit-receive apparatus in which the respective amplitude and phase characteristics of N sets of transmitting unit-receiving unit pair connected with N antenna elements are corrected all together and at the same time. At the time of reception, the reference signal from reference signal generator is branched into N reference signals. The branched reference signal is applied to the reception system through the transmit-receive switching switch. The reception-side error detector detects the error between the output signal of the reception-side amplitude-phase correction circuit and the reference signal to control the reception-side amplitude-phase correction circuit so that the error becomes zero. At the time of transmission, a part of transmitting signal is applied to the reception system through the antenna path. The transmission-side error detector detects the error between the output signal of the reception-side amplitude-phase correction circuit and the transmitting signal to control the transmission-side error detector so that the error becomes zero.09-30-2010
20100251049QUANTUM COMPUTING METHOD AND A QUANTUM COMPUTER - In an operation of two qubit gate having failure information related to success or failure, by using a code to concatenate N-error-correcting code transversally executing a Pauli gate, a Hadamard gate and a CNOT gate, an error-correction is executed by an error-correcting teleportation, and the CNOT gate is executed to an encoded qubit by the error-correcting teleportation. In Bell measurement of the error-correcting teleportation, when a measurement result of non-encoded qubit is processed, by suitably defining failure information of the encoded qubit of level (l+1) from the failure information of encoded qubits of level l, the measurement result of the encoded qubit of each level is determined, and the failure information of the encoded qubit of each level is defined. As a result, a measurement result of a logical qubit as the encoded qubit of the highest level is determined.09-30-2010
20110022913NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.01-27-2011
20100088565Correction of single event upset error within sequential storage circuitry of an integrated circuit - Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, and for comparing during a second phase of said clock signal said second indication and at least one of said third and fourth indications; and output circuitry for correcting any detected errors in said storage circuitry and for outputting an output value; said output circuitry being responsive to no match by said comparison circuitry to output said first indication during a first phase of said clock signal and said second indication during said second phase of said clock signal, and said output circuitry being responsive to a match by said comparison circuitry to output a value in dependence upon comparisons performed by said further comparison circuitry; said output circuitry being responsive to a match by said further comparison circuitry during a first phase of said clock signal to output said first indication during said first clock cycle and to a no match to output an inverted value of said first indication; and said output circuitry being responsive to a match by said further comparison circuitry during a second phase of said clock signal to output said second indication during said second phase of said clock signal and to a no match to output an inverted value of said second indication.04-08-2010
20100070811CIRCUIT ARRANGEMENT - The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x03-18-2010
20110066909PLUGGABLE TRANSCEIVER MODULE WITH ENHANCED CIRCUITRY - Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.03-17-2011
20110066908SIMILARITY DETECTION FOR ERROR REPORTS - Techniques for determining similarity between error reports received by an error reporting service. An error report may be compared to other previously-received error reports to determine similarity and facilitate diagnosing and resolving an error that generated the error report. In some implementations, the similarity may be determined by comparing frames included in a callstack of an error report to frames included in callstacks in other error reports to determine an edit distance between the callstacks, which may be based on the number and type of frame differences between callstacks. Each type of change may be weighted differently when determining the edit distance. Additionally or alternatively, the comparison may be performed by comparing a type of error, process names, and/or exception codes for the errors contained in the error reports. The similarity may be expressed as a probability that two error reports were generated as a result of a same error.03-17-2011
20090307551Mixed Signal Circuit for an Electronic Protected Control or Regulation System - Mixed signal circuit (12-10-2009
20090319843METHOD AND APPARATUS FOR ERROR CORRECTION - Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.12-24-2009
20110107164Method for Reconstructing Sparse Signals from Sign Measurements Using Greedy Search - A signal x is reconstructed from sparse sign measurements y. Estimated measurements {tilde over (y)} are obtained from a previous estimate 05-05-2011
20120144257RECEIVING APPARATUS, DATA TRANSFER APPARATUS, DATA RECEIVING METHOD AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - A data receiving device includes a receiving unit, an inverse conversion unit and an error correction unit. The receiving unit receives converted data, which is obtained by converting data including transfer data of a plurality of bits, and an error detection code for error detection of the transfer data, according to a predetermined first procedure. The inverse conversion unit inversely converts the received converted data according to a predetermined second procedure. If it is impossible for the inverse conversion unit to inversely convert the converted data, if it is possible for the inverse conversion unit to inversely convert inverted data obtained by inverting a portion of the bits of the converted data, and if an error is not detected in data obtained by inversely converting the inverted data based on the error detection code, the error correction unit performs error correction by inversely converting the inverted data.06-07-2012
20110107167METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING FREQUENCY CHANNEL INFORMATION - A method of transmitting frequency channel information by a device to which a frequency band is allocated so as to implement frequency sharing without affecting primary services. The method includes: modulating a stream having content into a main signal; generating a channel information signal related to the frequency band allocated to the device; and combining and transmitting the modulated main signal and the channel information signal. Accordingly, frequency sharing can be used for various primary services by enabling a terminal device to obtain information on a used frequency band without increasing the complexity of the terminal device.05-05-2011
20110107165DISTRIBUTED STORAGE NETWORK FOR MODIFICATION OF A DATA OBJECT - A distributed storage network generates a plurality of data segments from a data object and stores each of the plurality of data segments as a plurality of encoded data slices generated from an error encoding dispersal function. When the distributed storage network receives a modification request for the data object, it determines a size of the plurality of data segments of the data object from a segment size field and identifies one of the plurality of data segments requiring modification. The identified data segment is reconstructed from the plurality of encoded data slices and modified in accordance with the modification request.05-05-2011
20100306610CONCEALMENT PROCESSING DEVICE, CONCEALMENT PROCESSING METHOD, AND CONCEALMENT PROCESSING PROGRAM - A cipher processing device includes: a MAC loss detecting/estimating section which estimates the radio bearer of the lost protocol data unit and a data amount of the lost protocol data unit out of protocol data units produced by division according to the logical channel information included in a packet combining data unit received by a base station of a mobile communication system; an RLC loss detecting/estimating section which detects occurrence of loss in the protocol data units when the protocol data units are put together into a service data unit, and estimates a lost amount of the protocol data units when the protocol data units are put together into the service data unit according to the estimated data amount; and a correction section which corrects a frame number of the service data unit based on the estimated data amount estimated by the detecting/estimating section.12-02-2010
20090070648Efficient Scheduling of Background Scrub Commands - A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.03-12-2009
20090070647Scheduling of Background Scrub Commands to Reduce High Workload Memory Request Latency - A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.03-12-2009
20100313093ERROR-CORRECTION DATA GENERATION APPARATUS AND GENERATION METHOD - An error-correction data generation apparatus for correcting data to be protected in which an error has occurred, the apparatus includes an input unit configured to input data to be protected and a generation unit configured to generate first correction data to be used in correcting first data to be protected.12-09-2010
20100325500Detecting and Recovering from Silent Data Errors in Application Cloning Systems - A method, system, and article for resolving a silent error is disclosed. A primary program copy runs on a primary host, and a secondary program copy runs on a secondary host. The primary and secondary copies communicate to maintain synchronized execution. A third copy of the data is stored on a storage device as a write operations log and maintained in memory on the primary host while the program is running. The primary copy is synchronized with the secondary copy by computing a first checksum of data on the primary host in response to a read operation local to the primary host, computing a second checksum of data on the secondary host in response to a read operation local to the secondary host, and periodically communicating the first checksum to the secondary host, and resolving any discrepancies between the first and second checksum of data reflecting a silent data error.12-23-2010
20100332933SYSTEMS, METHODS, AND APPARATUSES FOR CIPHERING ERROR DETECTION AND RECOVERY - Systems, methods, and apparatuses are provided for ciphering error detection and recovery. A method may include using a first set of one or more cipher input parameters to decipher ciphered data ciphered using a second set of one or more cipher input parameters. The method may further include comparing a value of at least a portion of the deciphered data to an expected value. The method may additionally include determining an occurrence of a ciphering error when the value of the at least a portion of the deciphered data is not equal to the expected value. The method may also include initiating a ciphering resynchronization procedure in response to the determination that a ciphering error occurred so as to resynchronize at least one of the first set of cipher input parameters with at least one of the second set of cipher input parameters. Corresponding systems and apparatuses are also provided.12-30-2010
20110119545METHOD AND SYSTEM OF RECEIVING DATA WITH ENHANCED PARTIAL MATCHING - A method and system of receiving data with enhanced partial matching is disclosed. A received word is compared with the frame code to determine mismatch bit(s). Subsequently, a determination is made whether the mismatch bit(s) are at positions of defined critical bits. If the mismatch bit(s) are not critical, the received word is then affirmed.05-19-2011
20090249148ERROR-CORRECTION FORCED MODE WITH M-SEQUENCE - Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.10-01-2009
20100070812AUDIO DATA INTERPOLATING DEVICE AND AUDIO DATA INTERPOLATING METHOD - An audio data interpolating device includes: a reception module configured to receive content data; an extraction module configured to extract first audio data and second audio data corresponding to the first audio data from the content data; an interpolation data detection module configured to detect error data in the first audio data and detect interpolation data corresponding to the error data from the second audio data; and an output module configured to output the first audio data and output the interpolation data in place of the error data included in the first audio data.03-18-2010
20100064192METHODS AND APPARATUSES FOR CORRECTING ERRORS IN DATA STREAMS - Methods and apparatuses for correcting an error in a data stream that is coded with a line code and an error detection scheme. Information relating to the line code is used to locate at least one possible error character. At least one possible correct character to replace one or more of the at least one possible error character is then identified. Subsequently, the error detection scheme is applied to the data stream updated with one of the at least one possible correct character. If none of the at least one possible correct character results in a valid data stream, an error that is observable by a user is generated.03-11-2010
20110078527ENCODER/DECODER WITH UNFOLDING ERROR CORRECTION - A decoder includes an interface and a processing module. The interface receives first data, redundant data of the first data, second data, redundant data of the second data, and combined redundant data. The processing module decodes the first data based on the redundant data of the first data, decodes the second data based on the redundant data, of the second data and verifies the decoding of the first and second data. When the first data is decoded successfully and the second data is not, the processing module encodes the first data to produce a second redundant data of the first data, determines a second redundant data of the second data based on the combined redundant data and the second redundant data of the first data, decodes the second data based on the second redundant data of the second data, and verifies the decoding of the second data.03-31-2011
20110060956INTERFERENCE-COGNITIVE TRANSMISSION - Interference cognitive devices are described. An interference cognitive device can be collocated with a transmitter of an interference cognitive transmitter (ICT), as receive chains or portions thereof at the ICT. An interference cognitive device can also be remote with respect to the transmitter, which operates in an interference cognitive network and receives data directly or indirectly from the interference cognitive device. The ICT uses the data to mitigate interference while continuing to operate in accordance with a performance metric.03-10-2011
20110060955METHOD AND APPARATUS FOR PROVIDING FREQUENCY ERROR ESTIMATION - An apparatus for providing frequency error estimation may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code may be configured, with the processor, to cause the apparatus to perform at least receiving, at a receiving station, data descriptive of a received signal provided from a transmitting station, receiving confirmation data descriptive of a signal transmitted by the transmitting station corresponding to the received signal, and performing an error characteristic determination associated with operation of the receiving station. The error characteristic may define a probabilistic value of the error characteristic given the received signal and the corresponding confirmation data. A corresponding method and computer program product are also provided.03-10-2011
20110016368System and Method for Automated Configuration Control, Audit Verification and Process Analytics - A method for auditing and verifying configuration items (CIs) in an information technology (IT) configuration management database (CMDB) includes identifying which configuration item (CI) types should be part of an audit, defining link rules to link an authorized CI type stored in a CMDB to an actual CI type that is part of an IT infrastructure, retrieving all authorized CI instances of the identified CI types from the CMDB, retrieving all actual CI instances of the identified CI types from a discovery upload of a current IT environment, comparing the actual CI instances to the authorized CI instances, and taking remedial action when variances are discovered.01-20-2011
20110258507MULITCAST VIDEOCONFERENCING - In one embodiment, the invention is a method of transferring data. The method includes receiving a first video data stream at a first machine. The method also includes multicasting the first video data stream in uncompressed and raw form through a network. The method further includes receiving the first video data stream at a second machine. The method also includes playing the first video data stream on the second machine.10-20-2011
20110131460METHOD FOR REPAIRING IMAGE - A method for repairing an image is disclosed. To repair an image, the method first applies a statistic method based on a plurality of reference data to generate a predicted value range. Then repairing data having values in the predicted value range is generated to repair the image. The reference data of low correlation is filtered out to enhance the quality of a repaired image.06-02-2011
20110131459Memory Device with Protection Capability and Method of Accessing Data Therein - The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password.06-02-2011
20090240998METHOD AND SYSTEM FOR WIRELESS REAL-TIME TRANSMISSION OF MULTICHANNEL AUDIO OR VIDEO DATA - A method and a system for streaming multi channel digital isochronous data. The method is used for streaming multi channel digital isochronous data, e.g. audio data, in a standard wireless local area network transmission system where bandwidth is reserved for both contention-based traffic and contention free traffic and the audio data formed by samples is organized in audio frames and sent to receivers using multicasting, within consecutive beacon intervals. The contention free traffic of the beacon interval is adjusted to an optimum value, and the length of the beacon interval is adjusted such that a required amount of audio data can be sent to the receivers with minimum system delay.09-24-2009
20090150735METADATA BROKERING SERVER AND METHODS - Exemplary embodiments of the present invention provide methods and systems for supplying rich multimedia metadata usable to generate, e.g., sophisticated entertainment user interfaces in the home. These methods and systems can be implemented as a server-based software application that feeds multiple, diverse clients. The server functionality could be distributed, even co-located physically with one or more clients, or centralized. The server aggregates, filters, validates, augments and links metadata from disparate sources. The server transforms the metadata into a more manageable and extensible internal format. The server communicates with client devices using a schema-independent protocol, providing metadata in the appropriate format that suites the clients needs.06-11-2009
20090106616Integrated circuit using speculative execution - An integrated circuit 04-23-2009
20110161764PROCESSOR, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING PROCESSOR - A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.06-30-2011
20080320353APPARATUS COMPRISING A CIRCULAR BUFFER AND METHOD FOR ASSIGNING REDUNDANCY VERSIONS TO A CIRCULAR BUFFER - During operation of a transmitter a circular buffer is created where only column tops of the circular buffer are defined as a starting position for a redundancy version. Where the circular buffer is in sequence format, all possible redundancy versions are at positions ┌K12-25-2008
20120311394MEMORY SYSTEM HAVING MULTIPLE CHANNELS AND WRITE CONTROL METHOD INCLUDING DETERMINATION OF ERROR CORRECTION CHANNEL IN MEMORY SYSTEM - According to one embodiment, an error correction channel determination module determines, a channel to be allocated to a logical page as an error correction channel so that each of a plurality of channels is allocated to a uniform number of logical pages as the error correction channel. A command list generation module generates a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel. A command list issue module issues the list of the write commands.12-06-2012
20120311393APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY - Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.12-06-2012
20110179327COMPUTER-IMPLEMENTED METHOD FOR CORRECTING TRANSMISSION ERRORS USING LINEAR PROGRAMMING - A computer-implemented method for correcting transmission errors. According to the method, a transmitted vector corrupted by error can be recovered solving a linear program. The method has applications in the transmission of Internet media, Internet telephony, and speech transmission. In addition, error correction is embedded as a key building block in numerous algorithms, and data-structures, where corruption is possible; corruption of digital data stored on a hard-drive, CD, DVD or similar media is a good example. In short, progress in error correction has potential to impact several storage and communication systems.07-21-2011
20100287434SIGNAL PROCESSING DEVICE AND ERROR CORRECTION METHOD - Provided is a signal processing device including a signal receiving unit for receiving a multilevel signal having a signal waveform that is obtained by synchronously adding an encoded signal generated based on a specific coding rule and a clock which has an amplitude larger than the encoded signal and for which the transmission speed is half that of the encoded signal, an amplitude level detection unit for detecting an amplitude level of the multilevel signal received by the signal receiving unit, a violation detection unit for detecting a bit position at which rule violation of the specific coding rule occurred, based on a change pattern of the amplitude level detected by the amplitude level detection unit, and an error correction unit for correcting a detection value of the amplitude level corresponding to the bit position detected by the violation detection unit so that the rule violation is resolved.11-11-2010
20110126066MULTI-CHIP MEMORY SYSTEM AND RELATED DATA TRANSFER METHOD - A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.05-26-2011
20100192032System and Method for Correcting Primer Extension Errors in Nucleic Acid Sequence Data - An embodiment of method for correcting an error associated with phasic synchrony of sequence data generated from a population of substantially identical copy of a template molecule is described that comprises (a) detecting a signal generated in response to an incorporation of one or more nucleotides in a sequencing reaction; (b) generating a value for the signal; and (c) correcting the value for the phasic synchrony error using a first parameter and a second carry forward parameter.07-29-2010
20110093753PHASE CALIBRATION CIRCUIT, MEMORY CARD CONTROL DEVICE, AND PHASE CALIBRATION METHOD - Provided is a phase calibration circuit to suppress degradation of transfer efficiency when reading data from a memory card. The phase calibration circuit includes a receive clock generator that generates clock signals including a first clock signal (FCS) with a phase shifted with respect to a base clock signal, a second clock signal with a phase advanced with respect to the FCS, and a third clock signal with a phase delayed with respect to the FCS; a determination unit that acquires data blocks, each of which including a data body and detection information for detecting an error, in accordance with the clock signals, determines whether an error occurs by using the detection information of the data blocks, and outputs determination results; and a phase adjustment unit that instructs the receive clock generator to adjust a phase of the FCS depending on the determination results.04-21-2011
20100115356METHODS AND DEVICES FOR GENERATING DOTS OF AN IMAGE BY USING TWO ERROR ROW MEMORIES - Disclosed are devices and methods for generating dots of an image by using two error row memories, which are capable of reading and writing data synchronously. A device disclosed comprises: a buffer memory A; a buffer memory B; and a memory controller. The memory controller may comprise a read-write control circuit for the buffer memory A, a read-write control circuit for the buffer memory B, and a buffer memory selection circuit. The buffer memory selection circuit is used to generate a read-write selection signal for the buffer memory A and the buffer memory B. The read-write control circuit for the buffer memory A is connected to the buffer memory A and used to implement a read operation or a write operation on the buffer memory A according to the read-write selection signal. The read-write control circuit for the buffer memory B is connected to the buffer memory B and used to implement a read operation or a write operation on the buffer memory B according to the read-write selection signal. The devices and methods are capable of implementing read and write operations on memories synchronously, which can improve the speed of error diffusion during use.05-06-2010
20100017669METHOD FOR CORRECTING HIGH-FREQUENCY CHARACTERISTIC ERROR OF ELECTRONIC COMPONENT - An electronic-component high-frequency characteristic error correcting method for allowing a calibration work to be performed on a two-terminal impedance component using the same correction-target measuring system as that used in actual measurement. At least three correction data acquisition samples having different high-frequency characteristics are measured by a reference measuring system and an actual measuring system. An equation for associating the value measured by the actual measuring system with the value measured by the reference measuring system using an error correction coefficient of a transmission line is determined. A given electronic component is measured by the actual measuring system. An estimated high-frequency characteristic value of the electronic component obtained when the electronic component is measured by the reference measuring system is calculated using the determined equation.01-21-2010
20120011413METHOD AND SYSTEM FOR ADAPTING FORWARD ERROR CORRECTION IN MULTICAST OVER WIRELESS NETWORKS - A method and apparatus are described including receiving channel condition feedback from a device over a wireless channel, determining response to the channel condition feedback if a forward error correction coding rate is sufficient for the device to recover lost data, adjusting the forward error correction coding rate responsive to the second determining act and generating forward error correction packets using the adjusted forward error correction coding rate from source data.01-12-2012
20120159277METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES - Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, wherein each ramped voltage signal segment has a different start voltage and a different end voltage than the other ramped voltage signal segments.06-21-2012
20120072798SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a NAND flash memory, an error correction unit, and a table. The NAND flash memory is configured to hold data. The error correction unit detects and corrects errors in the data. The table holds information on an error correction method associated with each piece of data. The error correction unit selects an error correction method to be applied for each piece of data in accordance with the information in the table.03-22-2012
20120072799DATA TRANSMISSION DEVICE, DATA RECEPTON DEVICE, AND TRANSMISSION METHOD - The present invention provides a data transmission system that reduces the number of data transitions on signal lines in data transmission via parallel buses between devices such as memory interfaces and liquid crystal interfaces, and can realize a lower power consumption and lower EMI noise. A data transmission device (03-22-2012
20120317455SYMBOL ERROR DETECTION METHOD - The invention disclosed in this application describes an error detection method that can be used to identify an OFDM symbol that is interfered with. The method is based on computing a symbol by symbol path error metric from error correction code and by comparing the statistics of each individual symbol to the mean and the variance of the metric computed from the whole data packet.12-13-2012
20110099445RECEPTION APPARATUS, RECEPTION METHOD AND RECEPTION SYSTEM - Disclosed herein is a reception apparatus, including an acquisition section adapted to receive a signal which includes at least one of a first signal and a second signal which have different structures from each other except that the first and second signals have a preamble signal and acquire the preamble signal from the received signal; a detection section adapted to detect a value for correcting the signal using the signal; and a correction section adapted to correct, if it is decided based on the preamble signal acquired by the acquisition section that the signal is the first signal, the signal using the value detected by the detection section.04-28-2011
20110099444VIRTUAL REPAIR OF DIGITAL MEDIA - Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of a segment of unreadable digital content of the digital media. The virtual repair unit retrieves a readable copy of the digital content corresponding to the segment of unreadable digital content identified in the request from a media repository using the virtual repair unit. The virtual repair unit transmits the readable copy of the digital content to the media player for insertion into a buffer of the media player.04-28-2011
20120233515ELECTRONIC APPARATUS, METHOD OF CORRECTING DETECTION DATA, AND SENSOR UNIT - An electronic apparatus includes a sensor unit including a sensing device and configured to transmit detection data acquired with the sensing device; a computing device configured to receive the detection data and compute the corrected value of the detection data; and a memory containing, together with identification information, correction information for computing the corrected value A characteristic of the corrected value is switched by the computing device switching, in accordance with the identification information contained in the memory, a correcting operation method for computing the corrected value using the correction information contained in the memory.09-13-2012
20120124443AD-HOC MULTIMEDIA GROUP COMMUNICATION TERMINAL ROBUST TO PACKET LOSS AND METHOD OF OPERATING THE SAME - Disclosed herein is an ad-hoc multimedia group communication terminal which is robust to packet loss and includes a multimedia transmitter. The media transmitter includes a reception status monitoring module, an error recovery level/traffic adjustment module, a bit stream division and error recovery data generation module, and a media data packet generation module. The reception status monitoring module recognizes packet reception status information relevant to the reception side terminals based on control packets from each of the reception side terminals. The error recovery level/traffic adjustment module adjusts the error recovery level and the amount of traffic of the media data packets. The bit stream division and error recovery data generation module generates error recovery data to be transmitted to the reception side terminals based on the error recovery level. The media data packet generation module generates the media data packets and error recovery data packets.05-17-2012
20120124442STORAGE DEVICE FAILURE MANAGEMENT - Techniques involving failure management of storage devices are described. One representative technique includes encoding data to enable it to be stored in a storage block that includes at least one storage failure. The data is encoded such that it traverses the storage failures when stored in the storage block. When it is determined that a storage access request has requested the data stored in a storage block having such failures, the data is decoded to restore it to its original form.05-17-2012
20100205497Method and device for decoding by using window-based least significant bits in robust header compression - The present invention relates to communication technologies, and provides a decompression method for communication network, in which such fields as an SN are compressed by using an ROHC scheme, so that the compression efficiency is increased. The ROHC uses a WLSB algorithm to compress some fields which change regularly, and decodes by using the decompressor's context through transmitting the low significant bits in these fields. In order to avoid using the inefficient ergodic method and the incorrect direct replacing method in low bits, the present invention selects, based on the mathematical characteristics of the definition of interpretation intervals, to decode by using the method that the low bits is determined by the received k significant bits while the high bits is determined jointly by the local storage information and these k significant bits. Its decoding method can be used for decompression of an SN, a TS and an IP-ID in an ROHC compression.08-12-2010
20100205496MESSAGING SYSTEM - Input messages are received at respective ports (08-12-2010
20110185246METHOD AND APPARATUS FOR CORRECTING DATA POINTS ACQUIRED DURING WELL DRILLING - Described herein are a method, apparatus and computer readable medium for correcting data points acquired during well drilling. The data points are typically stored in a text file that is accessible by a processor. The processor applies one or more tags to the data points, with each of the tags corresponding to a characteristic of the data points. The processor then identifies one or more data faults in the data points using the one or more tags. Each data fault is indicative of inaccurate data in the data points; i.e., data that does not accurately represent the well as drilled. Following identification of the one or more data faults, the processor corrects one or more of the data faults. The resulting corrected, or cleaned, data is more indicative of the well as actually drilled than the uncorrected data. The processor can be connected to a computer readable medium that stores the statements and instructions that the processor executes.07-28-2011
20110185245METHOD FOR DETECTING AND CORRECTING ERRORS FOR A MEMORY WHOSE STRUCTURE SHOWS DISSYMMETRICAL BEHAVIOR, CORRESPONDING MEMORY AND ITS USE - To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ⅓.07-28-2011
20120137189ERROR CONCEALMENT FOR SUB-BAND CODED AUDIO SIGNALS - A decoder and method of decoding a sub-band coded digital audio signal. The decoder comprises: an input, for receiving sub-band coefficients for a plurality of sub-bands of the audio signal; an error detection unit (05-31-2012
20100174959DECODING METHOD AND MEMORY SYSTEM DEVICE USING THE SAME - A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.07-08-2010
20100174960Decoding apparatus, decoding method, and recording medium - A decoding apparatus includes a unit decoding and inversely quantizing coded data to obtain frequency domain audio signal data, a unit computing from the coded data one of the number of scale bits composed of the number of bits corresponding to the scale value of the coded data and the number of spectrum bits composed of the number of bits corresponding to the spectrum value of the coded data, a unit estimating a quantization error of the frequency domain audio signal data based on one of the number of scale bits and the number of spectrum bits of the coded data, a unit computing a correction amount based on the estimated quantization error and correct the frequency domain audio signal data obtained by the frequency domain data obtaining unit based on the computed correction amount, and a unit converting the corrected frequency domain audio signal data into the audio signal.07-08-2010
20100050032ROBUST FILE CASTING FOR MOBILE TV - The present invention concerns a repair control device and a method the repair control device for selecting a repair server among a plurality of repair servers, in a system where at least one terminal and the plurality of repair servers listen to at least one file delivery session distributed in a push mode from at least one file server. The method comprising the steps of receiving from at least one terminal a request for repairing a packet of the at least one file delivery session, selecting a repair server for repairing the packet to the at least one terminal and redirecting the request to the at least one terminal with the address of the selected repair server or forwarding the request to the selected repair server.02-25-2010
20120179947COMMUNICATION APPARATUS, COMMUNICATION METHOD AND STORAGE MEDIUM FOR FLEXIBLE ERROR CORRECTION - A communication apparatus performs communication with another communication apparatus through a communication path. The communication apparatus includes an encoder which is configured to generate B number of check packets from A number of information packets, a packet transmitter which is configured to transmit x number of the information packets and y number of the check packets, and a determination unit which is configured to determine the number of the information packets and the check packets to be transmitted by the packet transmitter to satisfy a condition of A≦x+y≦A+B in accordance with a state of the communication path.07-12-2012
20100275080INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit (10-28-2010
20100011268SYSTEM AND METHOD FOR SIGNAL RECONSTRUCTION FROM INCOMPLETE DATA - A method for reconstructing a signal from incomplete data in a signal processing device includes acquiring incomplete signal data. An initial reconstruction of the incomplete signal data is generated. A reconstruction is generated starting from the initial reconstruction by repeating the steps of: calculating a sparsity transform of the reconstruction, measuring an approximation of sparsity of the reconstruction by applying an m-estimator to the calculated sparsity transform, and iteratively optimizing the reconstruction to minimize output of the m-estimator thereby maximizing the approximation of sparsity for the reconstruction. The optimized reconstruction is provided as a representation of the incomplete data.01-14-2010
20100287433DATA ACCESS APPARATUS AND DATA ACCESS METHOD - A data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.11-11-2010
20120084615FAULT INFORMATION MANAGING METHOD AND FAULT INFORMATION MANAGING PROGRAM - To save the records of an instant fault generation history and an instant fault recovery history without omission, and to pursue the cause of the fault that causes data error and the like as well as to perform recovery works and the like accurately. Each of fault generation notifications transmitted from main signal packages are stored to an instant fault generation history table provided to a storage module of a monitoring control package along a time series cyclically without exception, and each of fault recovery notifications transmitted in accordance with a detection of recovery of the fault corresponding to each of the stored fault generation notifications is stored to the instant fault generation history storage table by corresponding to each of the fault generation notifications already stored to the instant fault generation history storage table.04-05-2012
20120233516RECEPTION PROCESSING DEVICE - According to one embodiment, a reception processing device receives and stores a data packet and a quality enhancement packet. The device includes a third storage unit that stores association between the quality enhancement packet stored in a second storage unit and the data packet stored in a first storage unit, and a fourth storage unit that stores, at each quality enhancement processing, a processing state representing at least one of an interim result and a final result in the quality enhancement processing. The device performs the quality enhancement processing using redundant data included in the quality enhancement packet and the data packet identified by the association and associated with the quality enhancement packet, stores, in the fourth storage unit, the processing state representing the interim result of the operation when interrupting the quality enhancement processing, and resumes the quality enhancement processing by using the processing state.09-13-2012
20110239071DETERMINATION APPARATUS, DETERMINATION SYSTEM, DETERMINATION METHOD, AND RECORDING MEDIUM - A determination apparatus includes a data obtaining unit that obtains data from a detector that outputs data in time series, in accordance with the result of detection of a detection target; a data correction unit that compares reference data indicative of data to be outputted by the detector when the detection target passed through a specific area with the data obtained by the data obtaining unit, and corrects the data obtained by the data obtaining unit so that the data length thereof is equal to the data length of the reference data; a similarity determination unit that determines the similarity between the data corrected by the data correction unit and the reference data; and a determination unit that determines whether the detection target passed through the specific area or not based on the result of the determination by the similarity determination unit.09-29-2011
20120278676RFID TAG, TAG READER/WRITER, DATA MANAGEMENT SYSTEM AND DATA MANAGEMENT METHOD - Disclosed is an RFID tag that is provided with a laminate forming a layered structure; an antenna disposed with respect to the laminate so as to enable external communication; and an RFID circuit electrically connected to the antenna. The laminate has a shielding member for shielding from radiation, and the RFID circuit is arranged in the laminate so as to be covered by the shielding member.11-01-2012
20120096326OPTICAL DISK REPRODUCTION APPARATUS, OPTICAL DISK REPRODUCTION METHOD, REPRODUCTION PROCESSING DEVICE AND REPRODUCTION PROCESSING METHOD - Provided is an optical disk reproduction apparatus capable of preventing information that is different from the original sub information from being subjected to error correction erroneously, and of stably reproducing the sub information. The optical disk reproduction apparatus (04-19-2012
20120331364ERROR CORRECTION PROCESSING CIRCUIT AND ERROR CORRECTION PROCESSING METHOD - An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.12-27-2012
20120331363Systems and Methods for Reduced Format Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.12-27-2012
20120102377METHOD FOR CONSTRUCTING A HISTOGRAM - A method for constructing a histogram can include sampling attributes in a column of a database on a server and determining a bucket set for the histogram based on a number of buckets that represents a distribution of the attributes with minimum error. A bucket in the bucket set includes boundaries and an approximation of a count of attributes falling within the boundaries. The method further includes determining a precision for encoding the approximation, such that the histogram having the bucket set fits within a storage limit on a tangible computer-readable medium. The histogram can then be stored for the database on a tangible computer-readable medium by encoding the approximation with the precision.04-26-2012
20120151291RECEIVING APPARATUS AND PROCESSING METHOD FOR RECEIVING APPARATUS - A receiving apparatus includes a receiving unit that receives a plurality of packets of content data from a transmitting apparatus and also receives, from the transmitting apparatus, recovery data for each group including a plurality of packets that belong to the plurality of packets of content data and that are a predetermined number of packets apart from each other in position in transmission order so that when a packet in the group is not correctly received (not-correctly-received packet), the recovery data is used to recover the not-correctly-received packet; and a determination unit that determines, before the recovery data is received, whether packets have been correctly received that are necessary to recover the not-correctly-received packet by using correctly received packets of content data and the recovery data in a case where the recovery data is correctly received.06-14-2012
20130024740Systems and Methods for Mitigating Stubborn Errors in a Data Processing System - Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.01-24-2013
20130173980SWITCHING CONVERTER WITH PULSE SKIPPING MODE AND CONTROL METHOD THEREOF - The present invention provides a switching converter with pulse skipping mode. The switching converter comprises a switching circuit having at least one switch, a controller and a feedback circuit. The controller comprises an error amplifying circuit, a logic circuit, a ramp signal generator and a pulse skipping circuit. The error amplifying circuit generates a compensation signal based on comparing the feedback signal with a reference signal. The logic circuit generates a control signal to control the ON and OFF switching of the at least one switch based on the compensation signal. The ramp signal generator generates a ramp signal. The pulse skipping circuit generates a pulse skipping signal based on the compensation signal, the ramp signal and a threshold voltage. The logic circuit skips one or more switching pulses of the control signal in accordance with the pulse skipping signal.07-04-2013
20080235551ERROR CORRECTION CIRCUIT AND METHOD THEREOF - An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data.09-25-2008
20110246845METHODS AND APPARATUSES FOR FACILITATING ERROR CORRECTION - Methods and apparatuses are provided for facilitating error correction. A method may include receiving a content item and first repair data over a content delivery network via a first network connection. The method may further include receiving second repair data via a second network connection from a remote device having received the content item over the content delivery network. The first and second repair data may be configured to enable error correction of the content item. Corresponding apparatuses are also provided.10-06-2011
20130103998SYSTEM AND METHOD FOR DIGITAL GAIN ERROR CORRECTION - A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.04-25-2013
20130145227Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port - An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.06-06-2013
20110219279APPLICATION LAYER FEC FRAMEWORK FOR WiGig - A method and apparatus perform forward error correction in a wireless communication device in a wireless communication network. Application layer forward error correction (AL-FEC) capability information is transmitted during a capabilities exchange. A set of source packets are reshaped to k equal-sized source symbols. Systematic packets for the source symbols and at least one parity packet is encoded using a single parity check (SPC) AL-FEC code on the k source symbols. A header of each encoded packet includes a parity packet indicator. The encoded packets are processed in a media access control (MAC) layer and a physical (PHY) layer for transmission.09-08-2011
20110214029SYSTEM AND METHOD FOR MULTI-DIMENSIONAL DECODING - A system and method for soft decoding data. A plurality of candidate error corrections may be generated to correct one or more data bits having soft bit information. Each candidate error correction may define suggested changes to the data bits and is associated with a soft bit value. The soft bit values associated the plurality of candidate error corrections may be mapped to a uniform scale, for example, a uniform finite or integer grid. The plurality of candidate error corrections may be ordered to have combined associated mapped values in a monotonically non-decreasing order. One or more of the plurality of candidate error corrections may be soft decoded in the order of the associated mapped values by a decoding operation for each candidate error correction therein with the associated non-mapped soft bit values.09-01-2011
20130151919Programmable Fault Protect for Processor Controlled High-Side and Low-Side Drivers - A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes a processor, a fault protect circuit, a first terminal, a driver that drives the first terminal, a second terminal, and detection circuitry that outputs a digital detection signal indicative of whether a predetermined condition is detected on the second terminal. The processor can program the fault protect circuit so that the fault protect circuit will later disable the driver as a function of multiple signals, including the digital detection signal. The function is programmable by the processor. In one example, if the detection circuitry detects the predetermined condition on the second terminal then the fault protect circuit disables all the high-side drivers and all low-side drivers of the MTPMIC independently of and without input from the processor.06-13-2013
20100313094COMMUNICATION DEVICE - A communication device is provided with a partial Fourier transformation circuit that calculates a correction parameter for quadrature errors correction. The partial Fourier transformation circuit is programmed to calculate a single one of frequency bins.12-09-2010
20100318868APPARATUS AND METHOD TO READ INFORMATION FROM AN INFORMATION STORAGE MEDIUM - A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel. Thereafter, the method uses those one or more second operating parameters to read the information from the information storage medium.12-16-2010
20100318867APPARATUS AND METHOD TO READ INFORMATION FROM AN INFORMATION STORAGE MEDIUM - A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel. Thereafter, the method uses those one or more second operating parameters to read the information from the information storage medium.12-16-2010
20130159804Increasing the Accuracy of Information Returned for Context Signals - The subject disclosure is directed towards a technology by which the accuracy of context-based information provided by at least one data source for received context data is increased. Correctness information received in association with usage of looked up context-based information is logged. The correctness information may be processed to increase the overall accuracy by correcting a data source, and/or by creating a blended data source that includes the most likely accurate portions (segments) from among multiple data sources as determined via the correctness information.06-20-2013
20130185609NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.07-18-2013
20120066561METHOD AND APPARATUS FOR OBTAINING COEFFICIENTS OF A FRACTIONALLY-SPACED EQUALIZER - A digital data recovery system (03-15-2012

Patent applications in class Digital data error correction

Patent applications in all subclasses Digital data error correction