Class / Patent application number | Description | Number of patent applications / Date published |
714741000 | Simulation | 14 |
20080244347 | Automated Circuit Model Generator - A method, system and program reduce ATPG processing times by eliminating non-value added cells in a circuit model that that is provided to an ATPG system. The elimination of non-value added cells results in a logically equivalent circuit model that is reduced in size from an original circuit model. As a result, an ATPG system that receives the modified circuit model generates a set of test vectors in a shorter amount of time. The method, system and program identify select cells in accordance with information provided in an original circuit model that defines each of the separate circuit cells. Leaf cells, a specific type of cell, are processed using a first set of conditions to generate a modified cell definition. Thereafter, a second set of conditions are applied to generate a modified circuit model. | 10-02-2008 |
20090031181 | Automated root cause identification of logic controller failure - A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic controller, and mapping the logic controller failure information to the logic model to identify a logic failure model state. The method further includes determining a potential trigger of the failure of the logic controller as a root cause via tracing through at least one path in the logic model to reach the logic failure model state. The method also includes identifying the root cause in the logic code via mapping the root cause from the logic model to the logic code, and outputting the logic code with the identified root cause of the failure of the logic controller. | 01-29-2009 |
20090077441 | METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT - A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector. | 03-19-2009 |
20090083600 | Systems and methods for critical node filtering of integrated circuits - Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to identify elements of the circuit which are related to a fault, a circuit pruner to separate the related elements from other elements of the circuit and correlate the related elements to a physical layout of the elements, and a probe tool to locate one or more of the related elements which cause or contribute to the fault. Alternative embodiments may comprise computer programs for simulating operation of a circuit to determine related elements of a fault, correlating the related elements to a physical layout or arrangement of the elements in the circuit, and testing the related elements via the physical layout to determine which elements contribute to the fault. | 03-26-2009 |
20090287974 | Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same - Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop. | 11-19-2009 |
20100064191 | DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device | 03-11-2010 |
20100138710 | LOGIC VERIFICATION APPARATUS - To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. | 06-03-2010 |
20110078526 | Method and Circuit Configuration for Simulating Fault States in a Control Unit - A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a fault-generating circuit are used, the multiplexer being realized using a relay technology, and the fault-generating circuit being implemented using a semiconductor technology. | 03-31-2011 |
20110289373 | Electornic Design Emulation Display Tool - One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display simulation results related to the multiple processors, for example, as a correlated software debug view of the processors. In at least some embodiments, the disclosed technologies can be used to examine a correlation between an error in the simulation results and one or more inter-processor synchronization events. | 11-24-2011 |
20120151290 | GRAPH MATCHING SYSTEM FOR COMPARING AND MERGING FAULT MODELS - A method and system for comparing and merging fault models which are derived from different data sources. Two or more fault models are first represented as bipartite weighted graphs, which define correlations between failure modes and symptoms. The nodes of the graphs are compared to find failure modes and symptoms which are the same even though the specific terminology may be different. A graph matching method is then used to compare the graphs and determine which failure mode and symptom correlations are common between them. Finally, smoothing techniques and domain expert knowledge are used to merge and update the fault models, producing an integrated fault model which can be used by onboard vehicle systems, service facilities, and others. | 06-14-2012 |
20120216091 | Method of Analyzing the Safety of a Device Employing On Target Hardware Description Language Based Fault Injection - A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurable integrated circuit device, synthesizing the fault model in the hardware description language, embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted, creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design, performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device. | 08-23-2012 |
20130007549 | Multithreaded, mixed-HDL/ESL Concurrent Fault Simulator for Large-Scale Integrated Circuit Designs - Techniques for performing multiprocessing/multithreaded concurrent fault simulation of large-scale integrated circuit (IC) designs are described herein. Specifically, an IC design's source files, coded in HDL (Hardware Description Language) and/or ESL (Electronic System-Level) languages, are compiled into a database; stuck-at, transition and/or inter-process communication faults are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a plurality of worker processes (or threads) are created to process those fault sets concurrently. The worker processes can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker process creates a plurality of child threads to carry out the multithreaded concurrent fault simulation of the IC design. After fault simulation is finished, a fault report is generated that depicts the fault coverage of the IC design and all undetected and potentially detected faults. | 01-03-2013 |
20130061104 | IMPROVEMENTS IN BACKWARD ANALYSIS FOR DETERMINING FAULT MASKING FACTORS - A method and a system are presented for determining the observability of faults in an electronic circuit. In the method, for each element the time periods are determined in which an occurrent fault could cause a deviation in analysis output signals. | 03-07-2013 |
20140143625 | COMPUTER-READABLE RECORDING MEDIUM, FAILURE PREDICTION DEVICE AND APPLICABILITY DETERMINATION METHOD - A failure prediction device generates a failure predictor pattern in accordance with previous cases of failure that has occurred in a first system, the failure predictor pattern being used to detect a predictor of failure in the first system configuration. When a system configuration is changed from the first system configuration to a second system configuration, the failure prediction device calculates the difference information that indicates the difference between the system configurations by using the number of changes that is the accumulated number of times that a change of the configuration item which is included in a system is executed. The failure prediction device determines, in accordance with the calculated difference information, whether the failure predictor pattern is applicable to the detection of a predictor of failure in the second system configuration. | 05-22-2014 |