Entries |
Document | Title | Date |
20080209292 | CIRCUIT FOR CONTROLLING VOLTAGE FLUCTUATION IN INTEGRATED CIRCUIT - An integrated circuit and related method for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and a plurality of latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for generating a first output signal that is active for a period from a predetermined time, which is after the integrated circuit is powered on and before an operating clock signal for the At Speed Test is generated, to a time when the operating clock signal is generated. In addition, it also includes a current consumption circuit provided in correspondence with each of at least a part of the plurality of clock buffers, for consuming a certain amount of current in the period during which the first output signal is active. | 08-28-2008 |
20080209293 | PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES - A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing. | 08-28-2008 |
20080215944 | Built-In Self Test (BIST) Architecture having Distributed Interpretation and Generalized Command Protocol - Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer. | 09-04-2008 |
20080235547 | SELF-TEST OUTPUT FOR HIGH-DENSITY BIST - A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/FAIL signal from each embedded memory and one or more comparators coupled to the one or more memories latch mutually identical outputted data coming from the memories upon a rising edge of an ORDY signal. In addition, the comparators may compare the latched mutually identical outputted data and output associated PASS/FAIL signal to the BIST controller. The BIST controller registers the received PASS/FAIL result upon receiving the PASS/FAIL signal from the comparators. The integrated circuit may include output registers coupled to the BIST controller and the comparators output a data log substantially serially upon receiving a SHIFT/CLK signal from the BIST controller. | 09-25-2008 |
20080250289 | Method for Performing a Logic Built-in-Self-Test in an Electronic Circuit - The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits ( | 10-09-2008 |
20080250290 | Method and Apparatus for Testing a Ring of Non-Scan Latches with Logic Built-in Self-Test - A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly. | 10-09-2008 |
20080276144 | Method and System for Formal Verification of Partial Good Self Test Fencing Structures - The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested. | 11-06-2008 |
20080276145 | INTEGRATED CIRCUIT HAVING ELECTRICALLY ISOLATABLE TEST CIRCUITRY - Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power. | 11-06-2008 |
20080301511 | INTEGRATED CIRCUIT WITH CONTINUOUS TESTING OF REPETITIVE FUNCTIONAL BLOCKS - A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing, substituting a test repetitive functional block for a selected repetitive functional block, and testing the selected repetitive functional block during normal functional mode of the IC. An IC which includes repetitive functional blocks for performing corresponding functional block operations during normal functional mode of the IC, and a test system which performs continuous testing of each repetitive functional block while the functional block operations are performed during normal functional mode of the IC. One block may be tested during normal operation for each IC reset event without transferring or copying state information. Multiple blocks may be tested one at a time during normal operation by transferring state information between a selected block and a test block. | 12-04-2008 |
20080313515 | SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC - A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode. | 12-18-2008 |
20090006916 | METHOD FOR CACHE CORRECTION USING FUNCTIONAL TESTS TRANSLATED TO FUSE REPAIR - A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses. | 01-01-2009 |
20090013228 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value. | 01-08-2009 |
20090013229 | BUILT-IN SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 01-08-2009 |
20090019330 | INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES - An integrated circuit includes a sensor for providing a sensor output signal and a diagnostic circuit coupled to the sensor for providing a self-diagnostic signal. The self-diagnostic signal comprises the sensor output signal during a first time duration and an inverted sensor output signal during a second different time duration. | 01-15-2009 |
20090019331 | Integrated circuit for a data transmission system and receiving device of a data transmission system - The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface, and c) a test unit for testing the functionality of the functional units, whereby the test unit has at least two operating modes and at least one gate terminal for switching between the operating modes and is designed to connect circuit points, assigned to a specific operating mode, of the functional units to terminals of the integrated circuit, when the test unit is operated in the specific operating mode. According to the invention, the at least one gate terminal of the test unit is connected to the TAP controller and the integrated circuit is designed to switch between the operating modes depending on the internal states of the TAP controller. The invention relates furthermore to a receiving device of a data transmission system. | 01-15-2009 |
20090024889 | INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES - An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and distribute a built-in self-test signal. The built-in self-test signal can emulate signals internal to the integrated circuit during normal operation, and/or the built-in self-test signal can have other signal characteristics representative of signals other than those signals internal to the integrated circuit during normal operation. | 01-22-2009 |
20090055698 | SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT-IN SELF TESTING USING MICROCODE SEQUENCERS - Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers. | 02-26-2009 |
20090063921 | Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration - A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in current that occur during logical built-in self testing (LBIST) operations in integrated circuits. The method includes executing a first logical built-in self test sequence for a first logic region within an integrated circuit, subsequently executing a second logical built-in self test sequence for a second logic region within the integrated circuit, wherein the second test sequence is offset from the first test sequence by one or more clock cycles. | 03-05-2009 |
20090083598 | METHOD FOR MONITORING AND ADJUSTING CIRCUIT PERFORMANCE - A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values. | 03-26-2009 |
20090094496 | System and Method for Improved LBIST Power and Run Time - A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. | 04-09-2009 |
20090100305 | REPROGRAMMABLE BUILT-IN-SELF-TEST INTEGRATED CIRCUIT AND TEST METHOD FOR THE SAME - The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost. | 04-16-2009 |
20090132883 | TEST CIRCUIT - A test circuit includes a plurality of circuit blocks having a same circuit construction and a same function, a plurality of internal test circuits each corresponding to a different one of the plurality of circuit blocks, an OR circuit which outputs a logical sum result of a test result output by each of the plurality of circuit blocks as a first result signal, an AND circuit which outputs a logical product result of the test result output by each of the plurality of circuit blocks as a second result signal, and a decision circuit which outputs a consistent comparison result between the first result signal and the second result signal as a final result signal. | 05-21-2009 |
20090138772 | MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN - A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block. | 05-28-2009 |
20090172487 | Multiple pBIST Controllers - A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time. | 07-02-2009 |
20090172488 | SEMICONDUCTOR DEVICE - A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing. | 07-02-2009 |
20090183044 | Method and circuit for implementing enhanced LBIST testing of paths including arrays - A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path. | 07-16-2009 |
20090204861 | System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry - An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block. | 08-13-2009 |
20090249146 | AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-TEST (ABIST) CIRCUITRY - A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree. | 10-01-2009 |
20090254788 | Techniques for Logic Built-In Self-Test Diagnostics of Integrated Circuit Devices - A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors. | 10-08-2009 |
20090271676 | Detecting architectural vulnerability of processor resources - In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed. | 10-29-2009 |
20090292963 | Method and System for Testing an Electronic Circuit - A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order, wherein each LBIST pattern of the subset range of LBIST patterns causes an associated output of an electronic circuit. The method tests an electronic circuit in a first test by applying to the electronic circuit the first subset range of LBIST patterns sequentially in the order, thereby generating a first plurality of associated outputs. The method stores a first subset of associated outputs based on the first log interval, the first log start pattern, and the first log end pattern. The method compares the subset of associated outputs with known outputs to identify a first output mismatch. | 11-26-2009 |
20100050031 | Providing Pseudo-Randomized Static Values During LBIST Transition Tests - An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path. | 02-25-2010 |
20100058130 | PROCESSOR TO JTAG TEST ACCESS PORT INTERFACE - Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller. | 03-04-2010 |
20100088563 | SAVING DEBUGGING CONTEXTS WITH PERIODIC BUILT-IN SELF-TEST EXECUTION - A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic. | 04-08-2010 |
20100107025 | SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT - A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behaviour, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module. | 04-29-2010 |
20100107026 | Semiconductor device having built-in self-test circuit and method of testing the same - A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at every cycle of a tester clock signal, and an output terminal for outputting a test result signal representing a result of testing performed in the BIST circuit. Before generating a test result signal, the BIST circuit generates a marker signal, whose phase is identical to the phase of the test result signal, instead of the test result signal. | 04-29-2010 |
20100199137 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 08-05-2010 |
20100223518 | Diagnostic mode switching - A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active. | 09-02-2010 |
20100223519 | COMPACT JTAG ADAPTER - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 09-02-2010 |
20100229059 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 09-09-2010 |
20100251048 | BDX DATA IN STABLE STATES - A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur. | 09-30-2010 |
20100262879 | Internally Controlling and Enhancing Logic Built-In Self Test in a Multiple Core Microprocessor - A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring. | 10-14-2010 |
20100275079 | CONVEYING STATE DATA THROUGH STATE TRANSITIONS AND NUMBER OF STAYS IN STATES - A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further comprises an interface adapter counting a number of inert scans in the command window, and the number of inert scans defines a particular command or data. An inert scan results in no data being moved into or out of the interface adapter. | 10-28-2010 |
20100281319 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 11-04-2010 |
20100293426 | SYSTEMS AND METHODS FOR A PHASE LOCKED LOOP BUILT IN SELF TEST - An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal. | 11-18-2010 |
20100299570 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 11-25-2010 |
20100299571 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 11-25-2010 |
20100318865 | SIGNAL PROCESSING APPARATUS INCLUDING BUILT-IN SELF TEST DEVICE AND METHOD FOR TESTING THEREBY - A signal processing apparatus according to the present invention includes: a built-in self test device dividing a digital reference clock signal to output an I division signal and a Q division signal, shifting the I division signal and the Q division signal by predetermined angles, converting the shifted I and Q signal into analog signals to output an I testing signal and a Q testing signal; and a signal processing receiving and processing the I testing signal and the Q testing signal. | 12-16-2010 |
20100318866 | TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure. | 12-16-2010 |
20110047428 | ON-DEVICE CONSTRAINED RANDOM VERIFICATION FOR DEVICE DEVELOPMENT - A method of functionally verifying a device under test having at least one processor and at least one memory is disclosed. The method includes creating verification data for the device under test using a constrained random verification data creation process executed on the at least one processor. The verification data includes input data and expected output data. The method further includes storing the verification data in the at least one memory. The method further includes processing the input data with the at least one processor to produce actual output data. The method further includes comparing the actual output data to the expected output data. When the actual output data does not equal the expected output data, the method further includes storing at least one inconsistency between the actual output data and the expected output data. | 02-24-2011 |
20110066907 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 03-17-2011 |
20110087941 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 04-14-2011 |
20110099443 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test. | 04-28-2011 |
20110138241 | BUILT-IN SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 06-09-2011 |
20110161760 | ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING - An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node. | 06-30-2011 |
20110161761 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 06-30-2011 |
20110167311 | System and Method for Analyzing an Electronics Device Including a Logic Analyzer - A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user. | 07-07-2011 |
20110202811 | TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY - The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states. | 08-18-2011 |
20110209021 | Failure Detection and Mitigation in Logic Circuits - The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized. | 08-25-2011 |
20110209022 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110209023 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110214028 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 09-01-2011 |
20110264972 | SELF-DIAGNOSIS SYSTEM AND TEST CIRCUIT DETERMINATION METHOD - Provided are a self-diagnosis system and a test circuit determination method that are capable of determining normality of a test circuit which diagnoses a test target circuit. A self-diagnosis system according to an aspect of the present invention includes a test circuit including first and second diagnosis controllers which determine normality of a test target circuit by using an execution result of a test pattern in the test target circuit; and a test circuit determination unit which determines normality of the test circuit by comparing a normality determination result of the test target circuit output from the first diagnosis controller with a normal determination result of the test target circuit output from the second diagnosis controller. | 10-27-2011 |
20110276850 | Field Programmable Gate Arrays with Built-in Self Test Mechanisms - A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST. | 11-10-2011 |
20110302471 | CIRCUITRY FOR BUILT-IN SELF-TEST - A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested. | 12-08-2011 |
20110307753 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal(I) and a data signal that is output from another semiconductor circuit for testing. | 12-15-2011 |
20110320898 | Integrated Circuit Arrangement For Test Inputs - An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch. | 12-29-2011 |
20120011411 | ON-CHIP SERVICE PROCESSOR - An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits. | 01-12-2012 |
20120011412 | ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP. | 01-12-2012 |
20120017131 | METHODS AND APPARATUS FOR PROVIDING A BUILT-IN SELF TEST - A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system. | 01-19-2012 |
20120030533 | IMPLEMENTING SWITCHING FACTOR REDUCTION IN LBIST - A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels. | 02-02-2012 |
20120084614 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 04-05-2012 |
20120096325 | In or relating to 1149.1tap linking modules - Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 04-19-2012 |
20120124440 | LBIST DIAGNOSTIC SCHEME - A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes executing a first test pattern from a plurality of test patterns of a logic built-in self test (LBIST). The method further includes generating a first value based on the first test pattern. The method also further includes comparing the first value to a second value, and terminating the LBIST in response to determining that the first value does not equal the second value. | 05-17-2012 |
20120131404 | Providing An On-Die Logic Analyzer (ODLA) Having Reduced Communications - In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed. | 05-24-2012 |
20120137188 | METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS - A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode. | 05-31-2012 |
20120159275 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 06-21-2012 |
20120179946 | LOGIC BIST FOR SYSTEM TESTING USING STORED PATTERNS - A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test. | 07-12-2012 |
20120221910 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 08-30-2012 |
20120266037 | TAP TIME DIVISION MULTIPLEXING WITH SCAN TEST - An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode. | 10-18-2012 |
20120297263 | SEMICONDUCTOR CHIP AND TEST METHOD - A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss. | 11-22-2012 |
20120304032 | TEST SYSTEM - A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit. | 11-29-2012 |
20120324305 | TESTING INTERPOSER METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer. | 12-20-2012 |
20120324306 | ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP. | 12-20-2012 |
20130013969 | BUS TRANSACTION MONITORING AND DEBUGGING SYSTEM USING FPGA - The various embodiments herein provide a method and a system for providing a bus transaction monitoring and debugging using FPGA. The system comprises a first FPGA, a second FPGA, application software and a communication interface to connect the second FPGA with the application software. The second FPGA comprises a monitor RTL for tapping data signals from different levels of the first FPGA, a transaction based signal trigger for capturing the signals tapped at different levels of the RTL, a monitor data interface for storing the data signals of interest and a packetizer for converting the signals to a plurality of data packets and transmit the data packets to the application software. The application software decodes the transmitted data packets and displays the transactions on a waveform viewer by communicating the information related to the data packets using a plurality of communication protocols. | 01-10-2013 |
20130024739 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 01-24-2013 |
20130047049 | BUILT-IN SELF-TEST FOR INTERPOSER - A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit. | 02-21-2013 |
20130139017 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 05-30-2013 |
20130151918 | IIMPLEMENTING ENHANCED APERTURE FUNCTION CALIBRATION FOR LOGIC BUILT IN SELF TEST (LBIST) - A method and circuits for implementing aperture function calibration for Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. The aperture function calibration uses aperture calibration data, and an LBIST calibration channel having a predefined number of scan inversions between the aperture calibration data and a multiple input signature register (MISR). LBIST is run selecting the LBIST calibration channel and masking other LBIST channels to the MISR. A change in the MISR value, for example, from zero to a non-zero value, is identified and an aperture adjustment is calculated and used to identify any needed adjustment of aperture edges. | 06-13-2013 |
20130159803 | ASYNCHRONOUS CIRCUIT WITH AN AT-SPEED BUILT-IN SELF-TEST (BIST) ARCHITECTURE - Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults. | 06-20-2013 |
20130179745 | TEST INTERFACE CIRCUIT FOR INCREASING TESTING SPEED - A test interface circuit couplable between a source driver and test equipment is disclosed. The test interface circuit includes a plurality of test interface modules and a logic circuit. Each of the test interface modules receives an output signal from one of a plurality of output pins of the source driver, judges whether the received output signal falls in a specified range or not, and generates a deviation signal accordingly. The logic circuit generates a deviation test output signal according to the deviation signals generated by the test interface modules. | 07-11-2013 |
20130191695 | IMPLEMENTING ENHANCED PSEUDO RANDOM PATTERN GENERATORS WITH HIERARCHICAL LINEAR FEEDBACK SHIFT REGISTERS (LFSRs) - A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics. | 07-25-2013 |
20130268819 | DATA RECEIVER DEVICE AND TEST METHOD THEREOF - A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit. | 10-10-2013 |
20140013177 | ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING - An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node. | 01-09-2014 |
20140026009 | INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF - An integrated circuit includes an input unit, a core processor and M output buffers, where M is a natural number greater than 1. The input unit has an output control pin, and receives an output control signal. The core processor is coupled to the input unit, and receives the output control signal to provide M output control signals. The M output buffers are coupled to the core processor, and are time-division multiplexing and enabled in response to the M output control signals, respectively, to output M output signals in M operation periods, respectively. | 01-23-2014 |
20140053035 | ON-CHIP DETECTION OF TYPES OF OPERATIONS TESTED BY AN LBIST - An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic. | 02-20-2014 |
20140115414 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 04-24-2014 |
20140129888 | STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES - Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected. | 05-08-2014 |
20140129889 | SEMICONDUCTOR INTEGRATED CIRCUIT - A state machine; a BIST circuit including a test pattern generator and an expected value comparison circuit; a state monitoring circuit configured to monitor whether or not a state of the state machine is a specific state; and a transition request detection circuit configured to detect a transition request signal from the specific state to a next state, are held. When the state monitoring circuit decides that the state of the state machine is the specific state, the state machine outputs a signal indicating the specific state as a state output of the state machine, and the BIST circuit performs a test of the state machine. When the transition request detection circuit detects the transition request signal while the test is performed, the BIST circuit stops the test of the state machine. | 05-08-2014 |
20140149817 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140149818 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140164861 | APPARATUS AND METHOD FOR SELF-TESTING A COMPONENT FOR SIGNAL RECOVERY - A circuit having a component for signal recovery, such as an adaptive equalizer, may be tested in order to ensure that the component operates properly. Unfortunately, external test equipment may be expensive and prone to being damaged. According to an aspect of the disclosure, there is provided a circuit including BIST (Built-in Self-Test) circuitry for testing a component for signal recovery with a stress signal that simulates an imperfect signal received over a communication channel. The circuit also has a detector for determining whether the component is operating properly with the stress signal. Thus, no external test equipment is needed for testing the component. In some implementations, the BIST circuitry includes a low-pass filter for filtering a transmit signal into the stress signal. Thus, the amount of circuitry involved in generating the stress signal can be reduced. | 06-12-2014 |
20140189456 | 3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION - Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist. | 07-03-2014 |
20140281778 | BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL - A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. | 09-18-2014 |
20140325300 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a test mode circuit capable of changing the semiconductor device into a test mode with fewer malfunctions and without providing a test terminal. The semiconductor device includes a test circuit configured to compare data of a data input terminal and a data output terminal in synchronization with clock, and control whether or not to change the semiconductor device into a test mode in accordance with a result of the comparison. | 10-30-2014 |
20140331099 | INTEGRATED CIRCUIT WITH TOGGLE SUPPRESSION LOGIC - An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal. The integrated circuit includes a switching element configured to receive the first enable signal and the second enable signal to generate a third enable signal. The integrated circuit includes combinational logic coupled to the loading circuit and the switching element, in which the combinational logic is configured to receive the third enable signal. The third enable signal is configured to disable toggling in the combinational logic while the loading circuit operates in the shift mode. | 11-06-2014 |
20150039957 | DYNAMIC BUILT-IN SELF-TEST SYSTEM - A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant. | 02-05-2015 |
20150095732 | Auto-Blow Memory Repair - In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation performed on the plural memories. | 04-02-2015 |
20150100842 | BUFFER TESTING FOR RECONFIGURABLE INSTRUCTION CELL ARRAYS - A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch. | 04-09-2015 |
20150106673 | METHOD AND APPARATUS FOR ON-THE-FLY MEMORY CHANNEL BUILT-IN-SELF-TEST - The present invention discloses a memory channel bridge with a BIST module; and the memory channel bridge interfaces other channels in a SOC to access a memory module. During a DFT test, SOC memory channels and the BIST access the memory module concurrently by using an arbiter in the memory channel bridge to arbitrate the traffics from the SOC memory channels and the BIST to ensure the correctness and completeness of the whole design. | 04-16-2015 |
20150293829 | METHOD AND APPARATUS FOR MONITORING GENERAL PURPOSE INPUT OUTPUT, GPIO, SIGNALS - An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit. | 10-15-2015 |
20160003903 | INTEGRATED CIRCUIT WITH SELF-VERIFICATION FUNCTION, VERIFICATION METHOD AND METHOD FOR GENERATING A BIST SIGNATURE ADJUSTMENT CODE - An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error. | 01-07-2016 |
20160003904 | INTEGRATED CIRCUIT TESTING - Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency. | 01-07-2016 |
20160011259 | INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR | 01-14-2016 |
20160025808 | METHOD AND SYSTEM FOR LOGIC BUILT-IN SELF-TEST - A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted. | 01-28-2016 |
20160033570 | LOGIC-BUILT-IN-SELF-TEST DIAGNOSTIC METHOD FOR ROOT CAUSE IDENTIFICATION - A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification. | 02-04-2016 |
20160178696 | IDENTIFICATION OF UNKNOWN SOURCES FOR LOGIC BUILT-IN SELF TEST IN VERIFICATION | 06-23-2016 |
20160187424 | APPARATUS FOR FAULT INJECTION TO SEMICONDUCTOR CHIP HAVING DIAGNOSTIC FUNCTION - An apparatus for testing a semiconductor chip in which a built-in self test function is embedded, the apparatus including a plurality of error generators inserted between a plurality of function blocks performing a function of the semiconductor chip to input an error signal into the function blocks; and an external error controller for controlling the error generators through external input and output pins of the semiconductor chip and confirming the built-in self test function of the semiconductor chip by monitoring an output signal of the function blocks, and thus an error detection function embedded in the semiconductor chip can be correctly verified. | 06-30-2016 |
20180024189 | IMPLEMENTING REGISTER ARRAY (RA) REPAIR USING LBIST | 01-25-2018 |