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Clock or synchronization

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714724000 - Digital logic testing

714726000 - Scan path testing (e.g., level sensitive scan design (LSSD))

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DocumentTitleDate
20110185244Scan test circuit and scan test control method - A semiconductor integrated circuit, includes a control flip-flop for inputting a scan control signal and a scan path chain formed of a plurality of scan storage elements serially connected to each other. The scan path chain performs a shift operation as a first mode when an output of the control flip-flop is a first status value, and performs a normal operation as a second mode when an output of the control flip-flop is a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching.07-28-2011
20090210763Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG - This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.08-20-2009
20120173943APPARATUS FOR AT-SPEED TESTING, IN INTER-DOMAIN MODE, OF A MULTI-CLOCK-DOMAIN DIGITAL INTEGRATED CIRCUIT ACCORDING TO BIST OR SCAN TECHNIQUES - An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.07-05-2012
20090193307Scan chain modification for reduced leakage - A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.07-30-2009
20110202810PULSE DYNAMIC LOGIC GATES WITH LSSD SCAN FUNCTIONALITY - A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.08-18-2011
20120179944DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES - A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.07-12-2012
20120246532SCAN TEST METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.09-27-2012
20090125771Scan Based Testing of an Integrated Circuit Containing Circuit Portions Operable in Different Clock Domains during Functional Mode - An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during a scan based testing of an integrated circuit. In an embodiment, the encoder receives a test clock, including a capture pulse during a capture mode of the scan test, but forwards the capture pulse only to one of the clock domains and blocking the capture pulse to other clock domains. As a result, erroneous captures in the memory element receiving data from another clock domain is avoided without the need of closing timing on paths which are not functionally exercised.05-14-2009
20090125769ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT - A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.05-14-2009
20090271674SCAN TEST METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.10-29-2009
20110239069SEQUENTIAL DIGITAL CIRCUITRY WITH TEST SCAN - A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.09-29-2011
20110296265SYSTEM FOR TESTING INTEGRATED CIRCUIT WITH ASYNCHRONOUS CLOCK DOMAINS - A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.12-01-2011
20110296266Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip - A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.12-01-2011
20090119562ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.05-07-2009
20100169728Decoupled clocking in testing architecture and method of testing - A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.07-01-2010
20090150732METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT RECOVERY TESTING USING SIMULATION CHECKPOINTS - A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.06-11-2009
20100153796Scan Chain Circuit and Method - A scan chain circuit is disclosed. The scan chain circuit includes a chain of serially coupled clocked circuits. In a first mode of operation, each of the clocked circuits toggles in response to a rising edge of a clock signal. In a second mode of operation, a first set of the clocked circuits in the chain of serially coupled clocked circuits toggle in response to the rising edge of the clock signal and a second set of the clocked circuits in the chain of serially coupled clocked circuits toggle in response to a falling edge of the clock signal.06-17-2010
20100122133LATCH CIRCUIT INCLUDING DATA INPUT TERMINAL AND SCAN DATA INPUT TERMINAL, AND SEMICONDUCTOR DEVICE AND CONTROL METHOD - A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan clock input terminal, a logical circuit that performs a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generates an update clock and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holds the data or the scan data provided from the update input terminal when the update clock is provided.05-13-2010
20100088562FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS - A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.04-08-2010
20100088561FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS - A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.04-08-2010
20100083064SCANNABLE D FLIP-FLOP - The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating its testability. The embodiment of the present invention provides a scannable D flip-flop, comprising a source coupled logic, comprising a trigger circuit for reading a clock input; a scannable input circuit coupled to the trigger circuit having four NMOS transistors; a first feedback circuit for a first output; and a second feedback circuit for a second output; a latch circuit coupled to the source coupled logic; and an output buffer coupled to the latch circuit. Another embodiment of the present invention provides a scannable D flip-flop, comprising: a cascade dynamic logic, comprising: a first stage circuit; a second stage circuit coupled to the first stage circuit; a third stage circuit coupled to the second stage circuit; and a scannable input circuit coupled to the first stage circuit having four NMOS transistors for reading a data input and scannable inputs; a latch circuit coupled to the second stage circuit; and an output buffer coupled to the latch circuit.04-01-2010
20110202809Pulse Flop with Enhanced Scan Implementation - In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse flop. The latch receives the scan data input during one of the phases of the clock, and retains the received input during the other phase. The other phase is the phase in which the pulse to the pulse flop occurs. Thus, when scan data is captured in the pulse flop, the latch at the next pulse flop in the chain may be closed and may prevent a race condition in propagating the scan data.08-18-2011
20090132880Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test - A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.05-21-2009
20080209291OVER TEMPERATURE DETECTION APPARATUS AND METHOD THEREOF - A device is provided for detecting delays of data due to over-temperature conditions, the device includes a first latch having a data input and a clock input and an output, and a first delay path including combinational logic, a first input coupled to the output of the first latch, and an output. The device further includes a second latch having a data input coupled to the output of the first delay path, a clock input coupled to the clock input of first latch, and an output, and a delay element having a data input coupled to the clock input of the first latch and an output. The device includes a third latch having a data input coupled to the output of the first delay path, a clock input coupled to the output of the delay element, and an output, and a comparator having a first input coupled to the output of the second latch, a second input coupled to the output of the third latch, and an output.08-28-2008
20090037786Method and apparatus for unifying self-test with scan-test during prototype debug and production test - A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.02-05-2009
20080270860Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip - An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.10-30-2008
20080282122SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN - Herein described are at least a method and a system to perform scan testing of an integrated circuit chip. The integrated circuit chip is scan tested using only a single scan clock. The single scan clock is provided through a single pin on the integrated circuit chip. In a representative embodiment, the method comprises inputting a single scan clock, first shifting data into one or more flip-flops of one or more scan chains by clocking the data into one or more scan in (SI) inputs of the one or more flip-flops using the single scan clock, selectively clocking flip-flops of a clock domain, and second shifting data from said one or more flip-flops of said one or more scan chains. In a representative embodiment, the system comprises one or more clock domains and one or more clock domain scan test modules.11-13-2008
20090119561Microcomputer and Method of Testing The Same - Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The microcomputer includes an IC on the side for transmitting data through the source-synchronous interface which further includes: a PLL (Phase-Locked Loop) circuit being adapted for transmitting an operation clock in actual operation; a first flip-flop being adapted for transmitting test data in accordance with the operation clock transmitted from the PLL circuit; and a second flip-flop being adapted for transmitting a synchronous clock in source-synchronous, in accordance with the operation clock transmitted from the PLL circuit, a synchronous clock in source synchronous, and an IC on the side for receiving data through the source-synchronous interface which further includes a third flip-flop being adapted for capturing, in accordance with the synchronous clock transmitted from the second flip-flop, the test data transmitted from the first flip-flop. Methods for testing the microcomputer are also provided.05-07-2009
20080288843OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.11-20-2008
20080270863METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD - A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input and a clock pin; and a slave latch having an output, a first clock pin and a second clock pin; capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch; launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.10-30-2008
20080270859Scan test circuit and scan test control method - A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a, shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.10-30-2008
20090125770SCAN BASED COMPUTATION OF A SIGNATURE CONCURRENTLY WITH FUNCTIONAL OPERATION - A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during functional testing without interrupting the functional testing. The functional state may be captured by and shifted out of the scan chain concurrently with functional testing. The scan chain includes sequential elements, each having a functional state and a scan state that operate in parallel. The method and circuit may further include a signature analyzer for compressing the contents of the scan chain into a signature. The method and circuit may capture and compress multiple functional states into a combined signature.05-14-2009
20090183043SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit and a register circuit configured to temporarily retain a logic output from the logic circuit. The first-stage register circuit has a function as an alternative configured to test at least one register circuit and a function as an interface which supplies input data from an external input terminal to the digital circuit. The first-stage register circuit retains the input data from the external input terminal in synchronization with a clock signal, supplies the retained data to the digital circuit at the time of system operation, and outputs the retained data from an external output terminal connected to a dedicated output terminal or the digital circuit at the time of testing.07-16-2009
20090164860SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING THE SAME - In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.06-25-2009
20110145667SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.06-16-2011
20110145666ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.06-16-2011
20110231723FLIP-FLOP CIRCUIT AND SCAN FLIP-FLOP CIRCUIT - A scan flip-flop circuit includes a pulse generator, a dynamic input unit and a latch output unit. The pulse generator generates a pulse signal which is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode. The dynamic input unit precharges a first node to a power supply voltage in a first phase of the clock signal, selectively discharges the first node in the normal mode, and discharges the first node in the scan mode. The latch output unit latches an internal signal provided from the first node to provide an output data, and determines whether the output data is toggled based on the clock signal and a previous state of the output data.09-22-2011
20100275077At-Speed Scan Testing With Controlled Switching Activity - Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.10-28-2010
20100275078HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.10-28-2010
20090240997SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN AUTOMATION SYSTEM - A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas disables the clock gating signal based on a logic of a scan enable signal authorizing the scan shift. A first clock gating circuit included in the clock gating circuit disables the clock gating signal during the scan shift based on the logic of the scan enable signal and also inverts the clock signal and outputs a result of inverting.09-24-2009
20090254787Shift-frequency scaling - There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.10-08-2009
20100162061TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.06-24-2010
20080307281TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN - An apparatus and program product utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.12-11-2008
20100218062Method and Apparatus for Unifying Self-Test with Scan-Test During Prototype Debug and Production Test - A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.08-26-2010
20100218061Circuit and method for increasing scan cell observability of response compactors - The circuit and method for increasing the scan cell observability of response compactors is based on manipulation of x distribution in responses prior to taking them through a compactor. An x-align block is capable of delaying scan chains by judiciously computed values, and thus aligning x's within the same slices. The x-alignment is effected in the insertion of proper control data to the generic x-align hardware. As a result, fewer scan cells are masked due to response x's into other cells, reflecting into enhanced test quality. An ILP formulation can be used to identify the delay assignment that leads to the maximum number of observable scan cells. Alternatively, a computationally efficient greedy heuristic can be used to attain near-optimal results in reasonable run-time. Thus, the x-align block enhances the effectiveness of response compactors and reaps high test quality, even in the dense presence of response x's.08-26-2010
20100229058METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION - A method is provided for testing a portion of a system under test via a scan chain of the system under test. The method includes decomposing the scan chain into a plurality of segments, generating a set of instructions for testing the portion of the system under test, and executing the set of instructions for testing the portion of the system under test. The scan chain is composed of a plurality of elements, and each segment includes at least one of the elements of the scan chain. The set of instructions includes a plurality of processor instructions associated with an Instruction Set Architecture (ISA), and a plurality of test instructions. The test instructions include, for each of the plurality of segments of the scan chain, at least one scan operation to be performed on the segment. An associated apparatus also is provided.09-09-2010
20100235698JTAG Mailbox - An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.09-16-2010
20100241917GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP 09-23-2010
20100235697Error detection in precharged logic - An integrated circuit 09-16-2010
20100146349Semiconductor integrated circuit including logic circuit having scan path and test circuit for conducting scan path test - A semiconductor integrated circuit is configured which has a logic circuit having scan path flip-flops and a test circuit which executes a scan path test. The test circuit includes a clock control circuit and a scan enable control signal generation circuit. The scan enable control signal generation circuit receives a clock-on information signal output from the clock control circuit and supplies a scan enable control signal to another clock control circuit. The other clock control circuit identifies the value of a scan enable signal on the basis of the scan enable control signal. At this time, the scan path flip-flops output fixed values from data output terminals according to the value of the scan enable signal.06-10-2010
20100138709METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT - A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain.06-03-2010
20100162062DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.06-24-2010
20100162060DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK MODIFIER ON AN IC - A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.06-24-2010
20110066906Pulse Triggered Latches with Scan Functionality - Described embodiments provide a scan chain including at least one pulse-triggered latch scan cell. The pulse-triggered latch scan cell includes a pulse-triggered latch adapted to latch data present at its input terminal to its output terminal based on a clock pulse applied to its clock terminal. A pulse generator is adapted to generate the clock pulse from either a rising edge or a falling edge of a clock signal, and the pulse generator includes a logic circuit adapted to generate either a rising edge-generated clock pulse or a falling edge-generated clock pulse based on a control signal.03-17-2011
20080313514ON-CHIP AC SELF-TEST CONTROLLER - A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.12-18-2008
20090319841STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.12-24-2009
20080270861NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD - A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch.10-30-2008
20100313090Scanning-capable latch device, scan chain device, and scanning method with latch circuits - In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs D1 to D4 are connected in series and, except the last-stage main latch circuit, the scanning output from each main latch circuit becomes the scanning input for the subsequent main latch circuit; while the scanning output from the last-stage main latch circuit becomes the scanning input for a slave latch circuit. Hence, in the scanning-capable latch circuit used in an information processing apparatus, the circuit area can be reduced and scanning can be performed with a small-scale circuit.12-09-2010
20100313089Scan Test Application Through High-Speed Serial Input/Outputs - Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.12-09-2010
20100332928SCALABLE SCAN SYSTEM FOR SYSTEM-ON-CHIP DESIGN - A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improves the scan test coverage of the system-on-chip.12-30-2010
20110010595OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.01-13-2011
20110016367SKEW TOLERANT SCANNABLE MASTER/SLAVE FLIP-FLOP INCLUDING EMBEDDED LOGIC - An integrated circuit includes a flip-flop circuit having a master latch unit and a slave latch unit. The master latch unit includes a data latch that may receive a data value on a data input, and a scan latch that may receive a scan data value on a scan data input. The data latch may latch and output the data value on an output line in response to a transition of a first clock signal, while the scan latch may latch and output the scan data value on the output line in response to a transition of a second clock signal. The slave latch unit may latch and output either the data value or the scan data value. The flip-flop circuit also includes a clock select circuit that may selectively provide either the first clock signal or the second clock signal dependent upon a scan enable signal.01-20-2011
20110041020SHIFT REGISTER CIRCUIT - A shift register circuit for providing plural scan signals and plural emission signals includes a plurality of shift register stages. Each shift register stage includes a scan signal generation module and an emission signal generation module. The scan signal generation module is utilized for generating a first scan signal and a second scan signal according to a first clock and a second clock having a phase opposite to the first clock. The first and second scan signals have pulses opposite to each other. The pulse width of the first scan signal is substantially twice that of the first clock. The emission signal generation module is utilized for generating an emission signal according to a third clock and a fourth clock having a phase opposite to the third clock. The pulse width of the emission signal is substantially identical to that of the third clock.02-17-2011
20110246844Test Mode Soft Reset Circuitry and Methods - A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.10-06-2011
20100070810ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.03-18-2010
20090024888SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.01-22-2009
20110078525Method and Apparatus of ATE IC Scan Test Using FPGA-Based System - An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource.03-31-2011
20110072326SRAM MACRO TEST FLOP - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.03-24-2011
20110029829SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.02-03-2011
20100269003DELAY FAULT DIAGNOSIS PROGRAM - An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.10-21-2010
20110161759SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUCTION IN SCAN AREA AND POWER OVERHEAD - A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.06-30-2011
20080270862METHOD AND APPARATUS FOR SOFT-ERROR IMMUNE AND SELF-CORRECTING LATCHES - A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.10-30-2008
20100332929SCAN TESTABLE REGISTER FILE - Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.12-30-2010
20110258505METHOD AND APPARATUS FOR AC SCAN TESTING WITH DISTRIBUTED CAPTURE AND SHIFT LOGIC - An integrated circuit device includes a plurality of functional tiles. Each functional tile may be configured into a scan chain. A clock generator is operable to generate an internal clock signal that is distributed to each of the functional tiles. A clock gater is associated with each of the functional tiles. Each clock gater is operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.10-20-2011
20100287430MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.11-11-2010
20100293425PARAMETRIC SCAN REGISTER, DIGITAL CIRCUIT AND METHOD FOR TESTING A DIGITAL CIRCUIT USING SUCH REGISTER - The present invention relates to a parametric scan register and a method of testing a digital circuit with the aid of such a register. The parametric scan register includes a memory cell having at least one data input, able to receive a test datum, and transferring to its output a representative signal indicative of the test datum by use of a synchronization signal. It furthermore includes a parametric test block one input of which is linked to the output (s) of the cell, the output signal of the cell being transferred at the output of the parametric test block through an internal module, this internal module operating according to modes able to modify the output signal of the cell. Embodiments of the invention apply to the testing of integrated circuits with high integration density, for example in the field of nanotechnologies.11-18-2010
20120072797DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER - Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.03-22-2012
20090300448SCAN FLIP-FLOP DEVICE - A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is located on an output side the scan flip-flop. The Nch insulated gate field effect transistor turns off and dose not output a signal when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor is located between a higher voltage source and an output side of the Nch insulated gate field effect transistor. The Pch insulated gate field effect transistor turns on when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor sets a SO port at a high level voltage.12-03-2009
20110154141METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING - A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.06-23-2011
20100031104Automatic Scan Format Selection Based on Scan Topology Selection - A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection criteria received by the controller and the signaling protocol is specified based on the received selection criteria.02-04-2010
20100031103Selecting a Scan Topology - A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the controllers, wherein the criteria for selection is broadcast to the controllers. A controller is placed online when the received selection criteria matches an activation criteria of the controller.02-04-2010
20110307752SEMICONDUCTOR DEVICE, AND DESIGN METHOD, DESIGN TOOL, AND FAULT DETECTION METHOD OF SEMICONDUCTOR DEVICE - A bridging fault which has occurred between clock signal lines in a semiconductor device can be easily detected. A semiconductor device having a plurality of hold circuits and configured such that a scan test can be performed includes a first and a second clock signal lines supplied with normal operational clock signals having at least either frequencies or phases different from each other during normal operation, and a test clock signal controller which switches, during a test, between a state in which a first test clock signal, which is the same as that supplied to the first clock signal line, is supplied to the second clock signal line, and a state in which a second test clock signal, which is inverted or phase-shifted relative to the first test clock signal, is supplied to the second clock signal line.12-15-2011
20120047412Apparatus and system for implementing variable speed scan testing - In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.02-23-2012
20120047413Methods for implementing variable speed scan testing - In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.02-23-2012
20110167310SCAN BASED TEST ARCHITECTURE AND METHOD - An integrated circuit architecture including architecture for a scan based test, where the integrated circuit includes N scan chain sets including one or more scan chains and an input register bank. The input register bank includes an input for serially receiving an N-bit input vector synchronous with a first clock signal, and N-outputs configured to substantially simultaneously provide the N-bits of the received input vector as N separate output bits. The N separate output bits are used to provide test bits for simultaneously shifting into the respective inputs of the scan chain set synchronous with a second clock signal.07-07-2011
20120017130CIRCUIT FOR TESTING INTEGRATED CIRCUITS - An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.01-19-2012
20120060068SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.03-08-2012
20120159273Dynamic Scan - In a test data access system, a shift register is coupled the test data in pin. A first multiplexer is in data communication with the TDI pin and is configured to receive data from the TDI pin and to transmit data to each of the instruments. The first multiplexer is also configured to receive data from a data recirculation bit and to transmit data from the TDI pin to a plurality of instruments when the recirculation bit has a first value and to transmit data to the plurality of instruments from a recirculation line when the recirculation bit has a second value, different from the first value. A second multiplexer is configured to receive data from each of the plurality of instruments and is configured to transmit data from a selected one of the plurality of instruments, selected based on a value of data in the shift register. A first AND gate is configured to generate a gates clock to the shift register. A second AND gate is responsive to the first AND gate, configured to lock the shift register. A third AND gate, responsive to the first AND gate, is configured to control clocking to the plurality of instruments.06-21-2012
20120079334Low Power Scannable Latch - A scannable latch circuit is disclosed. In one embodiment, the scannable latch circuit includes a master latch, a slave latch, and a gating circuit coupled between the master latch and the slave latch. The slave latch may be implemented to support scan-shifting for test operations. Scan data received by the master latch may be provided to the slave latch through the gating circuit. The gating circuit may enable data to be transferred from the master latch to the slave latch when a scan enable signal is asserted. When the scan enable signal is deasserted, the gating circuit may cause the slave latch to output a constant (i.e. unchanging) state, regardless of the state of data stored in the master latch. This may result in power savings by inhibiting the slave latch from making state changes when scan-shifting operations are not in progress.03-29-2012
20100095177Implementing Diagnosis of Transitional Scan Chain Defects Using LBIST Test Patterns - A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.04-15-2010
20120124439Wrapper Cell for Hierarchical System on Chip Testing - Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit footprint by eliminating a multiplexer and providing simpler interconnections. Identical wrapper cells may be used for input and output data lines reducing the cost of the cell library.05-17-2012
20090132882Scan-load-based dynamic scan configuration - A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells. A pulse on the configuration-set (CS) signal triggers PT Hold latches to capture configuration data from corresponding slave latches, which in turn set configurations of each of the reconfigurable scan cells.05-21-2009
20090132881DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the disclosure that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups.05-21-2009
20120166903MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.06-28-2012
20100241916SCAN TEST CIRCUIT AND METHOD FOR CHANGING CIRCUIT TO SCAN TEST CIRCUIT - A scan test circuit that performs a normal operation, a shift operation, and a capture operation based on a control signal includes: plural combination circuits; plural scan flip-flops, the plural scan flip-flops and the plural combination circuits being alternately connected in series; a flip-flop connected between the scan flip-flop and the subsequent combination circuit not through the combination circuit; and a selector switched between a first mode and a second mode by a switching signal, the selector feeding observation data of a predetermined observation target circuit into the flip-flop in the first mode, the selector feeding output data of a preceding circuit of the flip-flop into the flip-flop in the second mode, the selector being able to be switched to the first mode during the capture operation in a scan test, the selector being able to be switched to the second mode during the normal operation and the shift operation in the scan test.09-23-2010
20100205495DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the disclosure that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups.08-12-2010
20100205494SELECTABLE DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.08-12-2010
20120137187SYSTEM AND METHOD FOR SCAN TESTING INTEGRATED CIRCUITS - A system for scan testing an IC includes one or more scan registers, one or more scan-in pads, one or more scan-out pads, and one or more comparators. Scan test data is transmitted from the scan-in pads to the scan registers. The functional response obtained from the scan test is transmitted to the comparator. The scan-out pad transmits the expected data to the comparator. The comparator compares the expected data and the functional response data and the comparison result is stored. The test result data is transmitted at positive and negative edges of the test clock signal.05-31-2012
20120173942SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF - A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.07-05-2012
20120179945REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.07-12-2012
20120233513METHOD FOR CREATING TEST CLOCK DOMAIN DURING INTEGRATED CIRCUIT DESIGN, AND ASSOCIATED COMPUTER READABLE MEDIUM - In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.09-13-2012
20100011264MULTI-CLOCK SYSTEM-ON-CHIP WITH UNIVERSAL CLOCK CONTROL MODULES FOR TRANSITION FAULT TEST AT SPEED MULTI-CORE - A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk01-14-2010
20100332930STORAGE CIRCUIT, INTEGRATED CIRCUIT, AND SCANNING METHOD - A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.12-30-2010
20110239070METHOD AND APPARATUS FOR TESTING A DATA PROCESSING SYSTEM - A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.09-29-2011
20110276849SYSTEM, CIRCUIT, AND DEVICE FOR ASYNCHRONOUSLY SCAN CAPTURING MULTI-CLOCK DOMAINS - A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-211-10-2011
20120096324TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.04-19-2012
20120331362INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH CONTROLLABLE NUMBER OF CAPTURE PULSES - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains coupled to the additional circuitry, a scan capture clock generator configured to generate a scan capture clock signal having a controllable number of capture pulses, and a clock selection circuit configured to select between at least the scan capture clock signal and a scan shift clock signal for application to clock signal inputs of the scan chains. In one embodiment, the scan capture clock generator comprises a finite state machine, a plurality of capture clock pulse circuits each generating a capture clock pulse signal comprising a different number of capture clock pulses, and logic circuitry coupled to the finite state machine and having inputs adapted to receive the outputs of the capture clock pulse circuits. The logic circuitry is configured to provide at an output thereof at least a portion of a particular one of the capture clock pulse signals based on a current state of the finite state machine.12-27-2012
20120102376METHODS AND APPARATUS TO TEST MULTI CLOCK DOMAIN DATA PATHS WITH A SHARED CAPTURE CLOCK SIGNAL - Methods, circuits and systems are provided to test data paths that traverse multiple clock domains using a common capture clock that is applied to multiple domains. Test data is launched to a first clock domain, and each of the clock domains is selected to receive the common capture clock signal while the test data propagates through the selected clock domain. The test data is capture after it has propagated through each of the multiple domains in response to the shared domains. Applying a common capture clock to each of the different domains eliminates hold time errors that might otherwise occur as the data transitions from one clock domain to another.04-26-2012
20100199136METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PARALLEL TO SERIAL CIRCUIT - A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.08-05-2010
20080235546SYSTEM AND METHOD FOR DETECTING A WORK STATUS OF A COMPUTER SYSTEM - A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.09-25-2008
20080229165Address translation system for use in a simulation environment - Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of virtual addresses required for execution of the system definition file in a virtual testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a physical memory space for a testable system. The method further includes generating translation information by translating the virtual addresses into physical addresses using the memory map file.09-18-2008
20110264971TESTING OF MULTI-CLOCK DOMAINS - A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.10-27-2011
20080222471CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT - In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.09-11-2008
20130103997IEEE1588 PROTOCOL NEGATIVE TESTING METHOD - The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails. This testing method uses the field of correction field (correction Field) in the IEEE1588 message to “magnify” the response of the slave clock DUT to the abnormal message stimulus, and realizes a real-time closed-loop detection to efficiently verify whether the message processing logic of the slave clock DUT follows the IEEE1588 protocol.04-25-2013
20130159802TESTING OF MULTI-CLOCK DOMAINS - A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.06-20-2013
20110289372Scan Latch with Phase-Free Scan Enable - A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.11-24-2011
20080250288Scan Testing Methods - A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (10-09-2008
20120036407METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.02-09-2012

Patent applications in class Clock or synchronization