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Plural scan paths

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714724000 - Digital logic testing

714726000 - Scan path testing (e.g., level sensitive scan design (LSSD))

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DocumentTitleDate
20100023823AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.01-28-2010
20090193306APPARATUS AND METHOD FOR CONTROLLING DYNAMIC MODIFICATION OF A SCAN PATH - The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.07-30-2009
20130031436SEMICONDUCTOR INTEGRATED CIRCUIT, SCAN FLIP-FLOP, AND TEST METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an aspect of the invention includes scan flip-flops and a scan control unit. The scan flip-flop outputs backup data that is held as an internal state under control of the scan control unit, and the scan flip-flop holds backup data output from the scan flip-flop in the scan flip-flop under control of the scan control unit.01-31-2013
20130042161LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths (02-14-2013
20090158105IN SYSTEM DIAGNOSTICS THROUGH SCAN MATRIX - A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.06-18-2009
20100107024Semiconductor device having plural clock domains which receive scan clock in common - A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits, a clock oscillator which generates a plurality of clock signals corresponding to respective operating frequencies that are used to test the plurality of clock domains, a scan clock signal input circuit which receives, from an outside, and a scan clock signal that is supplied to the plurality of scan chains. The semiconductor device further includes a pulse generation circuit unit which generates a clock pulse signal used for the testing based on the clock signal and the scan clock signal, the pulse generation circuit unit including a plurality of pulse generation circuits corresponding to respective operating frequencies, a clock control circuit unit which selectively activates a part of the pulse generation circuit in the pulse generation circuit unit, the clock control circuit including a plurality of logic circuits corresponding to the plurality of scan chains, respectively, and a clock control signal generation unit which generates a clock control signal to control the clock control circuit unit, based on the scan clock signal.04-29-2010
20130047048AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.02-21-2013
20090044064Scan path circuit and semiconductor integrated circuit - Provided are a scan path circuit and a semiconductor integrated circuit that can reduce time necessary for shift operation. The scan path circuit includes: a first scan FF group (02-12-2009
20090307548METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT - A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.12-10-2009
20120233512Two-Dimensional Scan Architecture - Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.09-13-2012
20080294955Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.11-27-2008
20110283154ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 11-17-2011
20110296264Scan Insertion Optimization Using Physical Information - In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.12-01-2011
20090049353SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS - A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.02-19-2009
20100095173MATRIX SYSTEM AND METHOD FOR DEBUGGING SCAN STRUCTURE - An aspect of the present invention is drawn to a system comprising an automatic test engine, a decompressor, a first scan chain, a second scan chain, a compactor and a debug output. The automatic test engine is operable to output a test output, to receive a resultant input, to receive a debug input, to monitor the debug input and to compare the test output with the resultant input. The decompressor is arranged to receive a decompressor input based on the test output, to output a decompressor output. The scan chains are arranged to receive input based on the decompressor output, and each scan chain includes at least one flip-flop. The compactor is arranged to receive input based output from the flip-flops, and to output a compactor output. The debug output line is arranged to receive the flip-flop output.04-15-2010
20100100783PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit (04-22-2010
20100100782PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit (04-22-2010
20090158106Position Independent Testing of Circuits - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.06-18-2009
20120239995METHOD AND APPARATUS FOR SYNTHESIZING CIRCULAR DECOMPRESSORS - Methods and apparatuses are described for decompressing and routing test data. Some embodiments feature an integrated circuit (IC) that includes two or more shift registers configured to shift in the test data. Each of the two or more shift registers can include two or more sequential elements configured such that a scan chain in the set of scan chains receives inputs from at most one sequential element in each of the two or more shift registers. At least one shift register in the two or more shift registers can be configured as a circular shift register. The IC can also include a logic network coupled between the two or more shift registers and the set of scan chains such that the set of scan chains receives the decompressed test data from the two or more shift registers via the logic network.09-20-2012
20120110402METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS - A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.05-03-2012
20130219238INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN SHIFT CONTROL SIGNAL - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing.08-22-2013
20110197102AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.08-11-2011
20080209290System-on-chip performing multi-phase scan chain and method thereof - A silicon on chip (SOC), may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each other, wherein during an isolation mode, the scan chains test combination circuits of the function blocks, and during an interface mode, the scan chains of adjacent ones of the function blocks test combination circuits between the adjacent ones of the function blocks.08-28-2008
20100138708DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.06-03-2010
20120297262ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 11-22-2012
20110209020POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.08-25-2011
20090083595Scan test circuit - When a dynamic fault test is to be performed on a plurality of divisional circuits, in order to perform the dynamic fault test also on a circuit in which the divisional circuits are combined, and to increase a fault detection rate of dynamic fault, a scan test circuit for a semiconductor device including a plurality of divisional circuits obtained by dividing a logical circuit incorporated in the semiconductor device, includes: a clock control circuit; and a first scan path and a second scan path which are provided in each of at least two of the plurality of divisional circuits. The first scan path includes peripheral scan FFs corresponding to scan FFs which transmit and receive signals to and from another one of the plurality of divisional circuits, of scan FFs included in each of the divisional circuits. The second scan path includes internal scan FFs corresponding to scan FFs other than the peripheral scan FFs, of the scan FFs included in each of the plurality of divisional circuits. The clock control circuit controls propagation and blocking of each of clock signals corresponding to the peripheral scan FFs and the internal scan FFs in each of the plurality of divisional circuits.03-26-2009
20080244345FAILURE DIAGNOSTIC APPARATUS, FAILURE DIAGNOSTIC SYSTEM, AND FAILURE DIAGNOSTIC METHOD - There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals outputted from a plurality of scan chains in which a plurality of scan flip-flops, to which signals from the semiconductor integrated circuit device are inputted, are connected in series. For each stage of the scan chains, the failure diagnostic apparatus sets a virtual space compression circuit that compresses output signals of the scan flip-flops in the stage and a virtual pin connected to the output terminal of the virtual space compression circuit, and the output signal of the virtual pin is compared with the compression signal to diagnose the semiconductor integrated circuit device for failure.10-02-2008
20080276142WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.11-06-2008
20080276143Method and apparatus for broadcasting scan patterns in a random access based integrated circuit - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.11-06-2008
20090265596SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF - An integrated circuit package comprising a semiconductor device and pins is provided. The semiconductor device comprises first and second scan chains, each having an input port and an output port. The semiconductor device further comprises at least two first pads, at least two second pads, and a connecting device. The at least two first pads are coupled to the input port of the first scan chain and the output port of the second scan chain, respectively. The at least two second pads are coupled to the output port of the first scan chain and the input port of the second scan chain, respectively. The connecting device is coupled between the first and the second chains, and is capable of controlling electrical connection between the input port of the second scan chain and the output port of the first scan chain. When the connecting device is disabled, the input port of the second scan chain is electrically disconnected from the output port of the first scan chain. The first pads are electrically connected to the pins and the second pads are not electrically connected to any pins of the integrated circuit package.10-22-2009
20080235544Built-in self-test of integrated circuits using selectable weighting of test patterns - A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.09-25-2008
20080244344Testing A Pipeline In An Ic - An architecture for testing a pipeline (10-02-2008
20090119560LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths (05-07-2009
20090119559DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS - A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.05-07-2009
20090083596Method and Apparatus for Synthesis of Augmented Multimode Compactors - Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.03-26-2009
20090177935Scan chain cell with delay testing capability - A scan chain cell 07-09-2009
20090063920PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit (03-05-2009
20090249145SCAN CONTROL METHOD AND DEVICE - A scan control method of a circuit device including setting information indicating scan mode in a register is provided. The scan control method includes cutting an output of scan-out data to a test access port controller and an input of scan-in data from a data register based on information set in the register, and controlling a connection between a scan register and a data register. Each data/scan register includes data registers for the same number of chains to be scanned at the same time. Data set in one data register may be kept in all the data registers in parallel and scanned in all the scan chains in a scan-in process in the broadcast mode. The data set in the data register may be kept in the data register corresponding to the scan register and scanned in the corresponding scan chain, in a scan-in process in the parallel mode.10-01-2009
20090083597Method and Apparatus for Synthesis of Augmented Multimode Compactors - Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.03-26-2009
20110231719Logic Built-In Self-Test Programmable Pattern Bit Mask - In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.09-22-2011
20110231720DATA RECIRCULATION IN CONFIGURED SCAN PATHS - An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value.09-22-2011
20090177934APPARATUS FOR TESTING EMBEDDED MEMORY READ PATHS - An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.07-09-2009
20090210762Method for Blocking Unknown Values in Output Response of Scan Test Patterns for Testing Circuits - A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.08-20-2009
20090210761AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns - A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).08-20-2009
20110231721LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES - Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.09-22-2011
20080288842Ic Testing Methods and Apparatus - A testing circuit has scan chain segments (11-20-2008
20090217117Low power scan shifting with random-like test patterns - An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.08-27-2009
20090254786Accurately Identifying Failing Scan Bits In Compression Environments - X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some chains due to unknown values and select other chains to feed the compactor. This X-masking capability is used to select one scan cell to observe at a time after a failure is observed at the compactor output.10-08-2009
20080313513Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor - Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.12-18-2008
20090259903WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.10-15-2009
20130219239DIE STACK TEST ARCHITECTURE AND METHOD - A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.08-22-2013
20120246531SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS - Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.09-27-2012
20100205493SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes first and second scan storage elements forming a scan chain, and first and second logic circuits connected to inputs of the first and second scan storage elements respectively, wherein the first logic circuit includes a first logic path and a second logic path to an input of the first scan storage element, the first logic path becomes active in a normal state and has a delay difference larger than or equal to a predetermined range with respect to a third logic path possessed by the second logic circuit, the third logic path extending to an input of the second scan storage element, and the second logic path becomes active during a scan test and has a delay difference within a predetermined range with respect to the third logic path.08-12-2010
20100218060SYSTEM AND METHOD FOR SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A design supporting system of a semiconductor integrated circuit, includes: a scan chain designing section configured to generate a scan chain of scan cells; a specific cell determining section configured to determine as specific scan cells, ones of the scan cells of the scan chain based on the number of gates to be driven when a data held by each of the specific scan cells changes on scan-inputting a pattern data from a scan-in side of the scan chain; and a reordering section configured to reorder the specific scan cells at positions closest to the scan-in side of the scan chain. In the first pattern data, a don't-care bit has a same bit data as that of a care bit.08-26-2010
20100211839Circuit and method providing dynamic scan chain partitioning - The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent. The results confirm the superiority of dynamic scan chain partitioning over static partitioning techniques in terms of peak power reduction.08-19-2010
20100100784PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit (04-22-2010
20090187801METHOD AND SYSTEM TO PERFORM AT-SPEED TESTING - Herein described are at least a method and a system to perform at-speed scan testing of a digital integrated circuit chip. The digital integrated circuit chip is segmented into a plurality of segments wherein each segment comprises a signal conditioning circuitry. In a representative embodiment, the signal conditioning circuitry conditions and/or regenerates a scan enable control signal used to select either a scan-shift or capture mode during scan testing of the digital integrated circuit chip. In a representative embodiment, the method comprises dividing a scan chain into multiple segments and positioning a conditioning circuitry within each of the segments.07-23-2009
20090113265LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE - A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.04-30-2009
20100223516Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.09-02-2010
20100223517ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 09-02-2010
20090106613TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS - A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test pattern subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.04-23-2009
20090240996SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit equipped with multiple serially coupled scan chains which are used to shift inspection data based on different clock signals in order to inspect a scan path is provided. Inspection data is supplied to the respective scan chains in a first inspection mode, and the inspection data is supplied to the first stages of scan chains when in a second inspection mode. The inspection data supplied to the serially coupled scan chains in the second inspection mode is held in sequence by data hold units while being shifted between the scan chains.09-24-2009
20090089637Semiconductor test system and test method thereof - Disclosed is a semiconductor test system comprised of a semiconductor integrated circuit including a plurality of scan cells arranged in first and second directions, and a scan control circuit conducting first and second test operations on the scan cells, from among the plurality of scan cells, arranged along the first and second directions, respectively, and detecting a location of a defective scan cell, from among the plurality of scan cells.04-02-2009
20090217116DIAGNOSABLE GENERAL PURPOSE TEST REGISTERS SCAN CHAIN DESIGN - A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L08-27-2009
20100058129TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS - A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.03-04-2010
20120304031HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW PIN COUNT AND HIGH COMPRESSION DEVICES - This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).11-29-2012
20110078524AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.03-31-2011
20080320351LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.12-25-2008
20080215943Generating test sets for diagnosing scan chain failures - Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.09-04-2008
20110161758ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 06-30-2011
20110055649TESTING SECURITY OF MAPPING FUNCTIONS - Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.03-03-2011
20110264970LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths (10-27-2011
20110258504TEST ACCESS MECHANISM FOR DIAGNOSIS BASED ON PARTITIOINING SCAN CHAINS - Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.10-20-2011
20110093752Method and Apparatus for Synthesis of Augmented Multimode Compactors - Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.04-21-2011
20110138239WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.06-09-2011
20090300447SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.12-03-2009
20110307751Profiling-Based Scan Chain Diagnosis - Profiling-based scan chain diagnosis techniques are disclosed. With various implementations of the invention, unloading masking information for each of scan patterns is first determined. A tester then applies the scan patterns to a circuit under test and collects test response data according to the unloading masking information. A profiling-based analysis is performed to determine failing scan cell information based on the test response data.12-15-2011
20090172486TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT - Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.07-02-2009
20120011410SCAN TEST METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.01-12-2012
20120210184Compound Hold-Time Fault Diagnosis - Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan cell failing probability information and one or more faulty segments based on scan pattern test information. Calculated scan cell failing probability information may then be derived. Based on the calculated scan cell failing probability information and the observed scan cell failing probability information, one or more validated faulty segments are verified to have one or more compound hold-time faults. Finally, one or more clock defect suspects may be identified based on information of the one or more validated faulty segments.08-16-2012
20100095176PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit (04-15-2010
20100095175POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.04-15-2010
20100095174SCAN FRAME BASED TEST ACCESS MECHANISMS - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.04-15-2010
20110099442ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS - A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.04-28-2011
20090132879MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT - Techniques for efficiently performing scan tests are described. In an aspect, a single test pin may be used for both a scan input and a scan output for a scan chain. This multiplexing may reduce test costs and provide other benefits. In one design, an integrated circuit (IC) die includes a scan chain and an input/output (I/O) circuit. The I/O circuit is coupled between the scan chain and a single pad for a single test pin. The I/O circuit multiplexes a scan input and a scan output for the scan chain, provides the scan input from the pad to the scan chain during an input phase of a clock cycle, and provides the scan output from the scan chain to the pad during an output phase of the clock cycle. A bi-directional control signal controls the multiplexing of the scan input and the scan output by the I/O circuit.05-21-2009
20090132878SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING A SCAN OPERATION ON A SEQUENCE OF SINGLE-BIT VALUES USING A PARALLEL PROCESSOR ARCHITECTURE - A system, method, and computer program product are provided for performing a scan operation on a sequence of single-bit values using a parallel processing architecture. In operation, a scan operation instruction is received. Additionally, in response to the scan operation instruction, a scan operation is performed on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements.05-21-2009
20120166902Integrated circuit testing - An integrated circuit 06-28-2012
20120317453POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.12-13-2012
20100205492Circuit for boosting encoding capabilities of test stimulus decompressors - The circuit for boosting encoding capabilities of test stimulus decompressors is utilized in conjunction with a stimulus decompressor. The circuit, called align-encode is inserted between the decompressor and internal. The scan chains feed into a response compactor. The align-encode circuit is used to judiciously manipulate care bit distribution. Re-configurability of the align-encode circuit allows for this manipulation via delay cells with the align-encode circuit, whose length can be adjusted on a per scan chain per test pattern basis by loading the align-encode circuit with proper control data. Based on the stimulus decompressor characteristics, the scan chains are delayed in such a way that an unencodable pattern becomes encodable when using the align-encode circuit.08-12-2010
20080288841SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS. - A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.11-20-2008
20120254681SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.10-04-2012
20100299569WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.11-25-2010
20100050030HIGH SPEED ATPG TESTING CIRCUIT AND METHOD - The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.02-25-2010
20090019329Serial scan chain control within an integrated circuit - An integrated circuit 01-15-2009
20080301510Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.12-04-2008
20120266036METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.10-18-2012
20110047426METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.02-24-2011
20120324304SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.12-20-2012
20120324303INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REORDERED SCAN CHAINS - An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain. A given one of the pairs of parallel scan chains comprises an even scan chain and an odd scan chain, formed by reordering the corresponding single original scan chain.12-20-2012
20110276848Data processing apparatus and method for testing a circuit block using scan chains - A data processing apparatus comprises a circuit block to be tested, and a plurality of scan chains, each scan chain providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation. Configurable decompression circuitry is provided for supporting a plurality of decompression schemes associated with more than one test generation tool, and configuration circuitry is responsive to a configuration stimulus to configure the configurable decompression circuitry to implement a selected decompression scheme. Thereafter, on receipt of compressed input test data, the configurable decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to the plurality of scan chains. Configurable compression circuitry can also be provided in a similar manner, with the configuration stimulus being used to configure the configurable compression circuitry to implement a selected compression scheme to be applied to the output test data in order to produce compressed output test data to be issued from an output interface. Such a mechanism provides a particularly flexible approach for supporting compression and decompression schemes in association with the data input to, and output from, the plurality of scan chains.11-10-2011
20120331361METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.12-27-2012
20110320897CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.12-29-2011
20120151288Creating Scan Chain Definition from High-Level Model Using High-Level Model Simulation - Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.06-14-2012
20080244346Circuit for Compression and Storage of Circuit Diagnosis Data - A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.10-02-2008
20080235545Re-using production test scan paths for system test of an integrated circuit - Mission circuitry provided to implement desired data processing operations in an integrated circuit apparatus is tested by using a plurality of scan paths to subject the mission circuitry to production testing before the integrated circuit apparatus is deployed in a mission environment. The plurality of scan paths are re-used to subject the mission circuitry to further testing while the integrated circuit apparatus is deployed in a mission environment.09-25-2008
20130097468LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.04-18-2013
20110231722ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES - Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.09-22-2011
20110239068TAM WITH SCAN FRAME COPY REGISTER COUPLED WITH SERIAL OUTPUT - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.09-29-2011
20110289371LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.11-24-2011
20110307750COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS - Electronic scan circuitry includes a decompressor (12-15-2011
20110314348SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.12-22-2011

Patent applications in class Plural scan paths