Class / Patent application number | Description | Number of patent applications / Date published |
714722000 | Performing arithmetic function on memory contents | 17 |
20080270855 | Method For Detecting Memory Error - A method for easily detecting a memory error that may occur when a memory is accessed or an allocated memory is freed in the process of developing software is disclosed. The memory error detecting method includes: (a) generating an original block indication variable for indicating a starting memory block of a memory region allocated with respect to a variable included in a computer program; (b) detecting a memory error that may occur when the allocated memory region is accessed, by performing a certain operation (computing or arithmetic operation), before the allocated memory region is accessed, using a target block indication variable indicating memory block to be accessed in the allocated memory region and/or the original block indication variable; and (c) outputting information about a detected memory error. | 10-30-2008 |
20090024887 | SEMICONDUCTOR STORAGE DEVICE, DATA WRITE METHOD AND DATA READ METHOD - A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell. | 01-22-2009 |
20100185907 | METHOD FOR BOUNDS TESTING IN SOFTWARE - A method for a bounds test includes receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value, and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A computer readable medium stores instructions for a bounds test, the instructions for causing a computer to perform: receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value; and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A bounds test system includes a processor, wherein the processor supports two's-compliment notation; and a memory, operatively connected to the processor. The memory comprises instructions for causing the processor to perform: receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value; and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. The comparing uses an unsigned result value and two's-compliment notation is used for subtracting and comparing. | 07-22-2010 |
20100199135 | METHOD, SYSTEM AND COMPUTER-READABLE CODE TO TEST FLASH MEMORY - A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die. | 08-05-2010 |
20110113296 | Method of testing a memory module and hub of the memory module - Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals. | 05-12-2011 |
20110126062 | Method for Adjusting Memory Signal Phase - A method for adjusting a memory signal phase is applied to data access between a memory controller and a dynamic random access memory (DRAM) of an electronic apparatus. The method includes writing a test data into the DRAM by the memory controller in response to a predetermined status of the electronic apparatus; generating a first data strobe signal; offsetting a phase of the first data strobe signal to access and verify the test data to generate a verification result; generating a target offset value in response to the verification result; and offsetting the phase of the first data strobe signal by the target offset value for subsequent operations. | 05-26-2011 |
20110246842 | METHODS AND APPARATUS FOR APPROXIMATING A PROBABILITY DENSITY FUNCTION OR DISTRIBUTION FOR A RECEIVED VALUE IN COMMUNICATION OR STORAGE SYSTEMS - Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios. | 10-06-2011 |
20110252284 | OPTIMIZATION OF PACKET BUFFER MEMORY UTILIZATION - A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error. | 10-13-2011 |
20120036404 | CONTROL APPARATUS AND CONTROL METHOD - A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test. | 02-09-2012 |
20130145225 | CODE CHECKING METHOD FOR A MEMORY OF A PRINTED CIRCUIT BOARD - The present invention discloses a code checking method for a memory of a printed circuit board, which is to firstly add a check code to a data end of codes, after the codes is written in a memory, then use a timing controller to calculate a checksum of the data of the part of the primary codes and further compare the calculated checksum with the check code, and then output to a probe via a testing pin to display the result of comparison, so as to accomplish an object of checking if the written codes are correct. The present invention enhances work efficiency of checking the codes written in the memory. | 06-06-2013 |
20130290798 | Systems and Methods for Short Media Defect Detection Using Non-Binary Coded Information - Various embodiments of the present invention provide systems and methods for media defect detection. | 10-31-2013 |
20140365837 | TEST APPARATUS AND METHOD FOR TESTING SERVER - A test apparatus and method for testing a server are provided. The server includes a CPU group and a memory module. The test apparatus is electrically coupled to the CPU group and the memory module. The CPU group includes a number of CPUs, where each CPU is coupled to other CPUs through a plurality of QPI buses. The test apparatus includes a first copying control unit, a second copying control unit and a calculation unit. The first copying control unit controls each CPU to copy data stored in the memory module to a cache of the CPU and records the copying time duration. The second copying control unit controls each CPU to copy data stored in the memory module to caches of other CPUs and records the copying time duration. The calculation unit obtains copying speed according to the copying time duration. | 12-11-2014 |
20150026530 | CONTROLLER BASED MEMORY EVALUATION - A memory system or flash card may include a controller. Improved testing and memory evaluation may be achieved by utilizing the memory's controller rather than an external tester. User defined test algorithms may be run from the controller to characterize, evaluate and test memory (e.g. NAND memory) or test other components, such as the controller itself. | 01-22-2015 |
20150067420 | MEMORY MODULE ERRORS - Techniques for handling errors on memory modules are provided. An uncorrected error from a pair of memory modules may be received. Memory modules other than the pair of memory modules producing the error may be de-configured. Diagnostic tests may be run on the faded pair of memory modules. The memory module of the pair of memory modules that caused the uncorrected error may be determined. | 03-05-2015 |
20160064100 | System and Method of Simulation for Next Generation Memory Technology - A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, multiplying an input spectrum with each of the transfer functions to provide a plurality of results, summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal. | 03-03-2016 |
20160104527 | DETERMINING SOFT DATA FOR FRACTIONAL DIGIT MEMORY CELLS - Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping. | 04-14-2016 |
20160180967 | SEMICONDUCTOR DEVICE | 06-23-2016 |