Class / Patent application number | Description | Number of patent applications / Date published |
714720000 | Special test pattern (e.g., checkerboard, walking ones) | 22 |
20090024886 | System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation - A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution. | 01-22-2009 |
20090049350 | ERROR CORRECTION CODE (ECC) CIRCUIT TEST MODE - An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time. | 02-19-2009 |
20090089632 | Memory Sense Scan Circuit And Test Interface - Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel. | 04-02-2009 |
20090100303 | Adjustable test pattern results latency - A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles. | 04-16-2009 |
20090172480 | System and method for testing a packetized memory device - Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous. | 07-02-2009 |
20100095168 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 04-15-2010 |
20100211835 | METHOD FOR TESTING A MEMORY DEVICE - A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM. | 08-19-2010 |
20110145664 | TEST MODULE AND TEST METHOD - Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program. | 06-16-2011 |
20110214025 | Control method of non-volatile semiconductor device - Disclosed is a control method of a non-volatile semiconductor device including cells, wherein a stress for rewriting information is applied to each of the cells, and each cell has a first time period as a period of time until a characteristic of the cell is stabilized to expectation value information after the stress for rewriting information is applied, a plurality of first sequences, in each of which writing is performed to a plurality of the cells continuously in time series, and a plurality of second sequences, in each of which verification of a plurality of the cells is performed continuously in time series, after the writing performed continuous in time series. When repeating, continuously in time series, a plurality of sets, each of the sets comprising a plurality of the first sequences and a plurality of the second sequences, a period of time from completion of application of the stress to each of the cells in the first sequence until start of the verification in the second sequence for the each of the cells subjected to the stress application, is arranged for each of all of the sets, wherein the period of time is the first time period or more. | 09-01-2011 |
20110258497 | UTILIZATION OF MEMORY REFRESH CYCLES FOR PATTERN MATCHING - Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations. | 10-20-2011 |
20120131398 | METHOD OF performing A CHIP BURN-IN SCANNING with increased EFFICIENCY - Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip. | 05-24-2012 |
20120221903 | TESTING METHOD, NON-TRANSITORY, COMPUTER READABLE STORAGE MEDIUM AND TESTING APPARATUS - A method for testing data, has writing, in a first area of the test-target area, a test pattern, transferring, to a second area of the test-target area, the test pattern that has been written in the first area, transferring, to the first area, the test pattern that has been transferred to the second area, using as a transfer start address an address that is shifted by a predetermined amount, and inspecting whether or not the data is correctly written in and read from the test-target area by comparing the base patterns disposed next to each other in the base-pattern pair included in the test pattern that has been transferred from one of the first area and the second area to the other of the first area and the second area and by determining whether or not the base patterns disposed next to each other are identical to one another. | 08-30-2012 |
20130055039 | Fully Programmable Parallel PRBS Generator - A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock. | 02-28-2013 |
20130103993 | ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING - A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns. | 04-25-2013 |
20140026006 | MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS - A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. | 01-23-2014 |
20140095949 | METHOD AND APPARATUS FOR DIAGNOSING A FAULT OF AMEMORY USING INTERIM TIME AFTER EXECUTION OF AN APPLICATION - An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas. | 04-03-2014 |
20140149810 | SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY - In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing. | 05-29-2014 |
20140157067 | APPARATUS AND METHOD FOR APPLYING AT-SPEED FUNCTIONAL TEST WITH LOWER-SPEED TESTER - A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result. | 06-05-2014 |
20140181602 | MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS - A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus. | 06-26-2014 |
20150039953 | SYSTEM FOR SIMULTANEOUSLY DETERMINING MEMORY TEST RESULT - A system for simultaneously determining a memory test result includes a pattern generation part generating a pattern signal for testing so as to transmit the signal through an address line and a command line; a delay part receiving read data through a first data line from a closest memory device that is disposed closer to the system and to receive read data through a second data line from a farthest memory device that is disposed farther from the system; and a determination part simultaneously determining the read data of the closest memory device and the read data of the farthest memory device, which are simultaneously output from the delay part, using a determination clock, wherein the delay part recognizes the read data of the closest memory device and the read data of the farthest memory device. | 02-05-2015 |
20150067418 | STORAGE TESTER CAPABLE OF INDIVIDUAL CONTROL FOR A PLURALITY OF STORAGE - Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage. | 03-05-2015 |
20150357045 | CHUNK DEFINITION FOR PARTIAL-PAGE READ - The present disclosure is related to chunk definition for partial-page read. A number of methods can include setting a chunk size for a partial-page read of a page of memory cells. A start address of the partial-page read and chunk size can define a chunk of the page of memory cells. Some method can include enabling only those of a plurality of sense amplifiers associated with the page of memory cells that correspond to the chunk to perform the partial-page read. | 12-10-2015 |