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Read-in with read-out and compare

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

714718000 - Memory testing

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714720000 Special test pattern (e.g., checkerboard, walking ones) 13
Entries
DocumentTitleDate
20130031432FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal.01-31-2013
20130031431Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats - Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.01-31-2013
20100017664EMBEDDED FLASH MEMORY TEST CIRCUIT - Provided is an embedded flash memory test circuit, including an embedded flash memory call array a read-only memory (ROM) built-in self test (BIST) unit, a ROM BIST control unit and a comparison unit. The embedded flash memory cell array includes multiple flash memory cells, and simultaneously outputs m pieces of read data, where m is a natural number. The ROM BIST unit generates first compressed data by compressing the m pieces of read data. The ROM BIST controller controls the ROM BIST unit. The comparison unit compares the first compressed data and expected data.01-21-2010
20130031430Non-Volatile Memory and Method with Accelerated Post-Write Read Using Combined Verification of Multiple Pages - A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.01-31-2013
20100042880TEST APPARATUS AND TEST METHOD - Provided is a test apparatus provided in common for a plurality of memories under test, comprising an address generating section that sequentially generates addresses to be tested in the memories under test and a plurality of buffer memories that are provided to correspond respectively to the plurality of memories under test and that each store addresses to be independently supplied to the corresponding memory under test. The test apparatus (i) compares block data output by the corresponding memory under test in response to the read command to an expected value of this block data, for each generated address, (ii) sequentially stores, in the buffer memory provided corresponding to each memory under test and in response to detection of a discrepancy in the comparison, the address generated for reading the block data, and (iii) writes, in parallel to the plurality of memories under test, a disable data that includes, as individual addresses, the addresses stored in the buffer memory.02-18-2010
20090125763PROGRAMMABLE MEMORY BUILT-IN SELF-TEST CIRCUIT AND CLOCK SWITCHING CIRCUIT THEREOF - A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.05-14-2009
20090307544MEMORY TEST DEVICE AND MEMORY TEST METHOD - A memory test device, including a universal register to conduct an operation by a predetermined universal command language; an extension register having a larger capacity than the universal register and to conduct an operation by a predetermined extension command language; and a controller to write a predetermined test pattern in an external memory using the extension command language, to read the test pattern written in the memory, to determine the identity of the written test pattern and the read test pattern, and to determine a presence of an error in the memory using the universal command language.12-10-2009
20090271670Systems and Methods for Media Defect Detection Utilizing Correlated DFIR and LLR Data - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a method for detecting a media defect is disclosed. The method includes deriving a data input from a medium and performing a MAP detection on the data input. The MAP detection provides an NRZ output and an LLR output corresponding to the data input. A product of the NRZ output is correlated with a product of the LLR output to produce a correlated output. The correlated output is compared with a threshold value, and a media defect output is asserted based at least in part on the result of the comparison of the correlated output with the threshold value.10-29-2009
20120117432TEST APPARATUS - Provided is a test apparatus that tests a memory under test, comprising a logic comparing section that compares output data output from the memory under test to expected value data, for each address of the memory under test, and outputs fail data when the output data does not match the expected value data; a fail analysis memory section that stores the fail data in association with the addresses of the memory under test; and a masking section that counts the pieces of fail data output from the logic comparing section and, when the count value exceeds a preset upper limit fail value, masks the fail data supplied from the logic comparing section to the fail analysis memory section.05-10-2012
20090006914SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DETECTING FAIL PATH THEREOF - Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.01-01-2009
20090158104METHOD AND APPARATUS FOR MEMORY AC TIMING MEASUREMENT - A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.06-18-2009
20080294952TEST APPARATUS AND DEVICE - It is aimed to efficiently test devices that can transfer data at a very high bit rate. A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.11-27-2008
20080294951Methods and devices for testing computer memory - A method, and a corresponding device, provides for testing computer memory having a number of memory elements. The method includes the steps of initializing each memory element to zero, using a seeded random number generator, determining a random address that corresponds to a start point in the memory range, using the seeded random number generator, writing a random data value to the random address, repeating the two previous steps until all memory elements have been written to with random data values, conducting a refresh test of the memory range, and using the same seeded random number generator and the same written random data values, reading each of the memory elements in the memory range.11-27-2008
20130019131MEASUREMENT OF LATENCY IN DATA PATHSAANM Tetzlaff; David ErichAACI MinnetonkaAAST MNAACO USAAGP Tetzlaff; David Erich Minnetonka MN USAANM Vea; Mathew PowerAACI ShrewsburyAAST MAAACO USAAGP Vea; Mathew Power Shrewsbury MA US - This disclosure is related to measurement of latency in data paths. A latency measurement may be accomplished by calculating a roundtrip write-to-read latency based on generating a write signal and receiving a read signal approximately simultaneously. The read signal may be based on a coupling between a write element and read element. A device setting may then be adjusted based on the calculated roundtrip write-to-read latency. Further, a read/write mechanism that is used to write user data to and read user data from a data storage medium may be used to determine the roundtrip write-to-read latency. Even further, the roundtrip write-to-read latency may be determined in real-time as the data storage device is in operation.01-17-2013
20110283153TEST APPARATUS, TEST MODULE AND TEST METHOD - A test module comprising a compression information storage section that stores a plurality of pieces of compression information that each associate a pattern sequence with a piece of pattern sequence identification information; a basic pattern storage section that stores, as a group of basic patterns, a plurality of pieces of pattern sequence data that each include the pattern sequence or the pattern sequence identification information in association with a command; an instruction information storage section that stores instruction information indicating a processing order for the basic patterns; a selecting section that selects, from among the pieces of compression information stored in the compression information storage section, compression information to be used for the basic pattern to be processed according to the processing order indicated by the instruction information; a basic pattern reading section that reads, from the basic pattern storage section, the pattern sequence data included in the basic patterns to be processed; and a pattern sequence reading section that, when the pattern sequence identification information is included in the pattern sequence data read by the basic pattern reading section, references the compression information selected by the selecting section and reads the pattern sequence corresponding to the pattern sequence identification information.11-17-2011
20080270854SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL - A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.10-30-2008
20110302470TEST MODE FOR PARALLEL LOAD OF ADDRESS DEPENDENT DATA TO ENABLE LOADING OF DESIRED DATA BACKGROUNDS - One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm. The pattern generating logic further causes the data loading circuit to load each of the generated patterns of data into the buffer for transferring to a respective row of the memory cells.12-08-2011
20110296260SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.12-01-2011
20100037109METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN - A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.02-11-2010
20100169726INFORMATION PROCESSING SYSTEM - An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer for measuring an elapsed time after data is entered into a memory device, a read controller for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.07-01-2010
20090164857TESTING EMBEDDED CIRCUITS WITH THE AID OF A SEPARATE SUPPLY VOLTAGE - Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (06-25-2009
20090150729METHOD OF TESTING MEMORY ARRAY AT OPERATIONAL SPEED USING SCAN - A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.06-11-2009
20120110400Method and Apparatus for Performing Memory Interface Calibration - A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction.05-03-2012
20100251043SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT FUNCTION VERYFICATION DEVICE AND METHOD OF VERYFYING CIRCUIT FUNCTION - A semiconductor integrated circuit has a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory, a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal, and a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.09-30-2010
20090094494SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SAME - A semiconductor integrated circuit includes a semiconductor memory circuit, an address input unit to generate an input address and to input the input address into the semiconductor memory circuit, the address input unit repeating generating and inputting from a start address to a end address, and an output data processor to select a select data and to count a value of the select data. The input address specifies data stored in the semiconductor memory circuit. The select data is a count object of output data read out from the semiconductor memory corresponding to the input address.04-09-2009
20110271158METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.11-03-2011
20080215939Semiconductor memory device with fail-bit storage unit and method for parallel bit testing - There are provided a semiconductor memory device and a method for testing the same, in which when a plurality of semiconductor memory devices are under test, tester equipment can detect which one of the semiconductor memory devices fails without a separate fail memory. The semiconductor memory device with a memory cell array includes a comparing circuit configured to compare data read after having been written for parallel bit testing with each other and outputting comparison result data; and a storage and output unit configured to latch, as pass/fail data, the comparison result data output from the comparing circuit, simultaneously output the latched comparison result data via a plurality of outputs when an enable signal is activated, and simultaneously output independently applied parallel bit test comparison data via the plurality of outputs when the enable signal is not activated.09-04-2008
20090037784Semiconductor memory device having mount test circuits and mount test method thereof - A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.02-05-2009
20080282120Memory structure, repair system and method for testing the same - A memory structure is provided. The memory structure includes a memory array, an error correct code (ECC) unit, and a comparator. The memory array includes at least one memory cell being written and storing at least one original data. The ECC unit is for reading at least one tested data from the at least one memory cell, correcting the at least one tested data when there is an error occurred in the at least one tested data and outputting at least one ECC data accordingly. The comparator is for determining whether the at least one original data is substantially the same as the at least one ECC data or not and outputting an output signal indicating whether the at least one memory cell passes or fails.11-13-2008
20080288836Semiconductor integrated circuit capable of testing with small scale circuit configuration - In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.11-20-2008
20120198294Methods For At-Speed Testing Of Memory Interface - Methods for at-speed testing of a memory interface associated with an embedded memory involves in general two write operations in succession, two read operations in succession, and a capture operation using scan cells. The write and read operations may be performed during a single clock burst, two separate clock bursts in a clock signal, or two separate clock bursts in separate clock signals.08-02-2012
20090024885SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF - A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.01-22-2009
20090199058Programmable memory with reliability testing of the stored data - The invention relates, inter alia, to a method for testing a programmable memory cell having a particular memory state, the method involving the following steps of: applying a first read signal to the memory cell, with the result that the memory cell provides a first memory signal which represents its memory state; comparing the first memory signal with a threshold value in order to obtain a first comparison result; applying a second read signal to the memory cell, with the result that the memory cell provides a second memory signal which represents its memory state; comparing the second memory signal with the threshold value in order to obtain a second comparison result; assessing the integrity of the memory state using the two comparison results.08-06-2009
20090049349SEMICONDUCTOR DEVICE USING LOGIC CHIP - A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.02-19-2009
20090063917SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.03-05-2009
20090063916METHOD FOR SELF-TEST AND SELF-REPAIR IN A MULTI-CHIP PACKAGE ENVIRONMENT - A method and apparatus for operating a component including a memory device. The method includes receiving a plurality of commands and determining if a set of the plurality of commands matches a predefined pattern of commands configured to place the memory device into a test mode. Upon determining that the set of the plurality of commands matches the predefined plurality of commands, the memory device is placed in the test mode.03-05-2009
20120079331MEMORY SYSTEM - A memory system according to the embodiment comprises a cell array including cell units having p or more physical quantity levels (p is a prime of 3 or more); a code generator unit operative to convert binary-represented input data to a write code represented by elements in Zp that is a residue field modulo p; and a code write unit operative to write the write code in the cell unit in accordance with the association of the elements in Zp to different physical quantity levels, wherein the input data is recorded in (p−1) cell units, the (p−1) cell units including no cell unit that applies the same physical quantity level for write in the case where the input data is 0 and for write in the case where only 1 bit is 1.03-29-2012
20110225472READING MEMORY CELLS USING MULTIPLE THRESHOLDS - A method for operating a memory (09-15-2011
20110225471MEMORY DEVICES, TESTING SYSTEMS AND METHODS - Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.09-15-2011
20100162057Method for Detecting Disturb Phenomena between Neighboring Blocks in Non-volatile Memory - A method for detecting disturb phenomena between neighboring blocks in non-volatile memory includes, sequentially erasing and writing test data (pattern) to each block of a plurality of blocks under test in the non-volatile memory at a first time point, dividing the plurality of blocks under test into a first block group and a second block group based on ordinal number included in each block of the plurality of blocks under test, reading data from each block of the first block group at a second time point, and comparing the data with the test data written at the first time point to generate a first detecting result, and determining applicability of each block of the first block group based on the first detecting result.06-24-2010
20080307276Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.12-11-2008
20080307275CHECKING OUTPUT FROM MULTIPLE EXECUTION UNITS - Provided are a method and system checking output from multiple execution units. Execution units concurrently execute test instructions to generate test output, wherein test instructions are transferred to the execution units from a cache coupled to the execution units over a bus. The test output from the execution units is compared to determine whether the output from the execution units indicates the execution units are properly concurrently executing test instructions. The result of the comparing of the test output are forwarded to a design test unit.12-11-2008
20100185906ERROR CORRECTION CAPABILITY ADJUSTMENT OF LDPC CODES FOR STORAGE DEVICE TESTING - Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.07-22-2010
20120246527BUILT-IN SELF TEST CIRCUIT AND DESIGNING APPARATUS - According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.09-27-2012
20100218056METHOD AND SYSTEM FOR PERFORMING A DOUBLE PASS NTH FAIL BITMAP OF A DEVICE MEMORY - A method for performing a double pass n08-26-2010
20100251042DOUBLE DATA RATE MEMORY PHYSICAL INTERFACE HIGH SPEED TESTING USING SELF CHECKING LOOPBACK - An invention is provided for providing a double data rate memory physical interface having self checking loopback logic is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.09-30-2010
20100235694TEST APPARATUS AND TEST METHOD - A test apparatus includes a fail memory (AFM) for storing therein fail information in association with each of the addresses of a memory under test and a mark memory (CMM) for storing therein, in association with each of the addresses of the memory under test, validity information indicating whether the fail information stored in the AFM is valid. When the validity information read from the CMM in association with an address under test indicates that the fail information that has been stored in the AFM is invalid, the test apparatus overwrites the fail information stored in the AFM with the fail information that is newly generated by a current test. On the other hand, when the validity information read from the CMM indicates that the fail information is valid, the test apparatus updates the fail information stored in the AFM with the new fail information and writes the updated fail information back into the AFM. When overwriting the fail information that has been stored in the AFM with the new fail information, the test apparatus writes into the CMM the validity information that indicates that the new fail information is valid. Initialization of the AFM is performed in such a manner that, before and after the initialization, different validity information indicates validity of the fail information.09-16-2010
20100235695MEMORY APPARATUS AND TESTING METHOD THEREOF - A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.09-16-2010
20100125766SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.05-20-2010
20090254785TEST MODE FOR PARALLEL LOAD OF ADDRESS DEPENDENT DATA TO ENABLE LOADING OF DESIRED DATA BACKGROUNDS - One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm. The pattern generating logic further causes the data loading circuit to load each of the generated patterns of data into the buffer for transferring to a respective row of the memory cells.10-08-2009
20100269001TESTING SYSTEM AND METHOD THEREOF - Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory.10-21-2010
20100223513LATENCY DETECTION IN A MEMORY BUILT-IN SELF-TEST BY USING A PING SIGNAL - In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.09-02-2010
20110239063ACTIVE CALIBRATION FOR HIGH-SPEED MEMORY DEVICES - A system for calibrating timing for write operations between a memory controller and a memory device is described. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.09-29-2011
20110119539PATTERN GENERATOR AND MEMORY TESTING DEVICE USING THE SAME - An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.05-19-2011
20100223514SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a determination circuit that generates a determination signal by determining an error of read data read out from a memory cell array, and an I/O circuit that outputs the read data or the determination signal to outside via a data input/output terminal. The I/O circuit outputs the read data to outside at a first timing in a normal: operation mode, and in a test mode, outputs the determination signal to outside at a second timing later than the first timing. A difference between the first timing and the second timing is an integer times of a cycle of a clock signal. In this way, the determination signal can be correctly output in the test mode, because an output timing of the determination signal is controlled to be delayed from an output timing of the read data within the device.09-02-2010
20100218057CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.08-26-2010
20110035636DATA STORAGE DEVICE AND METHOD FOR WRITING TEST DATA TO A MEMORY - The invention provides a method for writing test data to a memory. In one embodiment, the memory comprises a data register. First, test data is written to a memory space of the memory. A read-back command and a read-back address of the memory space are then sent to the memory to direct the memory to read the test data from the memory space to the data register. A copy-back command and a copy-back command in a test range of the memory are then sent to the memory to direct the memory to write the test data stored in the data register to the copy-back address. Finally, when the test range of the memory has not been filled with the test data, the step of sending the read-back command and the read-back address is repeated, and the step of sending the copy-back command and the copy-back address is repeated.02-10-2011
20110119538Dynamically Replicated Memory - Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.05-19-2011
20100131810SYSTEM AND METHOD FOR IMPLEMENTING A STRIDE VALUE FOR MEMORY TESTING - Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.05-27-2010
20100131808Method For Testing Memory - A memory testing method is provided, by using the computation capability of a controller to receive the testing command the program code of a testing PC to generate random data or use an algorithm to generate testing data of specific format. Then, the method writes the data directly to the flash memory and read the data from the memory again to compare with the original data. The comparison result is transmitted back to the testing PC. The method greatly reduces the memory access frequency and I/O load of the testing PC so as to improve the testing efficiency.05-27-2010
20110179322NONVOLATILE MEMORY DEVICE AND RELATED PROGRAM VERIFICATION CIRCUIT - A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.07-21-2011
20090313512APPARATUS AND METHOD FOR MEMORY CARD TESTING - The invention provides a memory card testing apparatus for performing automated operations on memory cards. The memory card testing apparatus comprises a host device, a database, a processing unit and an interface. The host device is provided for accessing a memory card. The database maintains a plurality of test script files to be processed. The processing unit is coupled to the database for selecting a test item from one of the plurality of test script files according to a device identification number corresponding to a target device to be tested and a communication protocol associated with the memory card. The interface is connected to the processing unit and the host device for enabling the host device to execute at least one card command on the memory card according to the test item.12-17-2009
20110252283Soft Bit Data Transmission For Error Correction Control In Non-Volatile Memory - Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.10-13-2011
20080229163TEST APPARATUS, TEST METHOD AND MACHINE READABLE MEDIUM STORING A PROGRAM THEREFOR - The present invention provides a test apparatus that tests a plurality of memories under test. The test apparatus includes a data input-output section that gives and receives data to and from data input-output terminals of the plurality of memories under test, a test data supplying section that parallel supplies test data to the plurality of memories under test, a writing control section that parallel supplies a write enable signal to the plurality of memories under test, a reading control section that sequentially supplies a read enable signal to each of the plurality of memories under test, a comparing section that compares the test data sequentially read from the respective memories under test with an expected value, and a detecting section that detects, on condition that one test data is not identical with the expected value, a writing fail for the memory under test that outputs this test data.09-18-2008
20110179323Memory with Self-Test Function and Method for Testing the Same - The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.07-21-2011
20110055647PROCESSOR - A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.03-03-2011
20110055646FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT - Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (03-03-2011
20100122130Semiconductor Memory Device Supporting Read Data Bus Inversion Function and Method of Testing the Semiconductor Memory Device - Provided is a semiconductor memory device supporting a read data bus inversion (RDBI) function and a method of testing the semiconductor memory device. The method includes: providing data of an input test pattern to data input/output pads; including the data of the input test pattern in a data bus through a memory cell core block; if the data on the data bus satisfy an inversion condition, inverting and outputting the data on the data bus, and generating a flag signal indicating that the data on the data bus are inverted; comparing each of the inverted data on the data bus with the flag signal and transmitting resultant data to the data input/output pads; and determining whether the resultant data transmitted to the data input/output pads are data of an output best pattern.05-13-2010
20100122129METHOD FOR TESTING STORAGE APPARATUS AND SYSTEM THEREOF - A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in the step (b); and (d) determining that the storage unit has defect when the error bit number is larger than a error bit threshold value, wherein the error bit threshold value is smaller than a correctable bit number for a error correction code corresponding to the specific pattern.05-13-2010
20110072323Supporting scan functions within memories - A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch.03-24-2011
20110087935DRAM TESTING METHOD - A method for testing a dynamic random access memory (DRAM) includes copying a test program from the DRAM to a random access memory (RAM). Start and end physical addresses of the DRAM are respectively stored in first and second registers. First test data is written to the start physical address, and second test data is read from the start physical address. The method further includes determining whether the second test data is the same as the first test data. A fixed value is added to the start physical address to obtain a next start physical address if the second test data is the same as the first test data. The method further includes determining whether the next start physical address is less than the end physical address. A test success result is returned if the next start physical address is not less than the end physical address.04-14-2011
20090300444METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.12-03-2009
20120042220LOW-COST DESIGN FOR REGISTER FILE TESTABILITY - A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing buffer is located in the output data path between an output from the memory and an input to the comparator. The strobing buffer is configured to selectively enable the test vectors to propagate from the memory output to the comparator input.02-16-2012
20120210180BLIND AND DECISION DIRECTED MULTI-LEVEL CHANNEL ESTIMATION - A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges and (for each of the bins in the set) a corresponding portion of read values which fall into that particular bin. One or more of the bin ranges is adjusted such that the received portions of read values remain substantially the same after adjustment and after assignment of the read value to one of the set of bins after adjustment.08-16-2012
20120072793Registers with Full Scan Capability - A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.03-22-2012
20090089631MEMORY DIAGNOSIS APPARATUS - A memory diagnosis apparatus include an intra-word testing unit that tests for a coupling fault in each bit in each word in a memory, an inter-word testing unit that tests for a coupling fault between words in each sub-array each being plural words in the memory, and an inter-block testing unit that tests for a coupling fault between sub-arrays in the memory.04-02-2009
20130173974COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.07-04-2013
20090132874SYSTEM AND METHOD FOR TESTING A DATA STORAGE DEVICE WITHOUT REVEALING MEMORY CONTENT - A system and method for testing a data storage device without revealing memory content. To control the individual bits of the memory during testing each value is written into the memory according to the equation05-21-2009
20110185240EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.07-28-2011
20100262875SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A RETENTION BEHAVIOR FOR AT LEAST ONE BLOCK OF A MEMORY DEVICE HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes writing monitor data to at least one block of a memory device having finite endurance and/or retention; reading the monitor data after a period of time; determining a retention behavior of the at least one block based on the reading; and outputting a result of the determining. A memory device according to one embodiment includes a plurality of memory blocks having finite endurance and/or retention, at least one of the blocks having monitor data written therein; and circuitry for addressing the blocks. A system according to one embodiment includes a memory device having finite endurance and/or retention, the memory device comprising: a plurality of memory blocks, at least one of the blocks having monitor data written therein, wherein the at least one block has been written to a plurality of times prior to writing the monitor data; and circuitry for addressing the blocks.10-14-2010
20120173937SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF - A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.07-05-2012
20080282121Integrated Circuit and Test Method - An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.11-13-2008
20080215938MEMORY DEVICE AND RELATED TESTING METHOD - A method for testing a memory device is disclosed. The method includes: respectively writing at least one test data into a plurality of storage blocks in the memory device such that a plurality of first time written test data are stored in the storage blocks; in a read with write back test mode, reading the first time written test data from the storage blocks in the memory device and writing the plurality of first time written test data into the storage blocks to generate a plurality of second time written test data; and in a compress test mode, reading the plurality of second time written test data from the storage blocks by a compress test operation and determining whether the memory device operates erroneously according to the plurality of second time written test data and the test data.09-04-2008
20100011261Verifying Data Integrity of a Non-Volatile Memory System during Data Caching Process - To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I01-14-2010
20120185740DATA WRITING METHOD FOR NON-VOLATILE MEMORY MODULE AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a re-writable non-volatile memory module and a memory controller and a memory storage apparatus using the same are provided, wherein the re-writable non-volatile memory module has a plurality of physical writing units, and each of the physical writing units has a plurality of physical writing segments. The data writing method includes identifying at least one non-used segment among the physical writing segments of each of the physical writing units and writing a plurality of segment data streams into the physical writing units, wherein the non-used segments of the physical writing units are not used for writing the segment data. Accordingly, the data writing method can effectively use normal physical writing segments in the physical writing units.07-19-2012
20120185741APPARATUS AND METHOD FOR DETECTING A MEMORY ACCESS ERROR - Provided are an apparatus and method for detecting a memory access error in a computer system. The apparatus and method may intercept a sub-system that processes a request for access to a memory, and may be applied to various computer systems without causing any performance deterioration. The apparatus includes a sub-system configured to process a request for access to a memory, and an interception module configured to detect a memory access address by intercepting the sub-system.07-19-2012
20080301508SEMICONDUCTOR MEMORY DEFECT ANALYSIS METHOD AND DEFECT ANALYSIS SYSTEM - A defect analysis method for semiconductor memory includes: reading out an address bit map corresponding to an input kind of the memory macro from a database which stores address bit maps respectively corresponding to memory macro kinds; inputting size information of the memory macro; translating a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the address bit map read out, of the memory macro, and generating a fail bit map in the standard disposition; inputting disposition information of the memory macro; and translating a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and generating a fail bit map of the memory macro.12-04-2008
20120266034SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section.10-18-2012
20120089877CONTROL DEVICE AND DATA STORAGE DEVICE - When write request signal is input from a host device 04-12-2012
20120096323DIAGNOSTIC CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a certain amount of data is held in the memory cells, and after a state of the data held in the memory cell is transferred into an indefinite state, data autonomously held in the memory cell is read, and a change of the threshold voltage of transistors is diagnosed on the basis of the distribution of the data autonomously held in the memory cell.04-19-2012
20120096322SEMICONDUCTOR PACKAGE - A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.04-19-2012
20100131809APPARATUS AND METHODS FOR GENERATING ROW-SPECIFIC READING THRESHOLDS IN FLASH MEMORY - A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.05-27-2010
20080235540TEST APPARATUS AND ELECTRONIC DEVICE - A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data, a first fail memory storing a grouping of the read address and the fail data in a case where the read data and the expected value are not the same, a second fail memory storing fail data concerning addresses corresponding to each address of the memory under test, and an updating section updating fail data stored in the second fail memory and corresponding to the read address based on the grouping of the address and the fail data read from the first fail memory.09-25-2008
20080201623EMBEDDED ARCHITECTURE WITH SERIAL INTERFACE FOR TESTING FLASH MEMORIES - A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.08-21-2008
20110314347MEMORY ERROR DETECTING APPARATUS AND METHOD - A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.12-22-2011
20120290889HIGH-SPEED SERIAL INTERFACE BRIDGE ADAPTER FOR SIGNAL INTEGRITY VERIFICATION - A loopback card includes a connector configured to connect to an IO interface and emulate a storage device interface. The connector includes a port configured to receive a set of signals from the IO interface and transmit them to a redriver. The connector is configured to receive the set of signals from the redriver and transmit them from the redriver to the IO interface. The connector includes control signal inputs configured to receive control signals from the IO interface. The connector further includes one or more logic gates configured to receive the control signals. The one or more logic gates apply a logic operation on the control signals to generate an output and route the output to the IO interface through the connector. The redriver is operably connected to the port and configured to receive the set of signals from the port and transmit them back to the port.11-15-2012
20120030531Safe Memory Storage By Internal Operation Verification - The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.02-02-2012
20120030530DETERMINISTIC DATA VERIFICATION IN STORAGE CONTROLLER - Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.02-02-2012
20130091394DATA PROCESSING APPARATUS AND VALIDITY VERIFICATION METHOD - A data processing apparatus includes a ROM (Read Only Memory) having a validity verification program stored therein, an auxiliary storage device including a plurality of storage areas having a plurality of target verification data stored therein, an execution unit configured to perform a validity verification process on the plural target verification data in accordance with the validity verification program. An order of priority is assigned to the plural target verification data. The plural storage areas have addresses that is recognizable by the execution unit. The execution unit is configured to determine validity of each of the plural target verification data based on the order of priority until one of the plural target verification data is determined to be valid.04-11-2013

Patent applications in class Read-in with read-out and compare

Patent applications in all subclasses Read-in with read-out and compare