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Memory testing

Subclass of:

714 - Error detection/correction and fault detection/recovery

714699000 - PULSE OR DATA ERROR HANDLING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714719000 Read-in with read-out and compare 112
714723000 Error mapping or logging 47
714721000 Electrical parameter (e.g., threshold voltage) 37
714722000 Performing arithmetic function on memory contents 10
Entries
DocumentTitleDate
20100058128SHARED DIAGNOSIS METHOD FOR AN INTEGRATED ELECTRONIC SYSTEM INCLUDING A PLURALITY OF MEMORY UNITS - A shared diagnosis method may be for an electronic integrated system embedding a plurality of memory units associated with Built In Self Test (BIST) hardware portions for executing a test on memory locations of the memory units. A FAIL signal may be provided from the hardware portions, together with the memory locations of the memory units on which the test is executed. The method may include loading of address, state and data signals, generated during the test on the memory locations, in a series of bitmapping registers and supplied by multiplexer devices, which receive as inputs the address, state, and data signals from the memory units and from the hardware portions. The enabling for the loading of the bitmapping registers is through the processing of a Fail signal in a counter supplied by a multiplexer device receiving the Fail signals from the hardware portions.03-04-2010
20100058127SEMICONDUCTOR DEVICE - To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.03-04-2010
20110302467Memory test system with advance features for completed memory system - In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.12-08-2011
20090193302SEMICONDUCRTOR DEVICE - A semiconductor device capable of reducing a memory area of a test circuit required for storing fail-information is provided. In the test circuit, for determining right/wrong of information obtained by memory access, specific fail-information among pieces of fail-information sequentially obtained in response to wrong-determination result is held in a first memory section; and differences in serial two pieces of fail-information sequentially continuing from the specific fail-information are held in a second memory section. The test circuit, when it obtains differences based on pieces of fail-information sequentially obtained with a wrong-determination result at the time of holding the specific fail-information as a base point, sequentially adds subsequent differences to the specific fail-information to decompress subsequent pieces of fail-information.07-30-2009
20130031429Data Recovery for Defective Word Lines During Programming of Non-Volatile Memory Arrays - The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded. Once the recovery is complete the block can be reprogrammed and the temporary parity pages in the controller may be discarded upon successfully reprogramming.01-31-2013
20130086440GENERIC MARCH ELEMENT BASED MEMORY BUILT-IN SELF TEST - Method for testing a memory under test (04-04-2013
20100077268APPARATUS AND METHOD FOR TESTING SETUP/HOLD TIME - An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.03-25-2010
20130080847MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES - A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.03-28-2013
20100042879Method of memory build-in self-test - The present invention discloses a memory build-in self-test comprising steps of: (a) determining whether there is redundant address in the ROM; (b) when there is redundant address for storing standard check code, transferring the coefficient file in the ROM to a predetermined format; (c) producing a self-test logic and a standard check code corresponding to the ROM via design tool; (d) writing the standard check code into the redundant address and generating a new ROM. The present invention can assure that the standard check code and coefficient can be simply revised via corresponding way of Mask Change, so as to detect the damages of ROM by using memory build-in self-test (MBIST) which does not need to remake a whole set of Mask to revise the standard check code outside the ROM, so as to save cost and time, and lower the difficulty to update the product.02-18-2010
20100042878TEST APPARATUS AND TEST METHOD - Provided is a test apparatus for testing a plurality of devices under test, the test apparatus including: a data supplying section that concurrently supplies test data to the plurality of devices under test; a writing control section that controls the test data to be concurrently written to the plurality of devices under test; and a reading control section that successively reads the test data from each of the plurality of devices under test. The plurality of devices under test may be a plurality of memories under test.02-18-2010
20090158103TEST APPARATUS AND TEST METHOD - The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase difference between the first and second delay clock signals to a desired phase difference; a deciding section that decides the quality of the data signal from the DUT based on a result obtained by acquiring the delay data signal when the second delay clock signal is changed.06-18-2009
20090158102Methods, devices, and systems for experiencing reduced unequal testing degradation - One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input paths which do not receive test signals. Therefore, rather than being held in a fixed state during the burn-in process, the remaining inputs are toggled as well. Consequently, they degrade at a more similar rate as their counterpart inputs that did receive test signals.06-18-2009
20090125762APPARATUS FOR REPAIRING AND/OR TESTING A MEMORY DEVICE - Embodiments of the invention relate to an apparatus for repairing and/or testing at least one memory device having a plurality of memory cells, the apparatus comprising an interface which is adapted to accommodate a memory device; means for determining the type of memory device; a selection memory for storing at least one repair and/or test program; and selection means for selecting a repair and/or test program from the selection memory. Another embodiment of the invention relates to a method for repairing and/or testing at least one memory device having a plurality of memory cells, the method comprising: connecting a memory device to an apparatus for repairing and/or testing a memory device; determining the type of memory device by means of said apparatus; selecting at least one repair and/or test program from a selection memory being part of the apparatus for repairing and/or testing a memory device; executing the selected program, and thereby deactivating addresses of defective memory cells of the memory device and/or reallocating addresses of functional memory cells to addresses of defective memory cells.05-14-2009
20090125761Method for controlling a DRAM - A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y.05-14-2009
20090125760Method and apparatus for safe parameterization in accordance with IEC 61508 SIL 1 to 3 or EN 954-1 Categories 1 to 4 - The invention relates to a method and an apparatus for safe parameterization in accordance with IEC 61508 SIL 1 to 3 or EN 954-1 Categories 1 to 4 of safe electronic appliances.05-14-2009
20090044062Method of testing a memory module and hub of the memory module - A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.02-12-2009
20090044061STRUCTURE AND METHOD FOR DETECTING ERRORS IN A MULTILEVEL MEMORY DEVICE WITH IMPROVED PROGRAMMING GRANULARITY - An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.02-12-2009
20090307543TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE - An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.12-10-2009
20120192021METHOD OF TESTING ASYNCHRONOUS MODULES IN SEMICONDUCTOR DEVICE - A method of testing a semiconductor device that includes first and second mutually asynchronous modules, a buffer for storing transaction data for read/write operations from the first module and transferring it to the second module synchronously with the data rate of the second module, and an inhibit input. The second module receives the transaction data from the buffer and transfers the data to a data output when the inhibit signal is de-asserted and not when the inhibit signal is asserted. The method of testing includes repeatedly: asserting the inhibit signal; providing test transaction data to the first module and storing the data in the buffer while the inhibit signal is asserted; de-asserting the inhibit signal so that the second module transfers test transaction data received from the buffer to the data output synchronously with the data rate of the second module; and capturing deterministically test transaction data from the output of the second module.07-26-2012
20130061101NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH LOAD LEVELING AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page.03-07-2013
20130061102SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.03-07-2013
20090271669High-Speed Testing of Integrated Devices - A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.10-29-2009
20120117431EFFICIENT DETECTION OF ERRORS IN ASSOCIATIVE MEMORY - A method for error detection includes storing in an associative memory (05-10-2012
20120117430MEMORY CARD - A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.05-10-2012
20120117429BASEBOARD MANAGEMENT CONTROLLER AND MEMORY ERROR DETECTION METHOD OF COMPUTING DEVICE UTILIZED THEREBY - A method detects a memory error of a computing device using a baseboard management controller (BMC) of the computing device. The BMC includes a microprocessor and a storage system. The method reads data of a state register of a processor of the computing device when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor. Then the method determines whether the internal error is a multiple-bit error of a memory of the computing device according to the read data. Upon the condition that the internal error is the multiple-bit error, the method records error information of the multiple-bit error in the storage system.05-10-2012
20120198292TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a memory under test, comprising a testing integrated circuit device that tests the memory under test and includes an internal memory storing test information including at least one of a test result and test data for a partial memory region of the memory under test; an external memory that stores the test information for an entire memory region of the memory under test; and a memory controller that is connected to the external memory and transmits test information for a memory region of a test target between the external memory and the internal memory. Also provided is a test method.08-02-2012
20090006913Semiconductor memory device having test address generating circuit and test method thereof - A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.01-01-2009
20090006912Semiconductor memory device having burn-in test mode and method for driving the same - A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.01-01-2009
20130166973STORAGE-MEDIUM DIAGNOSIS DEVICE, STORAGE-MEDIUM DIAGNOSIS METHOD - A storage-medium diagnosis includes a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium; a higher-access executing unit that accesses a region corresponding to access request from a higher-level device, and stores a result of the access as a diagnosis result in the storage unit; a diagnosis-region identifying unit that identifies a diagnosis region to be diagnosed next on the basis of the respective diagnosis results of the subregions stored in the storage unit; and a diagnosis executing unit that accesses and diagnoses the diagnosis region identified by the diagnosis-region identifying unit, and stores a result of the diagnosis in the storage unit. The storage-medium diagnosis can reduce the time used for diagnosis of the storage medium and suppress degradation in performance even during operation.06-27-2013
20120239992METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE - A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.09-20-2012
20080294950DOUBLE DRAM BIT STEERING FOR MULTIPLE ERROR CORRECTIONS - A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 11-27-2008
20080294949MEMORY ACCESS SYSTEM - When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.11-27-2008
20080301507System and Method for Repairing a Memory - A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.12-04-2008
20110161752ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER - REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.06-30-2011
20100037108HIGH-SPEED SEMICONDUCTOR MEMORY TEST DEVICE - A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock signal and converting the frequency of the reference clock signal to a second clock signal in response to the control signal, and a test data converting unit receiving the first test data, converting the first test data to second test data synchronously with the second clock signal and providing the second test data to a semiconductor memory device under test.02-11-2010
20110302469NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array, a write control circuit, a latch circuit, an address control circuit, a scan control circuit, and an address latch circuit. The write control circuit executes write and verify for each page of the memory cell array. The latch circuit holds data of the verify result. The address control circuit divides the page into zones and sequentially selects the address of each of the zones. The scan control circuit executes scan so as to count the number of fail bits in zone selected by the address control circuit and determine whether the number of fail bits is not more than the number of allowable bits. The address latch circuit holds the address of a no fail zone, out of the plurality of zones, in which the number of fail bits is 0.12-08-2011
20110302468Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.12-08-2011
20120110399ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.05-03-2012
20120110398DATA ERROR CHECK CIRCUIT, DATA ERROR CHECK METHOD, DATA TRANSMISSION METHOD USING DATA ERROR CHECK FUNCTION, SEMICONDUCTOR MEMORY APPARATUS AND MEMORY SYSTEM USING DATA ERROR CHECK FUNCTION - Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.05-03-2012
20120011409DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY - Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.01-12-2012
20110296259TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY - A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit are tested at speed.12-01-2011
20090063913Semiconductor integrated circuit - Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.03-05-2009
20100083062High performance pulsed storage circuit - The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic data input; an output for outputting said value stored in said storage element; a pulse generator for generating pulses in response to a clock signal, said pulse generator comprising a diagnostic output and a functional output and being responsive to receipt of a diagnostic enable signal at said diagnostic select signal input to output said generated pulses at said diagnostic output and being responsive to receipt of a diagnostic disable signal at said diagnostic select signal input to output said generated pulses at said functional output; an operational path switch for receiving said pulses from said functional output and being responsive to receipt of each of said pulses to provide a transmission path from said operational data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said operational data input; and a diagnostic path switch for receiving said pulses from said diagnostic output and being responsive to receipt of each of said pulses to provide a transmission path from said diagnostic data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said diagnostic data input.04-01-2010
20090070643System and Method for Testing a Large Memory Area During Processor Design Verification and Validation - A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.03-12-2009
20100269000METHODS AND APPARATUSES FOR MANAGING BAD MEMORY CELL - A method for managing a bad cell is provided. The method includes reading status data from a page buffer and detecting a location of a bad cell from the status data. The method may further include remapping a bad address for the bad cell to a spare address for a spare cell in the same page.10-21-2010
20100268999MEMORY TESTING WITH SNOOP CAPABILITIES IN A DATA PROCESSING SYSTEM - A method of testing a memory includes generating a plurality of addresses, such as a test address, accessing contents of each of the plurality of addresses and storing them in storage circuitry, performing a test on the plurality of addresses, accessing the memory test circuitry by sending an access address to snooping circuitry, determining if the access address matches at least one of the plurality of addresses and generating at least one hit indicator in response thereto, generating a snoop miss indicator, determining if it indicates a miss, if it indicates a miss, accessing the memory in response to the access address, and if it does not indicate a miss, either storing snooped data from a interconnect master to a selected portion of the storage circuitry or reading the snooped data from the selected portion of the storage circuitry to the interconnect master.10-21-2010
20090150728HIGH SPEED SERIAL TRACE PROTOCOL FOR DEVICE DEBUG - Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of serial ports needed for data transfer is significantly less than a complimentary parallel port configuration. Additional functional blocks on the chip process the data for high speed serial output. The functional blocks format information into subchannels, arbitrate data, append protocol, perform data integrity checks, and serialize the data. The additional blocks built on the chip to support the serial ports consume less chip space than the space consumed by the number of parallel ports required to provide equivalent data transfer rates. The process operates in near real time and may use time stamping to correlate and reconstruct data from different information sources. An input port receives data from the external test component to modify registers or memory, set break points, modify hardware status, communicate with processors, or modify other operating conditions to debug the hardware device.06-11-2009
20100125765UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST - An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.05-20-2010
20100122128TEST INTERFACE FOR MEMORY ELEMENTS - A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.05-13-2010
20090313511SEMICONDUCTOR DEVICE TESTING - A semiconductor device test circuit includes a data producing unit to produce first test data to be fed into a semiconductor device, and expected value data; a first data retaining unit to retain the first test data, and feed the first test data into the semiconductor device; a second data retaining unit to retain the expected value data; a comparison unit to compare output data outputted through the first data retaining unit and the expected value data outputted from the second data retaining unit to supply data indicating comparison result between the output data and the expected value data; and a switching unit to switch the data fed into the second data retaining unit between the expected value data and the output data, wherein the first data retaining unit and the second data retaining unit form parts of a scan chain into which second test data may externally be fed.12-17-2009
20090265591SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.10-22-2009
20090210758METHOD FOR REDUCING DATA ERROR WHEN FLASH MEMORY STORAGE DEVICE USING COPY BACK COMMAND - A method for a flash memory storage device to use a copy back command includes the following steps. The method includes the step of copying a data in a first block of a flash memory to a buffer outside the flash memory, checking if the data in the buffer is correct, and copying the data in the first block of the flash memory to a second block in the flash memory when the data in the buffer is correct.08-20-2009
20090282303BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM - An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.11-12-2009
20080209283SHARED LATCH FOR MEMORY TEST/REPAIR AND FUNCTIONAL OPERATIONS - A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.08-28-2008
20090282304Debug circuitry - An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.11-12-2009
20090282302Multi-Stage Data Processor With Signal Repeater - A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.11-12-2009
20090287971METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE - A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.11-19-2009
20090287972TEST METHOD FOR NONVOLATILE MEMORY DEVICE - A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated.11-19-2009
20090300439Method and Apparatus for Testing Write-Only Registers - There is disclosed a test circuit for testing an integrated circuit containing at least one write-only register and providing at least one output signal through at least one output pin. The test circuit may include a test mode decoder circuit to enable a test mode and a data selector circuit to select at least a portion of data stored in the at least one write-only register as test data. The test data may be output from the integrated circuit through the at least one output pin.12-03-2009
20110209012Method and apparatus for optimizing address generation for simultaneously running proximity-based BIST algorithms - The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CM08-25-2011
20090265592MEMORY DEVICE AND TEST METHOD THEREOF - The present invention provides a memory device and a test method thereof that can detect a coupling fault between two memory arrays. The memory device includes a memory array unit and a test module. The memory array unit includes a value memory array and a mask memory array. The test module is coupled to the memory array unit for generating a test pattern signal that is based on a test rule and that is provided to the memory array unit for performing testing on the memory array unit. The test rule includes a number (M) of first test segments for testing the value memory array and a number (N) of second test segments for testing the mask memory array. The first test segments and the second test segments are interleaved in the test rule.10-22-2009
20080282119MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME - A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.11-13-2008
20080288834VERIFICATION OF MEMORY CONSISTENCY AND TRANSACTIONAL MEMORY - A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.11-20-2008
20080201621TEST APPARATUS - It is an object of the test apparatus according to the present invention to effectively manage test results. The test apparatus includes a test section that executes testing of each cell of the memory under test; a fail information storage section that stores in a fail memory fail information corresponding to each cell of the memory under test that indicates pass/fail of each cell; a counting section that counts a number of defective cells detected in each block for every block in the memory under test; a reading request receiving section that receives a request to read the fail information of each cell included in each block; a comparing section that compares the number of defective cells in a reading target block to a predetermined reference number; a converting section that, in a case where the number of defective cells in the reading target block exceeds the predetermined reference value, converts into a value indicating defectiveness a plurality of consecutive pieces of fail information in a response data string that includes the fail information of each cell in the reading target block to be returned in response to the reading request; and a compressing section that compresses the response data string and returns the compressed response data string.08-21-2008
20120198291LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED MEMORIES WITH ASYNCHRONOUS INTERFACES - A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.08-02-2012
20110271157TEST CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memory block; a second fail detection unit configured to detect a fail of a memory cell group of a second memory block by combining a plurality of second test data signals outputted from the memory cell group of the second memory block; a common fail detection unit configured to detect a fail of the memory cell groups of the first and second memory blocks by combining the plurality of first test data signals and the plurality of second test data signals; and a fail determination unit configured to output detection results of the first and second fail detection units or a detection result of the common is fail detection unit according to the detection results of the first and second fail detection units.11-03-2011
20090164855METHOD FOR SCRUBBING STORAGE IN A COMPUTER MEMORY - A method for scrubbing storage in a computer memory which includes a plurality of memory modules each having plurality of memory chips. The method includes selecting a pattern that correlates with physical structures for scanning the memory chips of the memory modules for errors, scanning a memory chip of a memory module for errors based upon the selected pattern. The method further includes successively scanning remaining memory chips of the respective memory module for errors when an error is found in the scanned memory chip, and scanning a memory chip of another memory module when an error is not found in the scanned memory chip of the respective memory module.06-25-2009
20090164856SYSTEM AND METHOD FOR INPUT/OUTPUT CHARACTERIZATION - A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state. A bi-directional element is connected to receive an output of the second storage element, the bi-directional element feeding the output of the second storage element to an input of the first storage element, such that capture of a state change at the output of the first storage element at the output of the first storage element is facilitated during the second operating state.06-25-2009
20120198293STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.08-02-2012
20090063914Content-Addressable Memories and State Machines for Performing Three-Byte Matches and Secondary Matches, and for Providing Error Protection - A method and system for detecting matching strings in a string of characters utilizing content addressable memory using primary and secondary matches is disclosed.03-05-2009
20090063912Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation - A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.03-05-2009
20090024884MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES - A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.01-22-2009
20090199057March DSS: Memory Diagnostic Test - Diagnostic march tests are powerful tests that are capable of detecting, identifying and locating faults in memories. While March SS was published for detecting simple static faults, no test has been published for identifying all faults and locating their involved memory cells. In this report, we target all published simple static faults. We identify faults that can not be distinguished due to their analogous behavior, and we provide a new 46n diagnostic test for the rest named March DSS. March DSS is the first test that is capable of identifying all distinguishable march test and yet has a lower time complexity.08-06-2009
20090083592SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.03-26-2009
20090083591Method and Apparatus For Recording High-Speed Input Data Into a Matrix of Memory Devices - For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.03-26-2009
20090049348SEMICONDUCTOR STORAGE DEVICE - This semiconductor storage device comprises a test mode based on test data input from the outside. A test data register temporarily retains the test data, while a test code register temporarily retains a test code corresponding to the test data. A test-code-match detection circuit detects a match between a test code retained in the test code register and a desired test code to output a match signal. When the match signal is output, a control circuit outputs the test data retained in the test data register to the first one of a plurality of shift registers in a test data latch circuit. Further, the control circuit inputs the test data returned from the last one of the plurality of shift registers in the test data latch circuit.02-19-2009
20090063915MANAGING PURGEABLE MEMORY OBJECTS USING PURGE GROUPS - Memory objects associated with a portion of a cache (e.g., data blocks of a media file) are assigned a value based on their importance to an application that is consuming memory objects. The values are used to assign the data blocks to purge groups. The purge groups are a labeling mechanism for determining a purge order. A memory object associated with a first data block assigned to a first purge group may be purged before a memory object associated with a second data block assigned to a second purge group. As new data blocks are received by the application (e.g., from disk or a network connection), the blocks are assigned a value and added to a purge group. In some cases, the data blocks arrive out of order (e.g., order of consumption). Memory objects can be reassigned to a different purge group when new data blocks are added or reclaimed.03-05-2009
20120079330TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE - According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.03-29-2012
20080263414SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.10-23-2008
20110231716DIAGNOSIS FLOW FOR READ-ONLY MEMORIES - A system and a method for diagnosis flow for a read-only memory (ROM) includes determining whether a window of the ROM is faulty, based on a pre-computed signature and a computed signature corresponding to the window. Based on the determination, the size of the window is reduced to form at least two reduced windows. It is further ascertained whether the at least two reduced windows are faulty based on pre-computed signatures corresponding to the at least two reduced windows and computed signatures corresponding to the at least two reduced windows.09-22-2011
20110231718MEMORY REPAIR - A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.09-22-2011
20110231717SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.09-22-2011
20090100302APPARATUS AND METHOD FOR DISK READ CHECKING - An apparatus and method for controlling a disk drive is provided. A disk lubricant sweep component for periodically initiates a disk lubricant spreading action. A disk data read check component checks data at one or more LBAs during the disk lubricant sweep. The apparatus may cache data from LBAs that have been checked by the disk data read check component and found correct and record LBAs that have been found correct, so that they can be omitted from subsequent operation of the read check component. The apparatus may further comprise an error checking and correcting component for checking and correcting data found incorrect by reason of a soft error, and an error reporting component for reporting on one or more LBAs that have been checked and found incorrect by reason of a hard error.04-16-2009
20090172479SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.07-02-2009
20090222702Method for Operating a Memory Device - In the method for operating a memory device which has a number of blocks, blocks are marked as intact, suspect, or defective. Blocks marked as suspect are monitored. A device for operating a memory device and a memory device.09-03-2009
20090249139Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.10-01-2009
20090254784SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output port. The ODT circuit is provided between the data input-output port and a termination port. The JTAG circuit controls the ODT circuit in response to an instruction such that the data input-output port and the termination port are electrically connected with each other.10-08-2009
20100275074RUNTIME PROGRAMMABLE BIST FOR TESTING A MULTI-PORT MEMORY DEVICE - One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.10-28-2010
20100275073METHOD AND DEVICE FOR BAD-BLOCK TESTING - Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing is postponed until the end user is in possession of the flash memory device. In some embodiments, after user data is received by the flash memory device from a host device, one or more blocks of the flash memory device are subjected to bad-block testing.10-28-2010
20090249136ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER - System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.10-01-2009
20090249137TESTING MODULE, TESTING APPARATUS AND TESTING METHOD - There is provided a testing module including a designation information storing section that stores thereon designation information designating an order of decoding fundamental patterns, a fundamental pattern storing section that stores thereon the fundamental patterns in a data form, a plurality of pattern generating sections each of which has a designation information temporary storing section that temporarily stores thereon part of the designation information, where each pattern generating section generates a test pattern to be supplied to a device under test by decoding the fundamental patterns in an order designated by the partial designation information stored on the designation information temporary storing section, a plurality of position information storing sections each of which stores thereon, in association with a corresponding one of the plurality of pattern generating sections, position information designating a read position from which the designation information is read from the designation information storing section, and an information transmission path that is shared by the plurality of pattern generating sections, where the information transmission path transmits the partial designation information from the designation information storing section to the designation information temporary storing section in each pattern generating section.10-01-2009
20080313511SYSTEM-IN-PACKAGE AND METHOD OF TESTING THEREOF - A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.12-18-2008
20080313510Systems and devices including memory with built-in self test and methods of making and using the same - Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. In one or more embodiments, the test module can include a linear-feedback shift register.12-18-2008
20130219235MEMORY SYSTEM AND TEST METHOD THEREOF - According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result.08-22-2013
20090259895SEMICONDUCTOR MEMORY DEVICE PARALLEL BIT TEST CIRCUITS - Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.10-15-2009
20080307274Memory apparatus and method and reduced pin count apparatus and method - A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-in self test device is used to detect whether the memory device under test has any error during a post-fuse stage. The memory apparatus is capable of promptly finding the address of a defect cell in the memory device under test such that repairs can be performed during a fuse stage. Furthermore, the invention reduces the pin count required during testing the memory device under test. Thus, the cost of testing equipment is reduced and the performance of memory testing is enhanced.12-11-2008
20090282305STORAGE SYSTEM WITH DATA RECOVERY FUNCTION AND METHOD THEREOF - A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for one or more times to assure the accuracy of reading data and enhance the data reliability effectively. The data recovery procedure includes the steps of providing test data by a test data generator of the storage system, writing the test data into a memory block where error data is found, finding an error bit by reading the test data, reducing the error to a recoverable range of the ECC technique by the recovery procedure. If the error bit cannot be found or reduced to a recoverable range of the ECC technique within an upper limit of the number of tests, the memory block is marked as bad.11-12-2009
20100153794SYSTEM AND METHOD FOR ON-BOARD TIMING MARGIN TESTING OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.06-17-2010
20100153793APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT - Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.06-17-2010
20090094493SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read, a sense amplifier for amplifying the read data signal, a selection unit for selecting a data signal having a second number of bits forming a part of the data signal amplified by the sense amplifier, and an error detection/correction unit for performing error detection and correction based on at least a part of the selected data signal having the second number of bits, wherein the selection by the selection unit is performed based on a row address.04-09-2009
20100169725MEMORY MODULE TESTER - a memory module test system for testing a plurality of memory modules includes a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module. The test system further includes an interface configured to receive a test program for testing the memory module, and a gate array configured to transmit the test program to the buffers using a Joint Test Action Group (JTAG) protocol and to read test results of the test program from the buffers using the JTAG protocol.07-01-2010
20100174955TEST AND BRING-UP OF AN ENHANCED CASCADE INTERCONNECT MEMORY SYSTEM - A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.07-08-2010
20120173936CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS - Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.07-05-2012
20090300440DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.12-03-2009
20100229056System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry - An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.09-09-2010
20090077436METHOD FOR RECORDING MEMORY PARAMETER AND METHOD FOR OPTIMIZING MEMORY - The invention relates to a method for recording a memory parameter and a method for optimizing a memory. In the invention, adjusted enhancement parameter data can be stored in a non-volatile memory of a memory module. Then, the setting value of a parameter of a memory module is portable, and users can write the needed setting value of the memory parameter into the non-volatile memory of the memory module. In other words, in the invention, no matter whether the memory module is applied to the same computer or not, the enhancement parameter data can be applied to prevent the users from repeatedly setting the memory parameter of the memory module in different computers.03-19-2009
20090077435TESTING DEVICE, TESTING METHOD, COMPUTER PROGRAM PRODUCT, AND RECORDING MEDIUM - There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.03-19-2009
20100162056SEMICONDUCTOR DEVICE - A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (06-24-2010
20100229055Fault Diagnosis For Non-Volatile Memories - Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).09-09-2010
20100218054Secure Scan Design - A circuit configuration for testing integrated circuitry featuring a number of system scan flip flops wired in series and connected to the integrated circuitry for inputting test signals and receiving test data back. At the front and back ends of the system scan flip flops there is an input multiplexer and an output multiplexer, each with a control input tied to a comparator. The multiplexers isolate the test circuitry until a predetermined scan key is received. When the comparator receives a k-bit scan key it enables the multiplexer to pass test data to the system scan flip flops.08-26-2010
20100235691MEMORY MODULE AND ON-LINE BUILD-IN SELF-TEST METHOD THEREOF FOR ENHANCING MEMORY SYSTEM RELIABILITY - A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.09-16-2010
20100235692MEMORY TEST CIRCUIT AND PROCESSOR - A memory test circuit for testing a memory including a first circuit for performing a logic operation of a test signal, which determines whether the memory is operated in a test mode or in an ordinary operation mode, and an expected value representing a value which is expected to be set to data read from the memory, and a second circuit for outputting an exclusive OR of an output signal from the first circuit and the data read from the memory.09-16-2010
20100235693SOLID STATE DRIVE TESTING APPARATUS AND METHOD - Provided are apparatus and method of testing solid state drives. The method includes accommodating solid state drives to be tested in a magazine with one or more cassettes, sorting the solid state drives into operable solid state drives or defective solid state drives by testing electrical characteristics, and loading the sorted solid state drives.09-16-2010
20100211834DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.08-19-2010
20100251041MEMORY CONTROLLING APPARATUS AND METHOD - A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.09-30-2010
20100199134DETERMINING SECTOR STATUS IN A MEMORY DEVICE - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.08-05-2010
20090249138Semiconductor memory apparatus for reducing bus traffic between NAND flash memory device and controller - Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced.10-01-2009
20090319840SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a nonvolatile memory functioning as a main memory unit, a volatile memory functioning as a buffer unit of the nonvolatile memory, a controller, an ECC buffer, a parity syndrome circuit, an ECC control circuit, a multiplexer, and an ECC error position decoder.12-24-2009
20100223510NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND DEFECT MANAGEMENT METHOD FOR NONVOLATILE MEMORY DEVICE - A life parameter generator generates life parameters related to the life of a nonvolatile memory device by using parameters related to allowable capacity for memory defect and occurrence capacity for memory defect. The life parameters are stored in a life parameter storing block of a nonvolatile memory. An access device reads and displays the stored life parameters. Thus, the user can precisely know the life of the nonvolatile memory device or the moment when a device having a built in nonvolatile memory such as a portable audio becomes unusable.09-02-2010
20110119537PATTERN GENERATOR - An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.05-19-2011
20130132785DOUBLE DATA RATE SIGNAL TESTING ASSISTANT DEVICE - A DDR signal testing assistant device includes a body. The body is detachably locked to a motherboard integrated with a DDR connector. The DDR connector defines a plurality of pins. The body defines a plurality of testing holes corresponding and mating with the pins. Each testing hole of the body is marked with characters. The characters indicate the denomination or property of each corresponding pin of the DDR connector.05-23-2013
20100332924AT-SPEED SCAN TESTING OF MEMORY ARRAYS - An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.12-30-2010
20100332925SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.12-30-2010
20100223511AT-SPEED BITMAPPING IN A MEMORY BUILT-IN SELF-TEST BY LOCKING AN N-TH FAILURE - In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.09-02-2010
20100218055Implementing Enhanced Array Access Time Tracking With Logic Built in Self Test of Dynamic Memory and Random Logic - A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.08-26-2010
20110004794SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.01-06-2011
20110113295SUPPORT ELEMENT OFFICE MODE ARRAY REPAIR CODE VERIFICATION - A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.05-12-2011
20100223512SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT IN SELF TESTING USING MICROCODE SEQUENCERS - Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.09-02-2010
20090217111EVALUATION METHOD AND EVALUATION SYSTEM FOR SEMICONDUCTOR STORAGE DEVICE - An evaluation method is proposed to evaluate reliability of a nonvolatile memory in a semiconductor storage device with respect to data writing and data reading. While power is being supplied to the semiconductor storage device, a test program and the control program are written in a storage unit of the semiconductor storage device. The test program being written to control execution of an evaluation test performed for evaluating the reliability of the nonvolatile memory and generate a simulated access command identical to an access command input externally for accessing the nonvolatile memory. Access to the nonvolatile memory is controlled according to the test program and control program in the storage unit.08-27-2009
20100064188FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS - In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.03-11-2010
20100064187BAD BLOCK IDENTIFICATION METHODS - A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed to the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.03-11-2010
20100058126Programmable Self-Test for Random Access Memories - A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.03-04-2010
20100241914CONTROLLER HAVING FLASH MEMORY TESTING FUNCTIONS, AND STORAGE SYSTEM AND TESTING METHOD THEREOF - A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.09-23-2010
20110078521TRANSITION FAULT TESTING FOR A VON-VOLATILE MEMORY - A method is for testing a non-volatile memory. A base data pattern is defined for a first pageset of the non-volatile memory. The non-volatile memory has a plurality of pages which comprise words. The base pattern is arranged so that each bitpair of a plurality of bitpairs that includes one of a group consisting of even bitpairs and odd bitpairs formed from all of the words exhibits all possible bitpair transitions during sequential accesses of the pages of the plurality of pages. The base pattern is stored in the first pageset. The pages of the plurality of pages of the first pageset are accessed sequentially.03-31-2011
20110029827METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST - In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.02-03-2011
20100115352METHOD FOR EVALUATING SRAM MEMORY CELL AND COMPUTER READABLE RECORDING MEDIUM WHICH RECORDS EVALUATION PROGRAM OF SRAM MEMORY CELL - A method for evaluating an SRAM memory cell in which the time required for designing the SRAM memory cell can be shortened by evaluating static noise margin in a shortened time. A recording medium which records an evaluation program is also provided. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a first inverter of the SRAM memory cell, and the first proximity curve function is specified by fitting the input/output characteristic data of the first inverter to the proximity curve. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a second inverter of the SRAM memory cell, and the second proximity curve function is specified by fitting the input/output characteristic data of the second inverter to the proximity curve. A third proximity curve function which is a function generated by mirror-inverting the second proximity curve function with respect to the Y axis is specified, and a static noise margin is specified based on an extremal value of a difference curve function which is the difference between the first proximity curve function and the third proximity curve function.05-06-2010
20100115351DATA STORAGE APPARATUS, DATA STORAGE CONTROLLER, AND RELATED AUTOMATED TESTING METHOD - A data storage controller for controlling each data access of a data storage element is disclosed. The data storage controller includes a processing unit and a storage unit. The processing unit is utilized for executing an automated testing program on the data storage element for automated testing. The storage unit is coupled to the processing unit and utilized for storing the automated testing program.05-06-2010
20100088558COMPUTER APPARATUS - A computer apparatus includes a main memory, a first memory diagnosis unit that determines a faulty area in the main memory by executing a first memory diagnostic program, and a storage unit that stores a relocatable second memory diagnostic program. Moreover, the computer apparatus includes a second memory diagnosis unit, that loads the second memory diagnostic program into areas of the main memory other than the faulty area determined by the first memory diagnosis unit.04-08-2010
20100005350TEST MODE CONTROL CIRCUIT AND METHOD FOR USING THE SAME IN SEMICONDUCTOR MEMORY DEVICE - A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.01-07-2010
20090327822TEST APPARATUS AND TEST METHOD - Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information. The test apparatus detects whether there is a defect corresponding to each of a plurality of fail conditions, outputs the detection result as a fail signal, and updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to the allocated fail conditions.12-31-2009
20120204070SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.08-09-2012
20120204069Integrated circuit and method for testing memory on the integrated circuit - An integrated circuit comprises a plurality of memory units and at least one memory test module, each memory test module having at least one associated memory unit from the plurality of memory units. Each memory test module comprises a set of test registers for each associated memory unit, and a test engine configured, for each associated memory unit, to perform a test operation on that associated memory unit dependent on the status of the set of registers provided for that associated memory unit. A transaction interface of the memory test module receives a transaction specifying a register access operation, the transaction providing a first address portion having encodings allowing individual memory units to be identified and groups of memory units to be identified, and a second address portion identifying one of the test registers within the set to be an accessed register for the register access operation. Decode circuitry within each memory test module is then responsive to the transaction to selectively perform the register access operation if it is determined that the memory test module includes a set of test registers associated with a memory unit identified either individually or as part of a group by the transaction. Such an approach provides a simple programmer's view of the memory test system allowing any transaction to be targeted at an individual memory unit or at arbitrary combinations of memory units as defined by the memory groups.08-09-2012
20110161754REVISION SYNCHRONIZATION OF A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a write request message from a dispersed storage (DS) processing module, wherein the write request message includes a slice name, a DS processing module most-recent slice revision, a new slice revision, and an encoded directory slice of directory information regarding storage of data. The method continues with the processing module obtaining, from local memory, a DS unit most-recent slice revision based on the slice name. The method continues with the processing module storing the new slice revision as the DS unit most-recent slice revision and storing the encoded directory slice when the DS unit most-recent slice revision compares favorably to the DS processing module most-recent slice revision.06-30-2011
20110055645SEMICONDUCTOR TEST METHOD, SEMICONDUCTOR TEST APPARATUS, AND COMPUTER READABLE MEDIUM - A semiconductor test apparatus includes an inputting module, a monitor, a converter, a storage, and a tester. The inputting module inputs addresses for first test, in which the addresses of a plurality of semiconductor memories are arrayed in an arbitrary order. The monitor monitors test time of the first test on each semiconductor memory. The converter sorts the addresses of the semiconductor memories based on the test time in order to convert the address for the first test to addresses for a second test. The storage stores the addresses for the second test. The tester tests each semiconductor device based on the addresses for the second test stored in the storage.03-03-2011
20110055644CENTRALIZED MBIST FAILURE INFORMATION - Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.03-03-2011
20080209284Input/output compression and pin reduction in an integrated circuit - An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.08-28-2008
20100287426MEMORY CHECKING SYSTEM AND METHOD - A memory checking system according to the present invention includes a memory that stores a data to be checked, a check circuit that checks the memory by using the data to be checked and a reference check code of the data to be checked, and a transfer circuit that transfers the data to be checked from the memory to the check circuit based on a transfer setting information of the data to be checked. The transfer setting information is registered in advance in the memory.11-11-2010
20100287424Method of writing an operating systems (OS) image to a semiconductor device and the semiconductor device - Example embodiments are directed to a method of writing an Operating System (OS) image to a semiconductor device having a data storage device, an Application Specific Integrated Circuit (ASIC), and a non-volatile memory. The method includes initializing a DRAM interface of the ASIC using a boot loader, receiving the OS image input from a data writer to the semiconductor device through the DRAM interface; and writing the OS image into the non-volatile memory of the semiconductor device using a Flash Translation Layer (FTL) code.11-11-2010
20100287425METHOD FOR TESTING A MEMORY DEVICE, AS WELL AS A CONTROL DEVICE HAVING MEANS FOR TESTING A MEMORY - A method for testing a memory and a control device having means for a memory test. A destination address of the memory is selected in the process, dependent addresses of the memory are determined from the destination address, and user data at the destination address and the dependent addresses are backed up. Furthermore, the destination address and the dependent addresses are described by test patterns, via which a signature is formed. The backed-up user data of the destination address and the dependent addresses are then restored. Finally, the determined signature is compared with the known setpoint value. In the event of a deviation between the signature and the setpoint value, suitable protective mechanisms are initiated.11-11-2010
20100180167ELECTRONIC CONTROL APPARATUS - An electronic control apparatus comprises a nonvolatile memory, operating means, determining means and retrying means. The nonvolatile memory stores predetermined data and has a memory region which is divided into a plurality of sub-regions. The operating means executes a check operation for each of the sub-regions in order to check whether the data stored in the nonvolatile memory are normal or not. The determining means determines whether the check operation has detected any data errors. The retrying means allows the operating means to retry the check operation for a predetermined number of times for the sub-regions that have been determined to be in data error by the determining means.07-15-2010
20110087934TEST APPARATUS AND TEST METHOD - A test apparatus testing a device under test includes a main pattern generating section that generates a main pattern, a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles, and a plurality of delay selecting sections each of which selects one of a main pattern that is from the main pattern generating section and a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, to supply the selected one to the corresponding sub-pattern generating section.04-14-2011
20110179321INFORMATION STORAGE DEVICE AND TEST METHOD THEREFOR - A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.07-21-2011
20110185239SEMICONDUCTOR TESTING APPARATUS AND METHOD - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.07-28-2011
20090300441ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.12-03-2009
20090300443Test apparatus, test method, and integrated circuit - A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.12-03-2009
20090300442Field mounting-type test apparatus and method for testing memory component or module in actual PC environment - Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data.12-03-2009
20110264969SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.10-27-2011
20100023818MULTIPLE ACCESS TEST ARCHITECTURE FOR MEMORY STORAGE DEVICES - A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral. Thirdly, a second processing unit which on one side is connected to the central processing system and on the other side is connected to the memory storage device via the multiplexer thus providing the second processing unit direct access to the memory storage device. And finally, the multiplexer that can connect either the electronic memory bridge or the second processing system to the memory storage device.01-28-2010
20100023817TEST SYSTEM AND METHOD - A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.01-28-2010
20080201620METHOD AND SYSTEM FOR UNCORRECTABLE ERROR DETECTION - A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.08-21-2008
20110307747MEMORY TESTING SYSTEM - An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.12-15-2011
20120047409SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS - Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks from one or more dies of a NVM. The subset of memory locations may be selected based on at least one reliability measurement of the subset of memory locations. In some embodiments, in response to detecting one or more access failures in a portion of the dynamic super block, the NVM interface can retire at least a portion of the dynamic super block. In some embodiments, the NVM interface can reconstruct a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block.02-23-2012
20120047410STORAGE DEVICE, CIRCUIT BOARD, LIQUID RESERVOIR AND SYSTEM - A storage device according to some aspects of the invention includes a communication unit configured to perform processing for communication with a host apparatus; a storage unit configured to have a first memory area and a second memory area that store therein received data from the host apparatus, and memory area selection information; a memory control unit configured to select one of the first memory area and the second memory area as a memory area for reading, select the other one thereof as a memory area for writing, and perform control of reading and writing; and an increment determination unit configured to compare a value of data having been read out from the memory area for reading by the memory control unit and a value of the received data to determine a magnitude relation therebetween.02-23-2012
20120047408SYSTEMS AND METHODS FOR MEMORY MANAGEMENT - Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a quality metric. In another aspect, the systems and methods described herein relate to improving communication quality in response to available memory capacity.02-23-2012
20110167307SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME - A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.07-07-2011
20110167306SEMICONDUCTOR TEST APPARATUS - A semiconductor test apparatus sorts addresses corresponding to memory cells in memory provided in a device under test, as well as failure data obtained as a result of testing the memory cells, and stores the sorted addresses and failure data in acquisition memory using burst access. The semiconductor test apparatus is provided with: an address generator configured to generate a burst target signal, which indicates that the addresses and failure data are target data for burst access; and a sort circuit configured to sort the addresses and failure data in order of continuous addresses suitable for burst access, on the basis of the burst target signal.07-07-2011
20120210179MEMORY INTERFACE WITH SELECTABLE EVALUATION MODES - A memory interface enables AC characterization under test conditions without requiring the use of automated test equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).08-16-2012
20120072790On-Chip Memory Testing - An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.03-22-2012
20120072792MEMORY TESTER AND COMPILER WHICH MATCHES A TEST PROGRAM - According to one embodiment, a memory tester is provided. The memory tester has first and second operation registers, a first selector, and first and second burst address generating circuits. The first operation register stores a first operation variable. The second operation register stores a second operation variable. The first selector outputs the first and second operation variables stored in the first and second operation registers selectively, as a burst address operation variable, based on a selection signal. The first and second burst address generating circuits are capable of generating first and second burst address signals based on the first and second operation variables outputted from the first selector, respectively.03-22-2012
20120072791Debugger Based Memory Dump Using Built in Self Test - A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.03-22-2012
20120072789MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY CONFIGURED TO FACILITATE PRODUCTION OF PRE-STRESSED INTEGRATED CIRCUITS AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.03-22-2012
20130173973DEVICE - A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.07-04-2013
20120131396DEVICE AND METHOD FOR REPAIR ANALYSIS - A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.05-24-2012
20120131397SEMICONDUCTOR DEVICE HAVING TEST MODE AND METHOD OF CONTROLLING THE SAME - When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.05-24-2012
20120216085DEVICES AND METHOD FOR WEAR ESTIMATION BASED MEMORY MANAGEMENT - A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.08-23-2012
20100205490INPUT/OUTPUT COMPRESSION AND PIN REDUCTION IN AN INTEGRATED CIRCUIT - An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.08-12-2010
20120137185METHOD AND APPARATUS FOR PERFORMING A MEMORY BUILT-IN SELF-TEST ON A PLURALITY OF MEMORY ELEMENT ARRAYS - A method and apparatus are described for performing a memory built-in self-test (MBIST) on a plurality of memory element arrays. Control packets are output over a first ring bus to respective ones of the arrays. Each of the arrays receives its respective control packet via the first ring bus, and reads commands residing in a plurality of fields within the respective control packet. Each of the arrays performs at least one self-test based on the commands, and outputs a respective result packet over a second ring bus. Each result packet indicates the results of the self-test performed on the array. Each control packet is transmitted in its own individual time slot to a respective one of the arrays.05-31-2012
20120317449DEVICE AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine.12-13-2012
20080215937REMOTE BIST FOR HIGH SPEED TEST AND REDUNDANCY CALCULATION - Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.09-04-2008
20120179942MEMORY SYSTEM - To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.07-12-2012
20120254679Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.10-04-2012
20120254678METHOD AND SYSTEM FOR DETERMINING SUPPORT FOR A MEMORY CARD - Embodiments related to methods and systems for determining support for a memory card, where the memory card is accessible to a card reader and the card reader is in communication with an accessing device. One embodiment comprises transmitting a first test command to the memory card, receiving a response to the first test command, and determining that the response to the first test command indicates that a card type is not supported by a plurality of card drivers. In response to said determining, at least one additional test command specific to a card type supported by a selected card driver is automatically transmitted, and if the response is successful, the selected card driver, which was previously determined not to support the card type of the memory card, is indicated to support the card type of the memory card.10-04-2012
20120226951TEST APPARATUS - Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.09-06-2012
20110004795METHOD FOR ENHANCING VERIFICATION EFFICIENCY REGARDING AN ERROR HANDLING MECHANISM OF A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate.01-06-2011
20110004793COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.01-06-2011
20100100779Data processing apparatus - A data processing apparatus includes a memory, an error detection circuit, a timing adjustment circuit and a terminal. The error detection circuit detects an error based on an output of the memory to output an error detection signal. The timing adjustment circuit enlarges a pulse width of a pulse signal which is generated at first after a start of a predetermined operation among pulse signals included in the error detection signal. The terminal outputs an output of the timing adjustment circuit when a test for the memory is performed. It is possible to report an occurrence of an error reliably without increasing the number of output terminals, test patterns or test time.04-22-2010
20110131457SEMICONDUCTOR MEMORY TESTING DEVICE AND METHOD OF TESTING SEMICONDUCTOR USING THE SAME - The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.06-02-2011
20120266033PROVIDING TEST COVERAGE OF INTEGRATED ECC LOGIC EN EMBEDDED MEMORY - A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.10-18-2012
20080288835Test method, integrated circuit and test system - The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.11-20-2008
20110047422NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION - The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations.02-24-2011
20110047421NAND FLASH-BASED STORAGE DEVICE WITH BUILT-IN TEST-AHEAD FOR FAILURE ANTICIPATION - A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.02-24-2011
20120272107METHOD AND APPARATUS FOR PROVIDING PRELOADED NON-VOLATILE MEMORY CONTENT - An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.10-25-2012
20120272108MEMORY AND TEST METHOD FOR MEMORY - A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.10-25-2012
20120324301METHOD FOR CHECKING THE FUNCTIONAL ABILITY OF A MEMORY ELEMENT - A method for checking the functional ability of a memory element having a stack memory, wherein the stack memory occupies a defined region within the memory element. A stack memory pointer is defined, which displays, in the form of an address, a stack memory position, from which data are currently being removed or to which data are currently being written. In the memory element, a section of defined length arranged outside a memory region to be checked is delimited and used as an auxiliary memory; the current address of the stack memory pointer is stored before the start of a test program for checking the memory element and the stack memory pointer is then assigned an address associated with the auxiliary memory, so that during the test program the auxiliary memory is used as working memory; and after terminating the test program the stack memory pointer is reassigned the address of that position, which it displayed before the start of the test program.12-20-2012
20110060952Semiconductor integrated circuit - The semiconductor integrated circuit including a memory macro includes a memory cell unit, input data holding units, and output data holding units. The input data holding units hold one of values of input data signals and a scan value depending on a scan control signal in accordance with an operating clock. The output data holding units hold one of values held by the input data holding units and data values stored by the memory cell unit depending on a test control signal in accordance with a phase different from a phase to operate the input data holding units. Further, the input data holding units and the output data holding units are alternately connected in series, and one input data holding unit is arranged at the top. A value held by one output data holding unit is transmitted to another input data holding unit arranged at a subsequent stage of the one output data holding units as the scan value.03-10-2011
20110271156APPARATUS AND METHOD FOR TESTING SHADOW LOGIC - A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.11-03-2011
20110276846UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST - An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.11-10-2011
20110276845METHODS, APPARATUS AND ARTICLES OF MANUFACTURE TO DIAGNOSE TEMPERATURE-INDUCED MEMORY ERRORS - Example methods, apparatus and articles of manufacture to diagnose temperature-induced memory errors are disclosed. A disclosed example method to diagnose a temperature-induced memory error includes detecting a memory error associated with a memory device, and writing a highest measured temperature of the memory device in the memory device when the memory error is detected, the highest temperature measured temporally near the detected memory error.11-10-2011
20110276844METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is designated read-only. A current checksum is calculated based at least in part on data within the memory block. When the first memory block is designated read-only, and the prior checksum represents expected data within the first memory block, it is determined whether the current checksum is equal to the prior checksum. When the current checksum is not equal to the prior checksum, a verification failure for the first memory block is indicated via a notification interface. A system for verifying memory device integrity is also disclosed.11-10-2011
20110320891Driving Method of Electronic Device - A method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power sequentially supplied from a contactless power feeding device, and a plurality of loads to which power is sequentially supplied from the power supply circuit. Further, a method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power supplied from a contactless power feeding device, and one or more loads to which the power supply circuit repeatedly supplies power. The power supply potential V12-29-2011
20120102374STORAGE DEVICE TESTING - A storage device testing system (04-26-2012
20120151287Memory-Module Extender Card for Visually Decoding Addresses from Diagnostic Programs and Ignoring Operating System Accesses - A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit.06-14-2012
20130019130TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITYAANM HAKHUMYAN; AramAACI YerevanAACO AMAAGP HAKHUMYAN; Aram Yerevan AMAANM Harutyunyan; GurgenAACI AbovyanAACO AMAAGP Harutyunyan; Gurgen Abovyan AMAANM Shoukourian; SamvelAACI YerevanAACO AMAAGP Shoukourian; Samvel Yerevan AMAANM Vardanian; ValeryAACI YerevanAACO AMAAGP Vardanian; Valery Yerevan AMAANM Zorian; YervantAACI Santa ClaraAAST CAAACO USAAGP Zorian; Yervant Santa Clara CA US - Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.01-17-2013
20110161753SEMICONDUCTOR MEMORY APPARATUS INCLUDING DATA COMPRESSION TEST CIRCUIT - A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode.06-30-2011
20130173971BOUNDARY SCAN CHAIN FOR STACKED MEMORY - A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.07-04-2013
20080229162TEST APPARATUS AND TEST METHOD - Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded.09-18-2008
20080222464Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test - A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.09-11-2008
20130173972SYSTEM AND METHOD FOR SOLID STATE DISK FLASH PLANE FAILURE DETECTION - A system and method for early detection and reporting of an impending NAND Flash device plane failure. Each time that a data unit is retrieved from a NAND Flash array the number of bits in error and the memory location associated with the errors is observed. if the number of bits in error or the error rate for a memory location exceeds a threshold of the number of bits in error per data, retrieval, or number of bits in error per data unit per unit time, a NAND Flash plane failure Patrol Read operation is performed at the memory location, regardless of where in the cycle the Patrol Read function is in a scrub of the overall NAND Flash device. The NAND Flash plane failure Patrol Read is repeated for a number of cycles on the NAND Flash plane in question.07-04-2013
20130124932Solid-State Disk Manufacturing Self Test - A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an ‘input’ SMART log of each SSD, and each SSD writes results to a respective included ‘output’ SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.05-16-2013
20130124931TRANSMISSION ERROR DETECTOR FOR FLASH MEMORY CONTROLLER - In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.05-16-2013
20110219276APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS, AND A NON-TRANSITORY COMPUTER-READABLE MEDIUM HAVING A SEMICONDUCTOR INTEGRATED CIRCUIT TESTING PROGRAM - An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test pattern data into a storage area of the semiconductor integrated circuit.09-08-2011
20080201622Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof - Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.08-21-2008
20110239062SEMICONDUCTOR DEVICE - A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.09-29-2011
20130151913Expedited Memory Drive Self Test - Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.06-13-2013
20130205177MEMORY CARD CLEANER AND METHOD OF UTILIZATION - A system and method for verifying memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A visual indicator is displayed on the computing device indicating whether the card is functioning correctly and whether the memory card passed or failed the scanning. An identifier associated with the memory card is stored in response to determining the memory card passed the scanning. A first volume name of the memory card is rewritten to the second volume name in response to storing the identifier.08-08-2013
20130205178SYSTEM AND METHOD FOR AUDITING MEMORY CARDS - A system and method for auditing memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A determination is made whether content in the memory card is acceptable or unacceptable. A first volume name of the memory card is rewritten to the second volume name in response to determining the content in the memory card is acceptable.08-08-2013
20120284576HARDWARE STIMULUS ENGINE FOR MEMORY RECEIVE AND TRANSMIT SIGNALS - Techniques and structures are disclosed in which memory training for DDR or other memory can be performed more rapidly. A memory controller is configured so that one or more memory parameters (e.g., timing delay) can be determined for one or more hardware elements such as delay locked loops (DLLs). Training may be performed without intermediation by (or reporting of results to) a system BIOS. Thus, training may be performed fully in hardware. Voltage training techniques are also disclosed.11-08-2012
20130159797APPARATUS AND METHODS FOR INDICATING THE HEALTH OF REMOVABLE STORAGE DEVICES - Disclosed are apparatus and techniques for indicating health of a memory system having a controller and nonvolatile memory array. In one embodiment, the invention pertains to a method for indicating health of a removable memory system that is removably coupled with a host device. After the memory system is coupled with a host device, a first health status is output via an external electrical or mechanical interface of the memory system. One or more health metrics of the memory system are monitored. After a first predefined limit is reached with respect to the one or more health metrics, a second health status is output via the external electrical or mechanical interface of the memory system. The first health status differs from the second health status.06-20-2013
20130103992Burn-In Method for Embedded Multi Media Card, and Test Board Using the Same, and Embedded Multi Media Card Tested by the Same - A burn-in method for an embedded Multi Media Card (eMMC), and a test board using the same, and an eMMC tested by the same. The disclosed burn-in method comprises the steps as below: writing a test pattern to a flash memory of the eMMC; electrically connecting a command line of the eMMC to ground to operate the eMMC in a boot state; performing a burn-in procedure on the flash memory when the eMMC is in the boot state and the test pattern is recognized as being contained in the flash memory; and collecting a test report during the burn-in procedure, wherein the test report is stored in the flash memory.04-25-2013
20130205179INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.08-08-2013
20120072788INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.03-22-2012
20130212444METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS - Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.08-15-2013

Patent applications in class Memory testing

Patent applications in all subclasses Memory testing