| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714712000 | Transmission facility testing | 32 |
| 20130036336 | TRANSMITTING DEVICE, TRANSCEIVER SYSTEM, AND CONTROL METHOD - An I/O controller | 02-07-2013 |
| 20130091393 | TRANSMISSION TEST DEVICE AND TRANSMISSION TEST METHOD - A transmission test device that performs a transmission test in a transmission path includes a determining unit and a killer pattern transfer unit. The determining unit acquires an abnormality incidence rate representing a rate of abnormality having occurred in test data in a transmission path, and determines whether or not the abnormality incidence rate is lower than a predetermined reference value. The killer pattern transfer unit changes the test data and transmits changed test data when the determining unit determines that the abnormality incidence rate is lower than the predetermined reference value. | 04-11-2013 |
| 20080250278 | Browser on test equipment - A portable telecommunication test set, such as a telephone line butt set, with a web browser incorporated therein. A standard HTML (Hyper Text Mark-up Language) or WAP (Wireless Application Protocol) browser may be incorporated within the portable test set, allowing a network technician to access the Internet as well as other remotely-located sources of information to retrieve data and other useful technical information while in the field for communication network or telephone line maintenance, troubleshooting or repair. The test set may contain memory to locally store certain technical information, e.g., telephone line-specific data or circuit information, that may be retrieved and “read” by the built-in browser module when prompted by the network technician. The web browser may display the content of the requested information on a display provided on the test set. Line-specific (as well as manufacturer-specific) test information need not be in a manufacturer-dictated proprietary format, but, instead, may be in a generally available text format, e.g., the HTML format or the WML (Wireless Mark-up Language) format. Testing-related data may thus be supplied (as hardware or software plug-in modules) by a vendor other than the manufacturer of the test set. | 10-09-2008 |
| 20100262874 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock. | 10-14-2010 |
| 20110246840 | TRANSMISSION OF ACKNOWLEDGEMENT AND NEGATIVE ACKNOWLEDGEMENT IN A WIRELESS COMMUNICATION SYSTEM - A communication device configured for transmission of Acknowledgement and Negative Acknowledgement (ACK/NACK) is described. The communication device includes a processor and instructions stored in memory. The communication device determines one or more thresholds based on a size of one or more code words and generates a compressed ACK/NACK sequence. The compressed ACK/NACK sequence identifies one or more correctly received code words and one or more incorrectly received code words if the number of incorrectly received code words is less than the threshold. If the number of incorrectly received code words is greater than the threshold, the compressed ACK/NACK sequence indicates that all of the one or more code words were incorrectly received. | 10-06-2011 |
| 20100192028 | DIAGNOSTICS OF CABLE AND LINK PERFORMANCE FOR A HIGH-SPEED COMMUNICATION SYSTEM - A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system. | 07-29-2010 |
| 20090313510 | PORT SELECTOR, DEVICE TESTING SYSTEM AND METHOD USING THE SAME - A port selector, a device testing system and a method using the same. The port selector includes: a plurality of terminal ports to which a device is respectively coupled; an integration port which is connected to the plurality of terminal ports through a signal transmitting line; a plurality of terminal switches which are disposed to correspond to each terminal port, and open and close the signal transmitting line; and a control unit which independently controls each terminal switch. Thus, the present general inventive concept provides a port selector, a device testing system and a method using the same including a plurality of terminal ports to which devices are respectively coupled, and independently controlling each terminal port, thereby selecting a port. | 12-17-2009 |
| 20110179320 | METHOD FOR RECEIVING DATA STREAMS AND CORRESPONDING METHOD FOR TRANSMISSION - The present invention relates to the domain of reception and transmission of data streams, for example audio and video. More specifically, the invention relates to the optional use of an error correction stream associated with a data stream. | 07-21-2011 |
| 20080320345 | SYSTEM AND METHOD FOR TESTING WIRELESS DEVICES - A system for testing a communication device includes a testing module, a measurement module, and a control module. The testing module transmits one or more first test signals based on a first test sequence. The measurement module acquires test data by receiving one or more second test signals that are based on the one or more first test signals. The control module initiates the first test sequence in response to receiving a start test signal from an analysis system. The control module transfers the test data to the analysis system in response to a transfer data request. The control module initiates a second test sequence while the analysis system is analyzing the test data. The testing module generates and transmits one or more third test signals based on the second sequence when the second test sequence has been initiated. | 12-25-2008 |
| 20080222463 | APPARATUS, METHOD AND PRODUCT FOR TESTING COMMUNICATIONS COMPONENTS - An apparatus, method and product for independently testing communications components are disclosed. A testing apparatus is provided that has a test control component which includes an input configured to receive a test script, an upper interface coupling and a lower upper interface coupling. In operation, a protocol stack component to be tested is coupled to the test control component via upper and lower interfaces. | 09-11-2008 |
| 20120324300 | COMPUTER SYSTEM, ACTIVE SYSTEM COMPUTER, AND STANDBY SYSTEM COMPUTER - Upon a receipt of an advance notice, an active system computer on which asynchronous replication is performed with a standby system computer stops a business application and transmits to the standby system computer transmission start information indicating start of data synchronization, data accumulated in a transmission queue | 12-20-2012 |
| 20120290888 | Enhancing a receiver for improved impairment/fault detection when handling the reception of intermittent signals - One embodiment of a Test Signal generated by Test Signal Synthesis | 11-15-2012 |
| 714714000 | By tone signal | 2 |
| 20100037107 | Method for testing a communication connection - The invention relates to a method for testing a communication connection ( | 02-11-2010 |
| 20090113257 | DEVICE AND METHOD FOR TESTING SAS CHANNELS - A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface. | 04-30-2009 |
| 714715000 | Test pattern with comparison | 15 |
| 20090235130 | TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM - A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface. | 09-17-2009 |
| 20090249135 | TESTING APPARATUS AND TESTING METHOD - Provided is test apparatus with higher testing efficiency, including: plurality of pattern generating sections generating test pattern to supply to devices under test; group control section controlling group of pattern generating sections out of the pattern generating sections, and generating control signal upon receiving signal output from any pattern generating section controlled; range information storage section storing range information indicating range of pattern generating sections, out of the pattern generating sections, that serve to test one independent device under test; and comprehensive control section receiving the control signal from the group control section, identifying any pattern generating section that supplies the test pattern to the same device under test as that to which the pattern generating section having output the signal supplies the test pattern based on the range information, and in response to the control signal, controlling any other group control section that controls the identified pattern generating section. | 10-01-2009 |
| 20090094492 | CHANNEL IMPAIRMENT EMULATOR SYSTEMS AND METHODS - Systems and methods are disclosed herein to provide improved communication system test techniques. For example, in accordance with an embodiment of the present invention, a wireless device test system is disclosed having a channel emulator for multipath and/or MIMO applications to allow the testing of wireless devices (e.g., WLAN devices) in a cabled environment. | 04-09-2009 |
| 20090265589 | DATA CHANNEL TEST APPARATUS AND METHOD THEREOF - A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port. | 10-22-2009 |
| 20090138768 | DATA CHANNEL TEST APPARATUS AND METHOD THEREOF - A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port. | 05-28-2009 |
| 20110154137 | DATA CHANNEL TEST APPARATUS AND METHOD THEREOF - A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port. | 06-23-2011 |
| 20090292961 | Integrated circuit communication self-testing - An integrated circuit | 11-26-2009 |
| 20100031098 | METHOD OF REAL TIME OPTIMIZING MULTIMEDIA PACKET TRANSMISSION RATE - A method and apparatus of optimizing transmission (both real time and continuous) of a number of multimedia data packets between a multimedia source device and a multimedia display device is disclosed. In the described embodiment, the multimedia source device and the display device are coupled by way of a unidirectional main link arranged to carry the multimedia data packets from the multimedia source device and the multimedia display device and a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia display device. The method can be carried out by following at least the following operations. Providing a test pattern by the multimedia source device on the main link, determining a transmission quality factor of the main link based upon the test pattern, and optimizing the transmission of the multimedia data packets based upon the transmission quality factor. | 02-04-2010 |
| 20100251040 | METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM - A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously. | 09-30-2010 |
| 714716000 | Loop-back | 6 |
| 20100077267 | Memory System with Point-to-Point Request Interconnect - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 03-25-2010 |
| 20090113258 | Method and system for testing devices using loop-back pseudo random datat - There is provided a method of testing a first device using a tester. The method comprises receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further comprise generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data. | 04-30-2009 |
| 20100138705 | STANDALONE DATA STORAGE DEVICE ELECTROMAGNETIC INTERFERENCE TEST SETUP AND PROCEDURE - A system for operating a data storage device having a plurality of sectors and at least one port, each port having a transmitter and a receiver, is disclosed. In one embodiment the system includes coupling at least one of the transmitters to at least one of the receivers, providing power to the data storage device, detecting that the transmitter is coupled to the receiver, and executing code for exercising the data storage device. | 06-03-2010 |
| 20090265590 | Method And System For Testing The Compliance Of PCIE Expansion Systems - The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE expansion system comprises delivering the data signals from the data lanes to a compliance board that is configured to loop back at least a first portion of the data signals and transmit a complementary second portion of the data signals to a testing device, and testing a compliance of the second portion of the data signals with the PCIE requirements. The first portion of the data signals is then tested through a second compliance board that is configured to loop back the second portion of the data signals and transmit the first portion of the data signals to the testing device. | 10-22-2009 |
| 20090292962 | Integrated circuit with inter-symbol interference self-testing - An integrated circuit | 11-26-2009 |
| 20120072787 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 03-22-2012 |
| 714717000 | Loop or ring configuration | 3 |
| 20090119554 | BACKPLANE EMULATION TECHNIQUE FOR AUTOMATED TESTING - The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable. | 05-07-2009 |
| 20120159271 | MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNS - A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output. | 06-21-2012 |
| 20110047420 | METHOD AND SYSTEM FOR TESTING CHIPS - A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip. | 02-24-2011 |
