| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714708000 | Shutdown or establishing system parameter (e.g., transmission rate) | 25 |
| 20130047044 | OPTIMAL PROGRAMMING LEVELS FOR LDPC - The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided. | 02-21-2013 |
| 20130047045 | ERROR INDICATOR FROM ECC DECODER - The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided. | 02-21-2013 |
| 20130061099 | EFFICIENT ERROR HANDLING ON A LINK USING ARQ AND MULTIPLE NACKS ASSOCIATED WITH MULTIPLE ERROR THRESHOLDS - The present invention describes how to handle errors occurring during communication in a frame-based communication system that uses a communication protocol having a first error handling mechanism responsive to receipt of an incorrect protocol symbol. The invention provides a method and apparatus that allow several errors to occur without the communication system responding by initiating the first error handling mechanisms. Under circumstances where errors occur, the method and apparatus may improve throughput. | 03-07-2013 |
| 20090271668 | Bus Failure Management Method and System - A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes. | 10-29-2009 |
| 20130124930 | CONTROLLING IPSEC OFFLOAD ENABLEMENT DURING HARDWARE FAILURES - Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold. | 05-16-2013 |
| 20120239991 | APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit. | 09-20-2012 |
| 20110219274 | MEMORY SYSTEM AND METHOD FOR PREVENTING SYSTEM HANG - A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented. | 09-08-2011 |
| 20080215935 | Processing Configuration Data Frames - In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames. | 09-04-2008 |
| 20130024736 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 01-24-2013 |
| 20100083061 | Method to Manage Path Failure Thresholds - A failure threshold host command that provides a host with the capability to tune a storage controller path failure threshold based on the host application performance requirements. The failure threshold host command comprises path failure threshold rules that the storage controller uses to determine when a CHPid has reached a failed state condition. | 04-01-2010 |
| 20090282300 | Partition Transparent Memory Error Handling in a Logically Partitioned Computer System With Mirrored Memory - A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error. | 11-12-2009 |
| 20090024883 | INTER-ASIC DATA TRANSPORT USING LINK CONTROL BLOCK MANAGER - An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed. | 01-22-2009 |
| 20120198290 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory cells are programmed to produce a verification result, determining whether all of the plurality of the memory cells are programmed in response to the verification result to produce a first determination result and determining whether at least a first number of memory cells are programmed among the plurality of the memory cells in response to the first determination result to produce a second determination result. | 08-02-2012 |
| 20090144591 | DETERMINING BIT ERROR RATE USING SINGLE DATA BURST - A communication system comprises a transceiver capable of receiving a data burst as part of a paging block. The system also comprises processing logic capable of comparing at least part of the data burst to a plurality of permutations of the data burst to locate a matching permutation. The processing logic determines a bit error rate (BER) in accordance with a difference between the data burst and the matching permutation. The processing logic uses the BER to operate the communication system. | 06-04-2009 |
| 20090063911 | DIGITAL BROADCAST RECEIVER - In digital broadcast receiver ( | 03-05-2009 |
| 20090031178 | Method and System for Adaptive Interleaving - A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system. | 01-29-2009 |
| 20100332923 | SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY - Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold. | 12-30-2010 |
| 20110179318 | APPARATUS, A METHOD AND A PROGRAM THEREOF - An apparatus and method for efficiently processing memory faults. A faulty memory is exchanged with a spare memory when the total number of faults in the memories is over a threshold. After the switching, when the number of faults in a single cache line is over a threshold, a memory page corresponding to the single cache line is blocked. | 07-21-2011 |
| 20120159270 | MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed. | 06-21-2012 |
| 20120216084 | SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE - A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link. | 08-23-2012 |
| 20120272106 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-25-2012 |
| 20120272105 | HOME NETWORK ENCRYPTION TECHNIQUES - A premises based multimedia communication system includes a source device that produces multimedia content, a rendering device that presents the multimedia content, and a premises communication network coupling the source device to the rendering device. The system determines a bit error rate of the premises communication network, transfers the multimedia content from the source device to the rendering device, and when the bit error rate exceeds a bit error rate threshold, the system at least partially disables link layer encryption of video frames of the multimedia content transfer. With the link layer operations at least partially disabled, the system can enable, at least partially, content layer encryption operations for the transfer of the multimedia content from the source device to the rendering device. | 10-25-2012 |
| 20120284575 | ADAPTIVE MEMORY SCRUB RATE - In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors. | 11-08-2012 |
| 20120331357 | METHOD AND SYSTEM OF COMPRESSING RAW FABRICATION DATA FOR FAULT DETERMINATION - The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data. | 12-27-2012 |
| 20110161748 | Systems, methods, and apparatuses for hybrid memory - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 06-30-2011 |
