Class / Patent application number | Description | Number of patent applications / Date published |
714703000 | Testing of error-check system | 14 |
20080235539 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction stream, a transfer section that reads the test instruction stream stored on the main memory and writes the read stream into the sequence cache memory in accordance with a described sequence, a pattern generating section that sequentially reads and executes instructions from the test instruction stream cached on the sequence cache memory and outputs a test pattern corresponding to the executed instruction, and a test signal output section that generates a test signal according to the test pattern and supplies the generated signal to the device under test, in which the transfer section overwrites the instruction read from the main memory on a space area on the sequence cache memory or an area on which executed instructions are stored and prohibits overwriting the read instruction on an area on which instructions in a predetermined range is stored, the instructions being located in the predetermined range forward from a final instruction among the executed instructions according to the described sequence. | 09-25-2008 |
20090083590 | System and method for determining the fault-tolerance of an erasure code - A method for determining a fault tolerance of an erasure code comprises deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns with one another to produce child erasure patterns of the erasure code. The method further comprises combining the base erasure patterns and the child erasure patterns to form a minimal erasures list (MEL) for the erasure code, whereby the MEL corresponds to the fault tolerance of the erasure code. Also provided are methods for communicating and storing data by using the fault tolerance of erasure codes. | 03-26-2009 |
20110087932 | Method and System for Detecting a Failure In an Error Correcting Unit - In order to detect a faulty error correcting unit ( | 04-14-2011 |
20110191643 | Detection And Diagnosis Of Scan Cell Internal Defects - A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models. | 08-04-2011 |
20130111280 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR ELECTRONIC MESSAGING | 05-02-2013 |
20130139008 | METHODS AND APPARATUS FOR ECC MEMORY ERROR INJECTION - An error injection module for injecting errors into an ECC memory selects a target address associated with the ECC memory, selects an error injection pattern, and sets a redirect address of the scrubber to the target address. During an injection mode of the scrubber, the error injection module injects the error injection pattern into the target address of the ECC memory with the scrubber. | 05-30-2013 |
20140115409 | SELF-TEST DESIGN FOR SERIALIZER / DESERIALIZER TESTING - Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate. | 04-24-2014 |
20140245086 | Test Signal Generator for Low-Density Parity-Check Decoder - A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used. | 08-28-2014 |
20140250340 | SELF MONITORING AND SELF REPAIRING ECC - Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test. | 09-04-2014 |
20140281762 | SYSTEM AND METHOD FOR RANDOM NOISE GENERATION - A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module. | 09-18-2014 |
20150074473 | PSEUDO-ERROR GENERATING DEVICE - A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predetermined path, configured to inject a pseudo-error to the predetermined path. The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data. | 03-12-2015 |
20150317194 | PERIODIC VALIDATION AND HEALTH REPORTS OF DISASTER RECOVERY PLAN - Techniques are described for validating a disaster recovery plan. In an embodiment, a request is received to perform a validation of a disaster recovery operation plan that includes a set of instructions for performing a disaster recovery operation with respect to a first site and a second site. In response to receiving the request to perform the validation of the disaster recovery operation plan, a set of one or more validation operations is performed with respect to the disaster recovery operation plan. Based on the set of one or more validation operations, a report is generated that identifies one or more issues that may prevent the disaster recovery operation plan from executing properly. | 11-05-2015 |
20150324260 | METHODS AND APPARATUS FOR REPLICATED DATA TEST FAILOVER - Systems and methods for facilitating test failover on a remote virtual machine without creating a full copy of the remote virtual machine. A snapshot is created of a remote virtual machine disk, the remote virtual machine disk protecting a source virtual machine disk. An instant, thin provisioned virtual machine is created from the snapshot, and the instant, thin provisioned virtual machine is powered on based on a received instruction to power on the instant, thin provisioned virtual machine thereby creating a running instance of a virtual machine, thereby facilitating test failover on the remote virtual machine without creating a full copy of the remote virtual machine. | 11-12-2015 |
20160103720 | DETECTING HIGH AVAILABILITY READINESS OF A DISTRIBUTED COMPUTING SYSTEM - Technology is disclosed for determining high availability readiness of a distributed computing system (“system”). A confidence measure (CM) can be computed for a particular controller in the system to determine whether a takeover by the particular controller from a first controller would be successful. The CM can be a percentage value. A CM of 0% indicates that a takeover would be a failure, which results in loss of access to data managed by the first controller. A CM of 100% indicates a successful takeover with no performance impact on the system. A CM between 0% and 100% indicates a successful takeover but with a performance impact. The CM can be computed based on events occurring in the system, e.g., veto and non-veto events. The CM is computed as a function of various weights and/or indices associated with the veto events and/or non-veto events. | 04-14-2016 |