| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714700000 | Skew detection correction | 29 |
| 20100115349 | MISALIGNMENT COMPENSATION FOR PROXIMITY COMMUNICATION - In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. | 05-06-2010 |
| 20090158100 | JITTER APPLYING CIRCUIT AND TEST APPARATUS - There is provided a jitter applying circuit that includes: a signal transmission path that transmits a signal from an input end to an output end thereof; a jitter control section that outputs, from an output terminal thereof, a jitter control voltage that is in accordance with jitter to be superposed to a signal propagating on the signal transmission path; a buffer circuit that is serially connected between the input end and the connection point on the signal transmission path; a serial resistance that is serially connected between the buffer circuit and the connection point, on the signal transmission path; and a variable capacitance diode that is provided between a connection point on the signal transmission path and the output terminal of the jitter control section, and whose capacitance changes in accordance with the jitter control voltage. | 06-18-2009 |
| 20120166894 | CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME - In a circuit, memory controller, memory system, and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences. | 06-28-2012 |
| 20130091392 | Apparatus and Method to Measure Timing Margin in Clock and Data Recovery System Utilizing a Jitter Stressor - A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails adding an amount of jitter within the CDR to change the receiver phase. The amount of jitter is incrementally increased until a threshold level of bit errors occur. Based on the amount of jitter needed to cause the threshold level of bit errors, timing margin can be calculated. | 04-11-2013 |
| 20090019323 | System and method for initializing a memory system, and memory device and processor-based system using same - Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames. | 01-15-2009 |
| 20110302464 | DIGITAL DATA TRANSMISSION SYSTEM USING TRANSMITTING UNIT AND RECEIVING UNIT AND TRANSMISSION METHOD - A digital data transmission system includes a transmission unit and a reception unit. The transmission unit includes: a transmission-side logic section configured to transmit digital data in parallel onto data lines; and a deskew data generating section configured to transmit deskew data onto a deskew signal line. The deskew data includes sample data and parity data for each of line components of the digital data. The reception unit includes: a skew adjusting section configured to perform deskew processing on the digital data recovered from the data transmitted on the data lines based on the deskew data recovered from the data transmitted on the deskew signal line; an error correcting section configured to perform error correction on the recovered digital data subjected to the deskew processing based on the parity data of the recovered deskew data; and a reception-side logic section configured to execute a predetermined process to the recovered digital data subjected to the error correction. | 12-08-2011 |
| 20110302465 | MISALIGNMENT COMPENSATION FOR PROXIMITY COMMUNICATION - In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. | 12-08-2011 |
| 20100023816 | METHOD FOR DETERMINING AN ASYMMETRICAL SIGNAL LAG OF A SIGNAL PATH INSIDE AN INTEGRATED CIRCUIT - A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first measuring operating mode using a controllable integrated multiplexer to measure an asymmetrical signal lag of a measuring path, which includes the integrated signal path and the integrated multiplexer, and a measuring signal being able to be decoupled in a second measuring operating mode using the controllable integrated multiplexer to measure the asymmetrical signal lag of the integrated multiplexer. | 01-28-2010 |
| 20090210756 | FRAME RESTORATION METHOD, FRAME RESTORATION CIRCUIT, AND STORAGE MEDIUM - A restoration frame identifier monitoring unit checks restoration frame identifiers within split frames and carries out processing to divide inputted split frames for input to a first split frame processing circuit or a second split frame processing circuit according to the value of the frame identifier and determines whether or not the split frames are inputted within a fixed monitoring time. The split frame accumulation buffer unit repeatedly accumulates inputted split frames until a split frame for a final frame is inputted. When the split frame for the final frame is inputted, this split frame and the accumulated split frames are combined so as to generate a single restored frame. The split frame accumulation buffer unit is then cleared when the split frames are not inputted within a fixed monitoring time. | 08-20-2009 |
| 20090024882 | METHOD FOR MONITORING AN INTERNAL CONTROL SIGNAL OF A MEMORY DEVICE AND APPARATUS THEREFOR - Disclosed is a method for monitoring an internal control signal of a memory device and an apparatus therefore. The method includes (a) generating a first signal having a first pulse width by a burst operation command, (b) receiving the first signal, and generating N−1 (where, N is a burst length) second signals having a second pulse width, (c) receiving the first signal and the second signals, and outputting a third signal by changing the first pulse width of the first signal and the second pulse width of the second signals in accordance with a variation of a frequency of a clock signal of the memory device, (d) outputting the third signal to an external pin of the memory device and monitoring the third signal, and (e) adjusting a pulse width of a signal that controls an operation of a data bus connecting a bit-line sense amplifier and a data sense amplifier using the third signal. | 01-22-2009 |
| 20090055694 | APPARATUS AND METHOD FOR MEASURING SKEW IN SERIAL DATA COMMUNICATION - An apparatus and method measures the skew between signals on data and clock channels using a bit pattern matching technique for any given protocol in Serial data communication. In one embodiment, the method of finding the pattern comprises of importing the waveform data from the oscilloscope and converting the waveform into bit patterns, finding the pattern index on the converted bit stream using a pattern based on the TMDS channel combination, and then measuring the skew. | 02-26-2009 |
| 20090259893 | 10GBase-T training algorithm - A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied. | 10-15-2009 |
| 20100192027 | COMPENSATION OF MISMATCH ERRORS IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A method for the compensation of frequency-response mismatch errors in M-channel time-interleaved ADCs. The compensation is done utilizing a technique that makes use of a number of fixed filters, that approximate differentiators of different orders, and a few variable multipliers that directly correspond to parameters in polynomial models of the M channel frequency responses. A compensated M-channel time-interleaved ADC is based on and can perform the method. | 07-29-2010 |
| 20090019324 | METHOD AND APPARATUS FOR ANALYZING SERIAL DATA STREAMS - An apparatus and method for processing a data signal is provided. An acquisition unit of a test instrument acquires a data signal for a predetermined time. The data signal is stored in a memory of the test instrument and a clock recovery unit recovers a clock signal from the stored data signal. The stored data signal is sliced by a processor into a plurality of data segments of a predetermined length in accordance with the recovered clock signal. | 01-15-2009 |
| 20100306603 | Segmented and Overlapped skew tracking method for serdes frame interface Level 5 - A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a reference data segment with a length of Umax over each of data channels to be subject to skew detection. The method includes: S1) performing the following on one frame of data transmitted over one data channel in a period of one frame: a) dividing the frame of data into a plurality of data blocks according to the maximum allowable skew detection range Rmax; b) dividing each of the data blocks into a plurality of segments each with the length of Umax; c) serially comparing each of the segments in the respective data blocks with the corresponding reference data segment, respectively, to derive skew detection results of all the segments in the respective data blocks; and d) for each of the data blocks, selecting the skew detection result of one of all the segments in the data block as a skew detection result of the data block; and S2) selecting a skew detection result with the maximum skew from among the skew detection results of all the data blocks as a skew detection result of the frame of data. | 12-02-2010 |
| 20100153792 | Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and memory test system and method using the same - In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences. | 06-17-2010 |
| 20100017662 | METHOD AND APPARATUS FOR CALIBRATING AND/OR DESKEWING COMMUNICATIONS CHANNELS - A series of pulses may be driven down each drive channel, which creates a series of composite pulses at the output of the buffer. Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels, and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels. | 01-21-2010 |
| 20100058124 | SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames. | 03-04-2010 |
| 20110258494 | Method for Correcting Prediction Errors of Signal Values with Time Variation Subjected to Interference by Various Uncontrollable Systematic Effects - A method for correcting the prediction of values of signal with time variation, in particular for navigation messages sent by the global satellite navigation systems, includes the following steps for the correction of the predictions of a parameter included in a received signal and varying in time: estimation of the prediction error based on a first batch of values estimated during a determined time period by comparing these values to the values previously predicted for the same determined time period, analysis of the predicted time-oriented series of prediction errors by a method for processing the signal and isolating the contributions of the systematic effects, and extrapolation of the behavior of the contributions of the systematic effects during the time period concerned and correction of the predictions using the duly extrapolated values. | 10-20-2011 |
| 20090240994 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA BITS - Provided are an apparatus and method for transmitting and receiving data bits. The apparatus includes a transmitter configured to generate a transmission signal corresponding to the data bits and having a periodic transition, a data line configured to transmit the generated transmission signal, and a receiver configured to generate a reception clock signal from the periodic transition of the transmission signal (“reception signal”) transmitted through the data line, sample the reception signal according to the generated reception clock signal to recover the data bits. Accordingly, it is possible to transmit clock information without a clock line separate from the data line. | 09-24-2009 |
| 20100318860 | INFORMATION PROCESSING APPARATUS, SYNCHRONIZATION CORRECTION METHOD AND COMPUTER PROGRAM - An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time. | 12-16-2010 |
| 20120023380 | ALGORITHMIC MATCHING OF A DESKEW CHANNEL - In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits. | 01-26-2012 |
| 20100205488 | FAST PHASE-FREQUENCY DETECTOR ARRANGEMENT - The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement. This provides the advantage that behavior of the charge pump circuit can alleviate extra ripple generated by the detector arrangement. | 08-12-2010 |
| 20110185238 | MICROCOMPUTER, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLIED EQUIPMENT - In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing control data that specifies an interval for suppressing the analog operation start of the one analog circuit in the analog operation cycle of the other analog circuit that has already started the analog operation. The control is conducted so that when the operation of one analog circuit starts, timing when the operation of the one analog circuit is influenced by the analog operation start of the other analog circuits in the operation cycle of the one analog circuit is retained as timing control data in advance, and the analog operation start of the other analog circuits is delayed or temporarily suppressed in synchronization with the operation start of the one analog circuit according to the timing control data. | 07-28-2011 |
| 20100275072 | CORRECTING APPARATUS, PDF MEASUREMENT APPARATUS, JITTER MEASUREMENT APPARATUS, JITTER SEPARATION APPARATUS, ELECTRIC DEVICE, CORRECTING METHOD, PROGRAM, AND RECORDING MEDIUM - There is provided a correcting apparatus for correcting a PDF obtained from a measurement result of measuring a characteristic of a measurement target at strobe timings including errors with respect to ideal timings at predetermined intervals, the correcting apparatus including: an interpolation section that is supplied with a CDF of the measurement result, interpolates a value between each strobe timing of the CDF, calculates a value of the CDF at each of the ideal timings, and calculates a corrected CDF at the ideal timings; and a corrected function generating section that generates a corrected PDF in which the errors of the strobe timings for the PDF have been corrected, based on the corrected CDF calculated by the interpolation section. | 10-28-2010 |
| 20120233510 | HIGH MEMORY DENSITY, HIGH INPUT/OUTPUT BANDWIDTH LOGIC-MEMORY STRUCTURE AND ARCHITECTURE - A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip. | 09-13-2012 |
| 20120278669 | RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION - For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data. The data is placed among data storage ranks The data storage ranks are balanced according to the adaptive data placement plan. | 11-01-2012 |
| 20120278668 | RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION - For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data. The data is placed among data storage ranks The data storage ranks are balanced according to the adaptive data placement plan. | 11-01-2012 |
| 20110320890 | DATA TRANSMISSION APPARATUS WITH INFORMATION SKEW AND REDUNDANT CONTROL INFORMATION AND METHOD - Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed. | 12-29-2011 |
