Class / Patent application number | Description | Number of patent applications / Date published |
714053000 | Address error | 18 |
20080320342 | MEMORY CONTROLLER - A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address. | 12-25-2008 |
20090006907 | METHOD AND APPARATUS FOR IDENTIFICATION OF PROGRAM CHECK ERRORS INDICATING CODE WITH HIGH POTENTIAL FOR STORAGE OVERLAY - In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not this interrupt involves or occurs as a result of an address translation. It is then determined whether or not, the instruction involved calls for an update of storage. If it is determined that all three of these conditions are satisfied, then a flag is set in an area of storage accessible to the operating system so that it may provide a more specific event monitoring record. | 01-01-2009 |
20090037782 | Detection of address decoder faults | 02-05-2009 |
20090254782 | METHOD AND DEVICE FOR DETECTING AN ERRONEOUS JUMP DURING PROGRAM EXECUTION - The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits. | 10-08-2009 |
20090300434 | Clearing Interrupts Raised While Performing Operating System Critical Tasks - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 12-03-2009 |
20100192026 | IMPLEMENTATIONS OF PROGRAM RUNTIME CHECKS - Runtime checks on a program may be used to determine whether a pointer points to a legitimate target before the pointer is dereferenced. Legitimate addresses, such as address-taken local variables (ATLVs), global variables, heap locations, functions, etc., are tracked, so that the legitimate targets of pointers are known. The program may be transformed so that, prior to dereferencing a pointer, the pointer is checked to ensure that it points to a legitimate address. If the pointer points to a legitimate address, then the dereferencing may proceed. Otherwise, an error routine may be invoked. One example way to keep track of legitimate addresses is to group address-taken variables together within a specific range or ranges of memory addresses, and to check that a pointer has a value within that range prior to dereferencing the pointer. However, addresses may be tracked in other ways. | 07-29-2010 |
20100251036 | IMPLEMENTATION OF MULTIPLE ERROR DETECTION SCHEMES FOR A CACHE - A cache includes a plurality of cache lines, where each cache line includes a detection type field, corresponding cache data field, a detection field, and a corresponding tag field. The detection type field indicates an error detection scheme from a plurality of error detection schemes currently in use for the corresponding cache data field. One example of an error detection scheme is a multiple bit error detection scheme (e.g. an error detection coding (EDC) or an error correction coding (ECC)). Another type is a single bit error detection scheme (e.g. parity error detection). The detection bits field stores parity bits if parity error detection is used. The detection bits field stores checking bits if EDC coding is used. | 09-30-2010 |
20110078517 | NETWORK CONNECTION DEVICE AND METHOD FOR DETECTING NETWORK ERRORS - A network error detecting method checks if a network connection device has an Internet protocol (IP) address, if domain name mapping of web pages is correct, and if data communication between a web browser and a web server is correct. Accordingly, the network connection device informs the web browser of an IP address error, a domain name mapping error, or a data communication error. The web browser displays the network errors to users when the network errors are detected. | 03-31-2011 |
20110271152 | FAILURE MANAGEMENT METHOD AND COMPUTER - A failure management method for a computer including a processor, and a memory connected to the processor, and in which the processor containing a memory protection function, executes a first software program and a second software program monitoring the operation of the first software program, and the second software program retains error information including address information and access-related information; and the method implemented by the by the second software program includes a step for detecting the occurrence of errors in the memory; and a step for prohibiting access to the address of the memory where the error occurred, and monitoring the access state; and a step for executing the failure processing when accessing by the first software program of the address of the memory where the error occurred was detected. | 11-03-2011 |
20110289365 | MANAGING A HOME NETWORK - A method for detecting an error in a home network while a network-compatible device is newly added to the home network, the home network having a modem configured to be connected to the Internet, a home gateway connected between the modem and the home network, the method for detecting the error comprising employing address resolution protocol and detecting the error in the home network due to filtering based on MAC addresses is disclosed. The disclosed subject matter can be used for diagnosis of problems in the home network that can arise due to filtering based on Media Access Control addresses by the home gateway. | 11-24-2011 |
20120278665 | METHOD AND APPARATUS FOR DETECTING MEMORY ACCESS FAULTS - Detecting a fault in the operation of a computer having a processor and a memory is taught. Instrumentation code is placed within an application program during compilation, and runtime library routines are modified to support detection of invalid memory accesses. Memory space is divided into application, shadow and unmapped memories. When accessing application memory at an original address, an address in shadow memory is computed by shifting the address and adding an offset. If the value stored at the shadow address indicates that the original address is invalid (e.g., not allocated or already freed), then error reporting code is executed that indicates the type of error and the location and optionally halts the computer. Invalid memory references to heap, stack and global objects in application memory can be detected. | 11-01-2012 |
20140082433 | SCSI Reservation Status Information on a SAN Disk - A method is disclosed for retrieving the reservation status information of a storage area network (SAN) device, a host transmits a persistent reservation in command with service action setting of ‘read reservation’ to a first LUN, wherein the host is connected to a port of the data storage server to which the LUN belongs. The host receives a message from the LUN. The host determines that the message is a success. The host sends to the LUN a persistent reservation in command with service action setting of ‘read keys’, responsive to a success message. The host determines that the LUN responds with a zero data length. The host determines the LUN is reserved with type 2 reservation, responsive to a determination that the LUN responds with a non-zero data length. | 03-20-2014 |
20140149808 | MEMORY DEVICES AND MEMORY SYSTEMS HAVING THE SAME - In one example embodiment, a memory device includes a cell array configured to receive data at an associated address in response to a write command. The memory device further includes a storage unit configured to receive the associated address and the data in response to the write command and output the data to the associated address of the cell array in response to a rewrite command. The memory device further includes a violation determining unit configured to determine violation data, count a number of the violation data and determine data written to the storage unit as the violation data if a storage duration of the written data is less than a write recovery time (tWR). | 05-29-2014 |
20140331095 | SYSTEM AND METHODS FOR MEMORY EXPANSION - This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel. | 11-06-2014 |
20140351660 | TWO-LEVEL SYSTEM MAIN MEMORY - Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. | 11-27-2014 |
20150058683 | RETENTION BASED DEFECTING IN A HYBRID MEMORY SYSTEM - A first page in a memory unit is programmed with one or more pages of the secondary memory. A first time corresponding to the start of the programming of the first page is recorded. A second time corresponding to the completion of the programming of the one or more pages is recorded. A time difference between the first time and the second time is determined. It is determined if the time difference is greater than a threshold. In response to the time difference being greater than the threshold, a retention based defecting process is for the memory unit is disabled. | 02-26-2015 |
20160139983 | DEVICE AND METHOD FOR DETECTING CONTROLLER SIGNAL ERRORS IN FLASH MEMORY - In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified. | 05-19-2016 |
20160179634 | DESIGN STRUCTURE FOR REDUCING POWER CONSUMPTION FOR MEMORY DEVICE | 06-23-2016 |