Class / Patent application number | Description | Number of patent applications / Date published |
714050000 | State out of sequence | 24 |
20100169720 | SYSTEM AND METHOD FOR DETERMINING RECOVERY TIME FOR INTERDEPENDENT RESOURCES IN HETEROGENEOUS COMPUTING ENVIRONMENT - A system and associated method for determining a recovery time for a resource in a heterogeneous computing environment comprising interdependent resources. A graph for the resource representing all sequence dependencies and all group relations are created. The recovery time may be a cumulative startup time or a cumulative shutdown time of the resource considering interdependencies of the resource to other resources. The recovery time for all support resources having sequence dependencies with the resource is calculated and each node representing the support resources are removed from the graph. Then the recovery time for all member resources left in the graph that have group relations with the resource is calculated per a group type of the resource. The recovery time for the resource is a sum of the recovery time of all support resources, the recovery time of all member resources, and a unit recovery time of the resource. | 07-01-2010 |
20110271151 | METHOD FOR PROVIDING ASYNCHRONOUS EVENT NOTIFICATION IN SYSTEMS - A method is provided for asynchronous notifications from a device to a host in systems without requiring hardware provision for asynchronous operations. In an embodiment of the invention, a system supports command queuing and a command is sent from a host to a device. The device receives the command and an associated tag, and accepts the command as valid. After accepting the command, the device begins monitoring for asynchronous events. If an asynchronous event is detected, the device provides notification of the event by sending a response and the associated tag to the host. In another embodiment of the invention, a method of asynchronous notification enables use of invalid tags. In a further embodiment of the invention, asynchronous notifications may be enabled by a host and operate without additional host commands. | 11-03-2011 |
20120042217 | STATE FEEDBACK CONTROL APPARATUS, STATE FEEDBACK CONTROLLER, AND STATE FEEDBACK CONTROL METHOD - A corrected state space model obtained by correcting a state space model to represent a controllable system by adding an error matrix Δ to a state space model representing an uncontrollable system is designed. A control object is controlled based on a control input of the system represented by this corrected state space model. The control input is calculated by a state feedback controller. By correcting the state space model representing the uncontrollable system by the error matrix Δ, the system can be made controllable. Since the error matrix Δ is added to a state matrix, an influence of an error on an output of the system can be reduced. | 02-16-2012 |
20120060064 | SOFT ERROR VERIFICATION IN HARDWARE DESIGNS - Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states. | 03-08-2012 |
20140281749 | LINEAR FEEDBACK SHIFT REGISTER WITH SINGLE BIT ERROR DETECTION - A linear feedback shift register machine capable of generating periodic sequences and having means for detecting single point errors in the generated sequences. | 09-18-2014 |
20160055048 | FLEXRAY NETWORK RUNTIME ERROR DETECTION AND CONTAINMENT - A FlexRay network guardian including: a resetting leading coldstart node (RLCN) detector configured to detect a RLCN failure; a deaf coldstart node (DCN) detector configured to detect a DCN failure; a babbling idiot (BI) detector configured to detect a BI failure; and a FlexRay network decoder configured to output a signal regarding the status of the FlexRay network to the RLCN detector, DCN detector, and BI detector, wherein the RLCN detector, DCN detector, and BI detector are configured to send an indication of a failure to a containment module. | 02-25-2016 |
714051000 | Control flow state sequence monitored (e.g., watchdog processor for control-flow checking) | 9 |
20100185903 | Failure Repetition Avoidance - Avoiding failure repetition in data processing includes storing a sequence of circumstances leading up to a previous failure, monitoring circumstances in a current process, matching a sequence of circumstances in the current process to a stored sequence of circumstances, and applying rules to determine if the current process should proceed. | 07-22-2010 |
20110016362 | CONTROLLER NETWORK AND METHOD FOR TRANSMITTING DATA IN A CONTROLLER NETWORK - A network having a plurality of subscribers has at least one message transmitter and at least one message receiver. The at least one message transmitter sends messages at predefined time intervals. The message receiver receives the messages at the predefined time intervals. A delay time of the messages is monitored on the basis of time outs. In addition, at least one of the subscribers repeatedly estimates a current delay time using a time measurement between sending out a request message and receiving a response message. The estimated delay time is compared with a predefined threshold value. If the estimated delay time exceeds the defined threshold value, an error signal is generated. | 01-20-2011 |
20120192017 | SYSTEM AND METHOD FOR EXECUTING A HIGH-RELIABILITY APPLICATION - A system for executing a high-reliability application and a third party application is provided. The system includes an application module and a second module. The application module has control logic for executing the high reliability application and the third party application. The high reliability application generates a message sequence. The application module includes a normal operating mode, a high reliability mode, and a high reliability boot. The second module is in communication with the application module, and includes a first control logic for monitoring the message sequence when the application module is operating in the normal operating mode. The second module also includes control logic for initiating the high reliability boot in the application module. | 07-26-2012 |
20140095945 | METHOD AND SYSTEM FOR PREEMPTIVE DETECTION OF OCCURRENCE OF FAULTY CONDITIONS BASED ON RESOURCE USAGE - A method and a system have been disclosed for the preemptive detection of occurrence of one or more faulty conditions based on the usage of one or more resources. The faulty conditions are detected during an execution of a program; the program includes at least one function. The method includes initializing Application Program Interfaces (APIs) across the at least one function. After this, calls to the APIs used within a namespace of the program are intercepted. The interception is performed by the at least one function through extended method classes. Thereafter, the usage of the resources for the at least function intercepting the APIs is checked against a corresponding predetermined threshold limit. Once the usage of the resources is checked, context of the usage of the resources is identified based on a predefined knowledge. Subsequently, the occurrence of the faulty conditions is determined based on the identification. | 04-03-2014 |
20140101496 | STATE MACHINE BASED PARSING ALGORITHM ON A DATA-STATUS FIFO WITH MULTIPLE BANKS - In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed. | 04-10-2014 |
20140149807 | Controller For Reading Data From Non-Volatile Memory - A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and directing transmission of the group of data units to the host in accordance with the first sequence. | 05-29-2014 |
20140317457 | SERVER SYSTEM - A server system includes at least one server and a server cabinet. The at least one server includes a first connection port and a baseboard management controller which detects a connection state of the first connection port and according to the connection state, outputs a data signal or a warning signal. The server cabinet includes chambers for containing the at least one server, and the chamber includes a second connection port and a storage unit. The storage unit stores data. When the connection state specifies that the first connection port couples to the second connection port, the baseboard management controller reads the data stored in the storage unit, to output the data signal. When the connection state specifies that the first connection port does not couple to the second connection port, the baseboard management controller outputs the warning signal. | 10-23-2014 |
20150089305 | INTERRUPT SUPERVISION SYSTEM, PROCESSING SYSTEM AND METHOD FOR INTERRUPT SUPERVISON - An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device receives the reception indication. | 03-26-2015 |
20150339179 | CONTROL OF MICROPROCESSORS - A microprocessor comprises a timer capable of resetting the device and a plurality of hardware registers ( | 11-26-2015 |
714052000 | Error checking code | 9 |
20080215929 | SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM - A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers. | 09-04-2008 |
20090006905 | In Situ Register State Error Recovery and Restart Mechanism - Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted. | 01-01-2009 |
20090006906 | Method and system for encoding data using rate-compatible irregular LDPC codes based on edge growth and parity splitting - In a system for parity encoding data using a low density parity check (LDPC) code, a rate-compatible, irregular LDPC code is generated by extending a base code using a constrained edge growth operation and a parity splitting operation. The base code is a “daughter” code having an encoding rate higher than a designated rate of the LDPC code. The daughter code is progressively extended to lower and lower rates such that each extension code (including the target LDPC code) is compatible with the previously obtained codes. The extension operation may involve introducing a set of new code symbols to the daughter code, by splitting check nodes of a base graph associated with the daughter code, and through constrained edge growth of the base graph. The LDPC code is used to parity encode a data message as a means for forward error correction across a communication channel. | 01-01-2009 |
20090070637 | ELECTRONIC CIRCUIT WITH A MEMORY MATRIX THAT STORES PAGES INCLUDING EXTRA DATA - An apparatus comprises a memory with a matrix ( | 03-12-2009 |
20090094489 | System, method and apparatus for tracing source of transmission error - A method and apparatus for identifying a device associated with a transmission error. The method generally comprising including a device identification information upon detection of a transmission error and further modifying an error check parameter according to a predefined rule. | 04-09-2009 |
20090150727 | DATA TRANSMISSION METHOD - An exemplary data transmission method is used in a data transmission system which has a data source, a data receiver, first, second, and third transmission lines connected between the data source and the data receiver. The data transmission method includes: the data source generating a checking code of a first byte and a second byte; transmitting the first byte, the second byte and the checking code from the data source to the data receiver via the first, second, and third transmission lines respectively; and the data receiver judging if the first byte, the second byte and the checking code are right, if right, transmission of the first byte and the second byte is complete, if one of the first byte and the second byte is wrong, and the checking code is right, the data receiver corrects the wrong byte via the checking code. | 06-11-2009 |
20100131804 | METHOD AND APPARATUS FOR SYMMETRY REDUCTION IN DISTRIBUTED MODEL CHECKING - A method for a model checking algorithm is provided. The method includes determining whether a class representative for a state has been processed, and generating a successor state for the state when the class representative for the state has not been processed. The method also includes determining which of a plurality of nodes is assigned to process the successor state, and processing the successor state at a node of the plurality of nodes that is assigned to process the successor state. | 05-27-2010 |
20150309866 | REJUVENATION OF LEGACY CODE INTO RESOURCES-ORIENTED ARCHITECTURES - A method for building a web-based application may include defining a scope of the web-based application, via a programming module, based on a plurality of parameters of a non-web-based application, and defining an error-handling mechanism based on an error-handling mechanism of the non-web-based application. The method may further include defining a plurality of resources for the web-based application, defining the mechanism of function for each resource of the plurality of resources, and generating the web-based application | 10-29-2015 |
20160124790 | COMMUNICATION SOFTWARE STACK OPTIMIZATION USING DISTRIBUTED ERROR CHECKING - A method of processing a request message begins when a first layer of a plurality of layers of a system stack receives the request message. In turn, the plurality of layers negotiate an agreement based on the request message, where the agreement indicates which layers will process particular error reply codes of an error reply code list. Then, a non-controller layer of the plurality of layers performs a first error check in accordance with the agreement and records a first error result in a communication interface based on the first error check; a controller layer of the plurality of layers performs a second error check in accordance with the agreement and records a second error result in the communication interface based on the second error check. Then a reply message responsive to the request message is outputted based on the first error check and the second error check. | 05-05-2016 |