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Memory or storage device component fault

Subclass of:

714 - Error detection/correction and fault detection/recovery


714001000 - Reliability and availability

714025000 - Fault locating (i.e., diagnosis or testing)

714040000 - Component dependent technique

Patent class list (only not empty are listed)

Deeper subclasses:

20130185598MULTI-TIER DETECTION AND DECODING IN FLASH MEMORIES - Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.07-18-2013
20130185599DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGHBORING BITS - Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a given page of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value for a bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the bit in the page using the reliability value. The probability that the data pattern was written to the plurality of bits given that the particular pattern was read from the plurality of bits is obtained from one or more tables.07-18-2013
20090024876System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation - A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.01-22-2009
20120266028ELECTRONIC DEVICE AND METHOD FOR DEBUGGING PROGRAMS - In a method for debugging programs of an electronic device, the method adds an appended block to one or more memory blocks allocated by one or more memory allocation functions of a specified program, so as to obtain one or more appended blocks, stores an identifier of each memory allocation function into a corresponding appended block, and executes a memory leak test to determine one or more unqualified memory allocation functions. The method further searches for one or more identifiers from the appended blocks if the memory leak test fails, and obtains a position of each unqualified memory allocation function in the specified program according to each found identifier if source codes of the specified program are available in a storage device of the electronic device.10-18-2012
20120266027STORAGE APPARATUS AND METHOD OF CONTROLLING THE SAME - Deterioration of performance due to diagnosis processing performed when a failure occurs is prevented.10-18-2012
20110022898NON-VOLATILE MEMORY SYSTEM WITH SELF TEST CAPABILITY - In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel.01-27-2011
20090006900SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM - A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.01-01-2009
20090006899ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT - A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.01-01-2009
20130166959SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD OF THE SAME - A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.06-27-2013
20080294943SATA INTERFACE TESTER AND TESTING METHOD - A serial advanced technology attachment (SATA) interface tester includes a memory, a signal converter, at least one SATA interface, and an indicator. The at least one SATA interface is adapted to connect with SATA interfaces of a motherboard, and is electrically connected to the memory via the signal converter. The signal converter receives serial signals from the motherboard via the at least one SATA interface and converts them to parallel signals and then passes the parallel signals to the memory to perform a writing process. The signal converter receives parallel signals from the memory and converts them to serial signals and passes the serial signals to the motherboard via the at least one SATA interface to perform a reading process. The indicator is electrically connected to the memory for indicating testing result of the SATA interfaces of the motherboard.11-27-2008
20080229154Self-referencing redundancy scheme for a content addressable memory - A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the faulty bit table, determine the data the faulty location should have held, and write that faulty data onto latches associated with the faulty memory elements.09-18-2008
20120317445DECONFIGURE STORAGE CLASS MEMORY COMMAND - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.12-13-2012
20120192012ELECTRONIC DEVICE AND METHOD FOR MANAGING TEST RESULTS - In a method for managing test results of an electronic device, the electronic device includes one or more expansion slots. The method selects a hard disk drive to insert into each expansion slot, executes a read-write test on each expansion slot, and saves test result(s) of the tests on each expansion slot into a file. Before managing the test results, the method sets a file name for each expansion slot for which test results is to be managed, and selects a test item from the read-write test. The method determines test results which expansion slots with are required to be managed and determines a test order of the expansion slots. After the test results are imported, the method amends a file name corresponding to each expansion slot according to the test order, and manages the test results of each expansion slot.07-26-2012
20080320337Removable Storage Media Drive Feature Enabling Self Test Without Presence of Removable Media - A method, system and apparatus for testing a removable storage media drive device are disclosed. According to teachings of the present disclosure, a simulated storage media may be disposed within a removable storage media drive device. In the event removable storage media is not present in the drive device when testing of the device is desired, the simulated storage media may be substituted for at least purposes of testing the operability of one or more device components. In one embodiment, the simulated storage media may be in the form of an annular ring of CD-ROM material. In a further embodiment, the simulated storage media may be in the form of a hologram designed to mimic one or more removable storage media characteristics.12-25-2008
20110283150STORAGE APPARATUS AND METHOD FOR CONTROLLING THE SAME - An objective is to allow a storage apparatus to accurately locate a failure site upon occurrence of a failure. Provided is a storage apparatus 11-17-2011
20110276837METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method and system for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a portion of a file and a checksum representing data within the memory block at a first time. Based at least in part on determining that the memory block is mapped to the same portion of the same file at a second time, it is indicated that the checksum represents expected data within the memory block. A system for verifying memory device integrity is also disclosed.11-10-2011
20110289359RECONFIGURING DATA STORAGE IN MULTIPLE DISPERSED STORAGE NETWORKS - A method begins by a processing module determining access performance to copies of dispersed storage encoded data, wherein the copies of the dispersed storage encoded data are stored in a set of a plurality of dispersed storage networks (DSNs). The method continues with the processing module modifying the set of the plurality of DSNs based on the access performance and the desired access performance level to produce a modified set of the plurality of DSNs when the access performance is not at a desired access performance level. The method continues with the processing module, for a new DSN of the modified set of the plurality of DSNs, determining error coding dispersal storage parameters based on local data retrieval accesses allocated to the new DSN and facilitating the new DSN storing another copy of the dispersed storage encoded data.11-24-2011
20110289358STORING DATA IN MULTIPLE DISPERSED STORAGE NETWORKS - A method begins by a processing module identifying a plurality of dispersed storage networks (DSNs) for storing copies of dispersed storage encoded data based on global data retrieval accesses of the copies of the dispersed storage encoded data. The method continues with the processing module determining a set of error coding dispersal storage parameters for at least one of the plurality of DSNs based on local data retrieval accesses allocated to the at least one of the plurality of DSNs. The method continues with the processing module encoding data in accordance with the set of error coding dispersal storage parameters to produce a copy of the copies of the dispersed storage encoded data and outputting the copy of the copies of the dispersed storage encoded data to the at least one of the plurality of DSNs.11-24-2011
20110296249SELECTING A CONFIGURATION FOR AN APPLICATION - There is provided a computer-implemented method for selecting from a plurality of full configurations of a storage system an operational configuration for executing an application. An exemplary method comprises obtaining application performance data for the application on each of a plurality of test configurations. The exemplary method also comprises obtaining benchmark performance data with respect to execution of a benchmark on the plurality of full configurations, one or more degraded configurations of the full configurations and the plurality of test configurations. The exemplary method additionally comprises estimating a metric for executing the application on each of the plurality of full configurations based on the application performance data and the benchmark performance data. The operational configuration may be selected from among the plurality full configurations based on the metric.12-01-2011
20080270842COMPUTER OPERATING SYSTEM HANDLING OF SEVERE HARDWARE ERRORS - A system and method is provided for handling severe hardware errors communicated to a computer operating system as an abort indication. The method includes classifying the type of abort into a memory-related error or non-memory-related error. For memory-related errors, a debug file is written that includes error source information for an affected process without accessing the affected process memory.10-30-2008
20110219269COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and sets the defective cell to be assigned to one of the devices if a defective cell is found.09-08-2011
20100115345Apparatus, System, and Method for Rapid Grading of Computer Storage Operating Condition - An apparatus, system, and method are disclosed for rapidly grading the operating condition of computer storage. A storage log module 05-06-2010
20100115344MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY - Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.05-06-2010
20100088550CACHE MEMORY APPARATUS, EXECUTION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.04-08-2010
20100122118Disk-Drive Write Head Fault Detection - One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.05-13-2010
20100083050ERROR DETECTION CONTROL SYSTEM - An error detection control system for a nonvolatile memory comprises: a nonvolatile memory having data areas for a plurality of addresses each including a main data area and a redundant data area for one address; memory control means for controlling on the nonvolatile memory a batch erasing process on a data area group basis, a reading process on the data area basis, a programming process on the data area basis, and an overwriting process on a bit basis; error detecting means for executing the error detecting process based upon the corresponding redundant data; error detecting control means for controlling availability of execution of the error detecting process based upon data types to be classified depending on whether or not the data is subjected to the overwriting process or a storage state indicating whether or not the overwriting process has been executed.04-01-2010
20100083051GAMING APPARATUS HAVING MEMORY FAULT DETECTION - In the information process device 04-01-2010
20090300425Resilience to Memory Errors with Firmware Assistance - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.12-03-2009
20120297253SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PHYSICAL DRIVE FAILURE IDENTIFICATION, PREVENTION, AND MINIMIZATION OF FIRMWARE REVISIONS - In one embodiment, a system includes logic adapted for receiving information relating to disk drive media (DDM) failures in an installed base of DDM across multiple virtual tape servers, a storage device adapted for storing the information relating to the DDM failures in a data repository, and a processor adapted for analyzing the information stored in the data repository to identify problems in an installed base of DDM, the analysis comprising analyzing comparative DDM failure data comprising vectors. In another embodiment, a method for managing DDM failures includes receiving DDM failure information in virtual tape servers, storing the DDM failure information in a data repository, and analyzing the information to identify problems in an installed base of DDM. Other systems, methods, and computer program products are also described according to more embodiments.11-22-2012
20080235537System and method for electronic testing of multiple memory devices - A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.09-25-2008
20080270843CONVOLUTION-ENCODED DATA STORAGE ON A REDUNDANT ARRAY OF INDEPENDENT DEVICES - A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.10-30-2008
20090183032Data processing apparatus and method for testing stability of memory cells in a memory device - A data processing apparatus and method are provided for testing stability of memory cells in a memory device. A data processing apparatus comprises a memory device having an array of memory cells for storing data values. Test circuitry is employed in a test mode of operation to execute one or more test patterns in order to detect any memory cells which may malfunction in a normal mode of operation due to cell instability following a write operation, as for example may be caused by body region history effect in embodiments where each memory cell comprises at least one transistor having a body region insulated from a substrate. Each test pattern causes a sequence of access requests to be issued to the memory device whose timing is controlled by a test mode clock signal. Dummy read control circuitry is employed in the test mode of operation, and is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. Further, the dummy read control circuitry is responsive to each write access request to perform using the internal clock signal a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same at least one memory cell, the dummy read operation serving to stress the at least one memory cell with respect to cell stability. This approach provides a very reliable, effective and realistic (in terms of test time) mechanism for detecting memory cells which may malfunction in normal use due to cell instability following a write operation.07-16-2009
20090187793EFFECTIVE METHOD TO PERFORM MEMORY TEST USING MULTIPLE PROCESSOR UNIT, DMA, AND SIMD INSTRUCTION - To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS). The method and the like including: MP allocating a partial memory region (PMA) in MM to each SP; MP requesting each SP to test the allocated PMA; each SP filling LS thereof with initial data in response to receiving the request; each SP transferring the data stored in LS thereof to PMA by using a DMA transfer; each SP transferring the data stored in PMA to LS thereof by a DMA transfer; and SP testing the data in LS; and MP judging a test result on MM by putting together the tests results in response to the completion of all the tests by respective SP.07-23-2009
20090199046Mechanism to Perform Debugging of Global Shared Memory (GSM) Operations - A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.08-06-2009
20090055688DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM - Methods are provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is, changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.02-26-2009
20090083584Method for maintaining track data integrity in magnetic disk storage devices - Techniques for detection of impending data errors in a mass storage system, such as a track squeeze problem in an electromagnetic disk drive, and then repairing the impending problem, such as by rewriting the affected tracks. In many cases the problem is detected and repair is effected when the original data can still be read. In other cases, when the data is no longer readable on the disk in question, but when the disk is part of a Redundant Array of Independent Disks (RAID) system, or other system in which higher layer fault tolerance mechanisms are implemented, the missing data can be recovered via these mechanisms. The recovered data is then used to repair the track squeeze problem. The invention can be implemented as firmware in a storage system, as a component of a general purpose operating system, or inside individual disk drives, or it can use a combination of these implementations.03-26-2009
20090106603Data Corruption Diagnostic Engine - A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.04-23-2009
20090210750Systems And Methods For Identifying Memory Leaks In A Computer System - Systems and methods are provided for identifying memory leaks in a computer system. Testing software is inserted into one or more memory routines of a computer system to cause at least two successive tests of the memory routines during which the memory routines perform memory operations to allocate and de-allocate memory from a plurality of memory areas, such as pools or heaps. Information is captured that identifies at least a number of memory allocations and a number of memory de-allocations performed by the memory routines during the pendency of the tests. The captured information is compared to identify one or more candidate memory areas from the plurality of memory areas. A candidate memory areas is identified when the difference between the number of memory allocations and the number of memory de-allocations increases from one test to the next. Each candidate memory area is then evaluated further to identify any specific memory leaks within the memory area.08-20-2009
20120198284MEMORY CORRECTNESS CHECKING IN DISTRIBUTED COMPUTER SYSTEMS - A remote data memory access method for use in a computer system having a plurality of nodes, each node using a respective memory and remote data memory access between nodes being performed by transferring user data from the memory used by one node to the memory used by another node, the method comprising: maintaining memory correctness information of the user data at a subunit level; selecting subunits of user data for transfer in dependence upon memory correctness information of each subunit; and selectively transferring the subunits so selected. The method preferably involves transferring the memory correctness information of at least the selected subunits of user data, in addition to the selected subunits of user data. The memory correctness information may be compressed prior to transfer.08-02-2012
20090259891DEFECT DETECTION APPARATUS FOR OPTICAL DISC AND METHOD THEREOF - Disclosed is a defect detection apparatus of an optical disk drive. The optical disc drive records a set of first data onto at least one data unit of an optical disc. The defect detection apparatus comprises an error detector and a defect verification unit. The error detector receives the set of first data, being recorded and the set of second data derived from the data unit of the optical disc, and then compares the set of first data with that of second data to generate error information of the set of second data. The defect verification unit determines whether the data unit is defective according to the error information. The object that the defect detection apparatus of the invention performs verification for can be a sector, an ECC Block or a cluster. The error detector can be a channel bit error detector, a byte error detector or a frame error detector.10-15-2009
20080307268SELF-HEALING CACHE OPERATIONS - A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.12-11-2008
20100185900VIDEO RECORDING AND REPRODUCING APPARATUS AND METHOD THEREOF - Achieving improvement in protection of recorded data and reproduction performance and editing performance of video data and audio data, in addition to minimizing the number of disk devices, an inexpensive and high-performance video recording and reproducing apparatus (07-22-2010
20100185899RAID TESTING METHOD AND TESTING SYSTEM - A RAID testing method and a RAID testing system including a reading unit, an option-ROM, a recording unit and several RAID configuration data are provided. These data are either contained in several binary files or stored in a memory. In the method, first, these data are read by the reading unit under a first mode to simulate connecting to several physical disk drives in a first manner. Then, a global RAID configuration information is generated according to these RAID configuration data. Further, these data are read by the reading unit under a second mode to simulate connecting to these physical disk drives in a second manner. Afterwards the global RAID configuration information is updated by the option-ROM in accordance with the second mode. Moreover, the global RAID configuration information is recorded by the recording unit.07-22-2010
20100262868Managing Possibly Logically Bad Blocks in Storage Devices - If data is lost a possibly logically bad pattern is placed in a standard size data block in a storage device, and the Logical Block Address associated with the data block is inserted in a Bad Block Table. The possibly logically bad pattern is able to be detected, and the Bad Block Table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given to a host if a Logical Block Address associated with the standard size data block is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.10-14-2010
20100218050Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading - A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.08-26-2010
20090319834COMPUTER-READABLE STORAGE MEDIUM STORING STORAGE MANAGEMENT PROGRAM, STORAGE MANAGEMENT METHOD,AND STORAGE MANAGEMENT APPARATUS - A storage management apparatus that performs a read/write check on each of a plurality of data-storing areas of a storage device, and is formed by a storage node that performs reading/writing of the data in the storage device. A computer determines whether or not the data exits, by referring to a flag provided in each data-storing area. The computer performs only an operation of writing the data into the data-storing area in which the data does not exist, and perform operations of reading and writing the data from and into the data-storing area in which the data exists.12-24-2009
20120198283System And Method for Fast Boot from Non-Volatile Memory - Described herein are systems and methods for fast boot from non-volatile (“NV”) memory. The exemplary embodiments relate to systems and methods for significant improvements in performance speed with simple implementations. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to identify a page fault, determine whether the page fault occurred due to a read from a NV memory, copy a page from the NV memory to a random-access memory (“RAM”) storage, and create an identity mapping for the page in the RAM storage. A further embodiment relates to a system comprising a NV memory, a random access memory, and a processor executing a set of instructions, wherein the set of instructions being operable to identify a page fault, determine whether a page fault occurred due to a read from the NV memory, copy a page from the NV memory to the RAM storage, and create an identity mapping for the page in the RAM storage.08-02-2012
20090106602Method for detecting problematic disk drives and disk channels in a RAID memory system based on command processing latency - In order to detect problematic drives in random arrays of independent disks, the system measures the latency of executing command sets which are broadcast to all disks in the data storage system and the results are compared to identify which disks take substantially longer to complete the requests. Disks that take longer to complete requests are likely to be problematic and are candidates for further examination and replacement. The disks in each tier group are compared to determine if any disk in that group exhibits problems. Also, counters for each tier group are compared to determine if the problem is with the disk or with the channel of the tier group. The latency of each disk in the tier group is saved in a table to provide a histogram of the latency of the disks in the tier group. Histograms of the disks in a single tier group are compared to determine if a specific disk is problematic. Histograms of each tier group are compared to determine if a specific disk is problematic or all the disks on the same channel exhibit problems.04-23-2009
20080229155ENHANCED ERROR IDENTIFICATION WITH DISK ARRAY PARITY CHECKING - When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented.09-18-2008
20090070632System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation - A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.03-12-2009
20130132779MEMORY MODULES WITH RELIABILITY AND SERVICEABILITY FUNCTIONS - One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.05-23-2013
20100313077ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.12-09-2010
20100313076SCANNING REASSIGNED DATA STORAGE LOCATIONS - An aspect of the present disclosure relates to scanning reassigned data storage locations. In one example, a reassignment table is accessed to identify a deallocated data storage location and scan the deallocated data storage location for media defects.12-09-2010
20090077425Method and Apparatus for Detection of Data Errors in Tag Arrays - A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.03-19-2009
20110078512METHOD AND APPARATUS FOR DISPERSED STORAGE MEMORY DEVICE UTILIZATION - A method begins by a processing module receiving data for storage. The method continues with the processing module determining storage metadata regarding the data the method continues with the processing module. The method continues with the processing module determining memory device capabilities based on the storage metadata. The method continues with the processing module identifying memory devices based on the memory device capabilities to produce identified memory devices. The method continues with the processing module encoding the data into a plurality of data slices in accordance with an error coding dispersal function. The method continues with the processing module storing the plurality of data slices in the identified memory devices.03-31-2011
20100037102FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE - Various embodiments of the present invention are generally directed to an apparatus and method for providing a fault-tolerant non-volatile buddy memory structure, such as a buddy cache structure for a controller in a data storage device. A semiconductor memory array of blocks of non-volatile resistive sense memory (RSM) cells is arranged to form a buddy memory structure comprising a first set of blocks in a first location of the array and a second set of blocks in a second location of the array configured to redundantly mirror the first set of blocks. A read circuit decodes a fault map which identifies a defect in a selected one of the first and second sets of blocks and concurrently outputs data stored in the remaining one of the first and second sets of blocks responsive to a data read operation upon said buddy memory structure.02-11-2010
20090217102Fault Diagnosis of Serially-Addressed Memory Chips on a Test Adaptor Board To a Middle Memory-Module Slot on a PC Motherboard - A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.08-27-2009
20110154123System and Method for Protecting Users of Data Storage Systems Against Know Problems - Methods and apparatus automatically identify certain types of data storage system problems, such as a flawed storage device or an incompatibility between a data storage system and a data storage device or an incompatibility between the storage system and a user computer. The existence of such a problem may be highlighted to a user through an indicator on the storage system and/or through a “dashboard” application being executed by the user computer, and the problem may be automatically corrected by automatically downloading a fix (e.g., new firmware or a “patch”) from a server (e.g., a server managed by the storage device manufacturer, a server managed by the storage system manufacturer and/or a server managed by a third party) and automatically implementing the fix.06-23-2011
20120304016STORAGE CONTROL DEVICE, STORAGE DEVICE, AND DIAGNOSTIC METHOD - A storage control device includes an interface for a host computer and a memory device and a control unit that creates a read command that causes the memory device to reproduce data at an access target address, and creates a first diagnosis command that causes the memory device to conduct a diagnostic reproduction at an address subsequent to the access target address, according to the request received from the host computer, sequentially issues the read command and the first diagnosis command to cause the memory devices to execute sequential accessing and conducts a diagnosis to confirm the normality of the memory device.11-29-2012
20110258491TEST APPARATUS AND TEST METHOD - A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.10-20-2011
20080320336System and Method of Client Side Analysis for Identifying Failing RAM After a User Mode or Kernel Mode Exception - A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the computing system's memory containing the binary code that was executing at the time of the exception. The exception-causing code from the system memory may be compared to an original version of the code from a non-volatile source. If the comparison identifies a hardware corruption pattern, the computing system may communicate information about the process and the exception to an error analysis server. Using historical exception data, the error analysis server may determine if the identified corruption pattern is most likely the result of corrupt hardware at the computing system. If corrupt hardware was the most likely result of the exception, then the server may communicate with the computing system to recommend or initiate a hardware diagnostic routine at the computing system to identify the faulty hardware.12-25-2008
20110179311INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM - In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.07-21-2011
20110179310STORAGE SYSTEM DETECTING PHYSICAL STORAGE DEVICE SUFFERING FAILURE, AND METHOD OF PERFORMING PROCESSING FOR ADDITIONAL STORAGE DEVICE PROVISION - In a storage system, a first loop and a second loop are connected to a controller, and at least one of the first loop and the second loop is connected to existing storage devices (which are physical storage devices other than additional storage devices, which are physical storage devices which are additionally provided). In processing for additional provision, after having disconnected all of the existing storage devices from the first loop, the controller connects an additional storage device to the first loop. And the controller acquires, via said first loop, an address acquired by this additional storage device, and makes a first suitability decision as to whether or not this address is appropriate. And, if the result of this first suitability decision is negative, then the controller blocks up this additional storage device whose address has been acquired.07-21-2011
20120311388APPARATUS AND METHODS FOR PROVIDING DATA INTEGRITY - The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.12-06-2012
20120278662METHODS AND STRUCTURE FOR DEBUGGING DDR MEMORY OF A STORAGE CONTROLLER - Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.11-01-2012
20110264963SYSTEM FOR CHECKING A PROGRAM MEMORY OF A PROCESSING UNIT - A system for checking a program memory) of a processing unit includes a check module, and the processing unit is made up of an instruction counter connected to the check module. The check module has a register connected to a first changeover switch that sets the register content. In a system that allows for the instruction addresses of the entire program memory to be checked, the instruction counter contains an ancillary counter, which runs through the instruction address space of the program memory independently of the program code during normal operation and which is connected to the register.10-27-2011
20110119531Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (IC) Design - Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.05-19-2011
20110126056PROCESSOR PERFORMANCE ADJUSTMENT SYSTEM AND METHOD - The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.05-26-2011
20110087928SYSTEMS AND METHODS FOR MANAGING STALLED STORAGE DEVICES - Embodiments relate to systems and methods for managing stalled storage devices of a storage system. In one embodiment, a method for managing access to storage devices includes determining that a first storage device, which stores a first resource, is stalled and transitioning the first storage device to a stalled state. The method also includes receiving an access request for at least a portion of the first resource while the first storage device is in the stalled state and attempting to provide access to a representation of the portion of the first resource from at least a second storage device that is not in a stalled state. In another embodiment, a method of managing access requests by a thread for a resource stored on a storage device includes initializing a thread access level for an access request by a thread for the resource. The method also includes determining whether the storage device, which has a device access level, is accessible based at least in part on the thread access level and the device access level and selecting a thread operation based at least in part on the determination of whether the storage device is accessible. The thread operation may be selected from attempting the thread access request if the device is accessible and determining whether to restart the thread access request if the device is not accessible.04-14-2011
20090300426TESTING A VIRTUALISED STORAGE SYSTEM IN RESPONSE TO DISK EXERCISING COMMANDS - Provided are a method, apparatus, and computer program product for testing a virtualised storage system. Data defining one or more configuration features of the virtualised storage system is received. Also received is a set of one or more predetermined rules defining interpretation of the disk exercising commands, the interpretation being dependent on one or more of the configuration features. A first disk exercising command is received. The first disk exercising command is interpreted in accordance with one of the predetermined rules to produce a second disk exercising command. The second disk exercising command is sent to the virtualised storage system.12-03-2009
20090204852SOLID STATE STORAGE SUBSYSTEM THAT MAINTAINS AND PROVIDES ACCESS TO DATA REFLECTIVE OF A FAILURE RISK - A storage subsystem is disclosed that maintains (a) statistics regarding errors detected via an ECC (error correction code) module of the storage subsystem; and/or (b) historical data regarding operating conditions experienced by the storage subsystem, such as temperature, altitude, humidity, shock, and/or input voltage level. The storage subsystem, and/or a host system to which the storage subsystem attaches, may analyze the stored data to assess a risk of a failure event such as an uncorrectable data error. The results of this analysis may be displayed via a user interface of the host system, and/or may be used to automatically take a precautionary action such as transmitting an alert message or changing a mode of operation of the storage subsystem.08-13-2009
20100017660System and method for protecting memory stacks using a debug unit - A method is disclosed for detecting a memory stack fault. The method may include reserving a memory stack for executing software instructions. The method may also include enabling a debug unit and as the software instructions are execute, utilizing the debug unit to monitor a memory space adjacent to the memory stack. The method may further include identifying a memory stack fault if a write operation to the memory space is attempted.01-21-2010
20120042211Controlling a Solid State Disk (SSD) Device - A mechanism is provided for controlling a solid state disk. A failure detector detects a failure in the solid state disk. Responsive to failure detector detecting a failure, a status degrader sets a degraded status indicator for the solid state disk. Responsive to the degraded status indicator, a degraded status controller maintains the solid state disk in operation in a degraded operation mode.02-16-2012
20090113249Stress testing method of file system - A stress testing method of a file system includes traversing local or network storage devices with a drive letter; detecting a network mapping path of the network storage devices; calculating an absolute path of all the storage devices through a mounted point and a system volume; collecting the above information to update the path information of the file system; and then calling a corresponding test algorithm and stressing strategy according to different types of storage devices, so as to perform the stress test. The stress testing method can make the file system display storage devices without a drive letter, and call appropriate testing methods and stressing strategies for different types of storage devices, so the depth and scope of the stress testing for file system are expanded, the accuracy of the test is enhanced, and the problem of occupying too many system resources is avoided.04-30-2009
20110167305Methods and Apparatus for Soft Data Generation for Memory Devices Based on Performance Factor Adjustment - Methods and apparatus are provided for soft data generation for memory devices based on a performance factor adjustment. At least one soft data value is generated for a memory device, by obtaining at least one read value; and generating the soft data value based on the obtained at least one read value and an adjustment based on one or more performance factors of the memory device. The read values may comprise, for example, data bits, voltage levels, current levels or resistance levels. The read values may be soft data or hard data. The possible performance factors include endurance, number of read cycles, retention time, temperature, process corner, inter-cell interference impact, location within the memory array and a pattern of aggressor cells. One or more pattern-dependent performance factors and/pr location-specific performance factors may also be considered. The generated soft data value may be a soft read value that is used to generate one or more log likelihood ratios, or may be the log likelihood ratios themselves.07-07-2011
20120023374INFORMATION PROCESSING DEVICE EQUIPPED WITH WRITE-BACK CACHE AND DIAGNOSIS METHOD FOR MAIN MEMORY OF THE SAME - The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.01-26-2012
20120159262EXTENDED PAGE PATCHING - The embodiments described herein generally relate to methods and systems for using an extended patching procedure for correction or repair of logical data portions, pages, or sectors of a computer data storage device. The extended patching procedure targets for repair not only the page(s) appearing to be defective or unusable based on a failed read operation for a data transfer request, but also additional pages. Determining the additional pages to include for automatic patching is based on: statistical distribution analyses to include pages within the physical or logical vicinity of the original page, information about the underlying storage device technology or Input/Output (I/O) subsystem, and/or historical data about error conditions for areas related to the original page. Preemptively patching pages based on extended page lists improves system performance by reducing the total number of costly repair processes and by avoiding situations involving correction actions that fail to resolve.06-21-2012
20120072778DIAGNOSIS SYSTEM FOR REMOVABLE MEDIA DRIVE - Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison.03-22-2012
20120166885SYSTEM AND METHOD FOR TESTING HARD DISK DRIVE OF COMPUTING DEVICE - A system and method test serial attached SCSI (SAS) hard disk drives (HDDs) of a computing device. The computing device includes a SAS backpanel, and the SAS backpanel includes one or more connectors that are respectively connected to the SAS HDDs. An identification (ID) of each of the connectors and an SCSI address of each of the SAS HDDs are obtained. A predefined file is created, and the obtained ID of each connector and the SCSI address of each SAS HDD are recorded into the predefined file. An SCSI address of a SAS HDD to be tested is obtained from the predefined file, and functions of the SAS HDD are tested. An ID of the connector connected to the SAS HDD is obtained from the predefined file, and is displayed on a display device if one or more of the functions are abnormal.06-28-2012
20120216079Obtaining Debug Information from a Flash Memory Device - This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.08-23-2012
20120173932STORAGE CODES FOR DATA RECOVERY - A random permutation code is described which provides efficient repair of data nodes. A specific implementation of a permutation code is also described, followed by description of a MISER-Permutation code. Finally, an optimal repair strategy is explained that involves an iterative process of downloading the most effective available parity data, updating costs of remaining parity data, and repeating until the data is recovered.07-05-2012
20100050021ERROR CODE HANDLING IN A STORAGE SUBSYSTEM - Disclosed is a computer implemented method and apparatus for making ownership changes to a storage subsystem. The host sends the first ownership change command to the storage subsystem then determines whether the storage subsystem responded with an error message. Upon responding to a determination that the storage subsystem responded with the error message, the host determines whether the storage subsystem indicated an error associated with an ownership change. In response to a determination that the storage subsystem indicated an error associated with an ownership change, the host sends a discover ownership message to the storage subsystem. Upon receiving a list of logical unit number associations from the storage subsystem, the host responds to receiving a list of logical unit number associations. The host performs a second ownership command to determine whether the list of logical unit number associations matches an ownership defined in the ownership change command. The host responds to a determination that the list of logical unit number associations matches an ownership defined in the ownership change command by aborting ownership changes.02-25-2010
20120179937STORAGE SYSTEM AND CONTROL METHOD THEREOF - Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.07-12-2012
20100275066IDENTIFYING A STORAGE DEVICE AS FAULTY FOR A FIRST STORAGE VOLUME WITHOUT IDENTIFYING THE STORAGE DEVICE AS FAULTY FOR A SECOND STORAGE VOLUME - Storage volumes are provided across a plurality of storage devices, where the storage volumes include at least a first storage volume and a second storage volume. A storage controller detects fault in a portion of a particular one of the plurality of storage devices, where the portion corresponds to the first storage volume. The storage controller identifies the particular storage device as faulty for the first storage volume without identifying the particular storage device as faulty for the second storage volume.10-28-2010
20120185733APPLICATION RELIABILITY AND FAULT TOLERANT CHIP CONFIGURATIONS - An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes. Creating a communication path between the application and the hardware registers would allow the application to modify the reliability of memory operations07-19-2012
20120324294MEMORY DIAGNOSTIC METHOD, MEMORY DIAGNOSTIC DEVICE, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - In a memory diagnostic method, a fixed domain stores data that are not changed during process execution. A variable domain stores data that are subject to writing during process execution. A fixed domain diagnostic part adds an error-detecting code to data to be stored in the fixed domain. The fixed domain diagnostic part compares an error-detecting code calculated from data read from the fixed domain with the added error-detecting code to determine whether there is any data error. A variable domain diagnostic part temporarily stores data stored in the variable domain in a memory region different from the memory storing the data, and writes known data in the variable domain where the temporarily stored data were stored. The variable domain diagnostic part reads data from the region where the known data were written and determines whether the data is the same as the written known data.12-20-2012
20110252280INTELLIGENT LUN GENERATION AND MANAGEMENT - An apparatus for generating and managing logical units (LUNs) in a storage network environment is disclosed herein. In one embodiment, such an apparatus includes an identification module to identify a type of LUN, one or more servers that will access the LUN, and a storage system that will host the LUN. A mapping module maps the type, the one or more servers, and the storage system to one more abbreviations. A naming module then generates a LUN name that encapsulates the abbreviations. An assignment module may then assign the LUN name to the LUN. A corresponding method and computer program product are also disclosed herein.10-13-2011
20080301504Method and Apparatus to Anticipate Memory Exhaustion in an Open Services Gateway Initiative Environment - A computer implemented method, computer program product, and data processing system for predicting a future status of a memory leak. A first set of data including memory consumption data is received at a software bundle. The software bundle is operating in an open services gateway initiative environment. Responsive to a determination that a memory leak exists, the first set of data is analyzed to predict a future status of the memory leak. The future status is stored, as stored data, in a storage device.12-04-2008
20130024732Protecting Storage Fabrics from Errant Device Causing Single Point of Failure - A mechanism is provided for protecting storage fabrics from an errant device causing a single point of failure. The mechanism identities a source of the out-of-context traffic, isolates the TAG to prevent further catastrophe, and ensures that device isolation control operations are processed timely allowing device isolation and removing the source of the issue. Should device isolation not solve the issue, the mechanism allows the host to use a binary search method to isolate the device that may be hiding its true identity and sourcing possibly malicious traffic.01-24-2013
20130173966MEMORY CONTROLLER AND MEMORY ACCESS SYSTEM - A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.07-04-2013
20130173967HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE - A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.07-04-2013
20130124925METHOD AND APPARATUS FOR CHECKING A MAIN MEMORY OF A PROCESSOR - A method and an apparatus for checking a main memory of a processor, which includes a cache memory and a plurality of registers. Before the memory test is carried out, a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test is written to at least one register and is held there, and the access from the cache memory to the main memory is activated. The main memory is accessed via the cache memory such that bit patterns are written to the cache memory and from there to the main memory, and are read out again from the main memory via the cache memory and are compared. The area of the main memory to be tested is larger than the size of the cache memory. The interrupted boot-up sequence is then restarted or continued after completion of the memory test.05-16-2013

Patent applications in class Memory or storage device component fault