Class / Patent application number | Description | Number of patent applications / Date published |
714035000 | Substituted or added instruction (e.g., code instrumenting, breakpoint instruction) | 55 |
20080320331 | CONTROL APPARATUS - For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator ( | 12-25-2008 |
20090055687 | RAM diagnosis device and RAM diagnosis method - A RAM diagnosis device sequentially generates a state bit indicating any one of states of kinds of processing; selects processing referring to the state bit. The devices then writes a first data pattern in all areas of the RAM when writing processing is selected, and writes a second data pattern obtained by inverting the first data pattern in all the areas of the RAM when the writing processing is selected. The first data pattern is binary data. The device also reads out the first or the second data pattern from all the areas of the RAM to detect an error when error check processing is selected after each of the kinds of writing processing. | 02-26-2009 |
20090259890 | Method & apparatus for hardware fault management - A hardware health evaluation module is associated with a hardware module or device and employs a linked list of error records to continually evaluate the state of the hardware module to determine whether or not it is currently operating with or without errors. In the event that the health evaluation module determines that the hardware module is not operating in an error free manner, it detects and stores, for a specified period of time, an indication of the error and associates this detected error or errors with one or more of the error records. The error records are designed to provide assistance in diagnosing the cause of a hardware error. | 10-15-2009 |
20090271661 | STATUS TRANSITION TEST SUPPORT DEVICE, STATUS TRANSITION TEST SUPPORT METHOD, AND RECORDING MEDIUM - A status transition table generation portion generates a status transition table containing combination information cells provided in the form of a matrix for describing information corresponding to combinations of internal status and event. In a status transition table design support portion, a test path generation portion generates a test path including a series of test cases to be executed as a status transition test, based on information accepted by an operation specification information input acceptance portion. In a test support portion, a test cell highlight portion highlights a combination information cell associated with the next test case to be executed, during execution of the status transition test, and a test result history, an error replication procedure, and test progress are displayed on a display portion. | 10-29-2009 |
20090300420 | Method for Testing at Least One Arithmetic Unit Installed in a Control Unit - A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit. | 12-03-2009 |
20100017658 | TEST SYSTEM AND METHOD WITH A SIMULATOR - A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic devices through the simulation control device. The master device records input signals of the input device and generate simulation signals according to the input signals. The simulation control device simulates the input signals of the input device according to the simulation signals to test the electronic devices. | 01-21-2010 |
20100037100 | METHOD AND SYSTEM FOR ISOLATING SOFTWARE COMPONENTS - A software testing system operative to test a software application comprising a plurality of software components, at least some of which are highly coupled hence unable to support a dependency injection, each software component operative to perform a function, the system comprising apparatus for at least partially isolating, from within the software application, at least one highly coupled software component which performs a given function, and apparatus for testing at least the at least partially isolated highly coupled software component. | 02-11-2010 |
20100058111 | ABNORMALITY DETECTION METHOD FOR ELECTRONIC DEVICE CONNECTED BY LOOP, AND ELECTRONIC DEVICE - An electronic device is connected to a loop transmission line via a bypass circuit and detects being bypassed from the loop transmission line. Each electronic device connected to a looped transmission line via each bypass circuit receives a positioning map in which an own address is registered, and judges whether the own address is still registered. The electronic device can judge whether this electronic device is being bypassed from the loop transmission line by the bypass circuit using a conventional sequence. | 03-04-2010 |
20100095156 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis. | 04-15-2010 |
20100122117 | Directed Design of Experiments for Validating Probability of Detection Capability of a Testing System - A method of validating a probability of detection (POD) testing system using directed design of experiments (DOE) includes recording an input data set of observed hit and miss or analog data for sample components as a function of size of a flaw in the components. The method also includes processing the input data set to generate an output data set having an optimal class width, assigning a case number to the output data set, and generating validation instructions based on the assigned case number. An apparatus includes a host machine for receiving the input data set from the testing system and an algorithm for executing DOE to validate the test system. The algorithm applies DOE to the input data set to determine a data set having an optimal class width, assigns a case number to that data set, and generates validation instructions based on the case number. | 05-13-2010 |
20100218045 | DISTRIBUTED RUNTIME DIAGNOSTICS IN HIERARCHICAL PARALLEL ENVIRONMENTS - A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment. | 08-26-2010 |
20100218046 | Method For Testing A Control Apparatus And Test Device - A method is described and represented for testing a control apparatus with a test device, where the control apparatus has at least one state variable and at least one actual functionality that contains a time dependency, and the control apparatus and the test device are connected to each other via a signal interface. | 08-26-2010 |
20100229043 | HARDWARE ACCELERATION FOR A SOFTWARE TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction. | 09-09-2010 |
20100287412 | SOFTWARE RELIABILITY TEST METHOD USING SELECTIVE FAULT ACTIVATION, TEST AREA RESTRICTION METHOD, WORKLOAD GENERATION METHOD AND COMPUTING APPARATUS FOR TESTING SOFTWARE RELIABILITY USING THE SAME - Provided are a software reliability test method using selective fault activation, a test area restriction method, a workload generation method and a computing apparatus for testing software reliability using the same. The software reliability test method registers a test target module. The software reliability test method injects a fault into a fault injection target function when a caller of the fault injection target function is included in the registered module, in a case of calling the fault injection target function. | 11-11-2010 |
20100293413 | PROCESS-WINDOW AWARE DETECTION AND CORRECTION OF LITHOGRAPHIC PRINTING ISSUES AT MASK LEVEL - In one aspect of the invention, a method provides a calibrated critical-failure model for a printing process of a critical feature by virtue of a classification of an optical parameter space according to at least two print-criticality levels. Print failure of a respective critical feature is judged on the basis of a print-failure criterion for the critical feature. The respective print-criticality level is ascertained from test-print-simulation data at a sampling point of a process window for a given point in an optical-parameter space, and from a failure rule. An advantage achieved with the method is that it comprises ascertaining the predefined optical-parameter set from the test-print-simulation data at only one sampling point of the process window, which sampling point is identical for all test patterns. This saves processing time and processing complexity by reducing the number of ascertained optical-parameter sets and their processing in the subsequent scanning and classifying steps. | 11-18-2010 |
20100299561 | SYSTEMS AND METHODS FOR MANAGING TESTING FUNCTIONALITIES - Described herein are systems and methods for managing testing functionalities. One such method includes receiving, from a test tool, data indicative of a user-created test script, being a data-bound test script in the present example. The data-bound test script is created for testing a target application, and is bound to a predetermined data set. This received data is then processed, thereby to define data indicative of an unbound test script. A user interface is provided for allowing a user to associate the unbound test script with one or more data sets selected from a repository of stored data sets. Responsive to a user command, data indicative of a new data-bound test scripts is defined based on the association of the unbound test script with the selected one or more data sets. This new defined data-bound test script is executable via the test tool. For example, instructions are provided to the test tool such that those scripts are executed for the testing of the target application. In some cases, multiple unbound test scripts are effectively bolted together to create more complex scenarios for testing. | 11-25-2010 |
20100306591 | METHOD AND SYSTEM FOR PERFORMING TESTING ON A DATABASE SYSTEM - There is provided a system and method for performing testing on a database system comprising a query optimizer, the query optimizer having an optimizer plan space comprising a plurality of query plans. An exemplary method comprises generating a plurality of queries programmatically according to a template query by varying at least one of an operation, a predicate or a parameter to produce a plurality of query plans. The exemplary method also comprises optimizing the plurality of queries using the query optimizer to collect the plurality of query plans and selecting a subset of queries from the plurality of queries using the query optimizer, the subset of queries comprising queries with distinct query plans that substantially cover the optimizer plan space. The exemplary method additionally comprises executing the subset of queries on the database system to identify an inefficiency of the database system. | 12-02-2010 |
20100332905 | PROGRAM EXECUTION DEVICE AND METHOD FOR CONTROLLING THE SAME - Conventionally, when executing a plurality of programs while being synchronized by a plurality of debuggers, an interface has been required for performing a particular coordination between the debuggers. In the present invention, programs are synchronously executed without coordination between the debuggers by performing a control method including a step for maintaining a program execution state in the debuggers to be different from an actual program execution state, so that the program execution is retained, if necessary, in response to a program execution request from a debugger. | 12-30-2010 |
20110072309 | Debugger for Multicore System - A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for enabling parallel execution of a program that is divided into the basic modules that are executable asynchronously with one another, the program being defined with the execution rule of the basic modules for executing the basic modules in time series, wherein the scheduler includes a break point setting module configured to set a group of break points that are designated through a graphical user interface. | 03-24-2011 |
20110093744 | Distributed Batch Runner - Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test scripts for allocation to a plurality of test machines. A first request for a first test script task may be received from a first test machine of a plurality of test machines. A determination may be made as to whether each test script within the set of test scripts has been allocated. If not, a first unallocated test script to allocate to the first test machine may be determined, and a first test script task may be allocated to the first test machine where the first test script task includes the first unallocated test script. The first unallocated test script then may be identified as an allocated test script in the set of test scripts. | 04-21-2011 |
20110099425 | SYSTEM AND METHOD FOR TESTING GRAPHICS CARD - A system for testing a video memory reliability of a video card includes an input module, a data read/write module, a data processing module, a data comparison module, and an output module. The input module is capable of activating a testing program which includes an original image file. The data read/write module is capable of writing the original image file in the video memory from the testing program, and reading the image file data stored in the video memory during the writing process for storing the read image file data to form a new image file. The data processing module is capable of calculating hash values of the original and new image files using hash function(s). The data comparison module is capable of comparing hash values, and outputting the comparison result. The output module is capable of indicating whether the video card is normal according to the comparison result. | 04-28-2011 |
20110099426 | SYSTEM FOR INJECTING PROTOCOL SPECIFIC ERRORS DURING THE CERTIFICATION OF COMPONENTS IN A STORAGE AREA NETWORK - An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences. | 04-28-2011 |
20110138229 | Automated Testing of Software with Targeting of Deep Paths - A method is provided for generating a test case for testing a program, which can include analyzing instructions of the program to identify basic blocks and superblocks, each basic block containing at least one executable instruction, and each superblock containing a plurality of basic blocks. The method can include executing instructions by a processor to perform determining respective weights of superblocks, each weight representing a number of basic blocks which require execution when the superblock is executed; determining the constraints which cause a superblock having a high weight to be executed, and using the determined constraints to generate a test case which, upon execution of the program, causes the high weight superblock to be executed. | 06-09-2011 |
20110145645 | TEST SYSTEM AND METHOD FOR TESTING ELECTRONIC DEVICES USING A PIPELINED TESTING ARCHITECTURE - A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction. | 06-16-2011 |
20110154112 | DATA STORAGE DEVICE TESTER - A data storage device (DSD) tester is disclosed for testing a DSD. The DSD tester comprises control circuitry operable to receive production line data through an interface, wherein the production line data is related to the DSD. The control circuitry executes a DSD test on the DSD, and transmits failure data generated by the DSD test and the production line data to a failure information database. | 06-23-2011 |
20110154113 | DATA STORAGE DEVICE TESTER - A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises control circuitry operable to receive a DSD log from the DSD, wherein the DSD log comprises at least one entry identifying at least one error condition. A sequence of commands associated with the error condition is executed in order to determine whether the DSD is defective. | 06-23-2011 |
20110173499 | System of Testing Engineered Safety Feature Instruments - The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed. | 07-14-2011 |
20110219266 | System and Method of Testing an Error Correction Module - In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point. | 09-08-2011 |
20110225457 | System for Testing a Multitasking Computation Architecture Based on Communication Data between Processors and Corresponding Test Method - System for testing a multitasking computation architecture, comprising a set of processors linked by data communication channels, comprising a generating stage for generating sequences of test instructions based on characteristics of said processors comprising programming rules for the computation processors, characterized in that it comprises a control stage for the stage for generating sequences based on data representative of the data communication channels. | 09-15-2011 |
20110239048 | PARTIAL FAULT TOLERANT STREAM PROCESSING APPLICATIONS - In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment. | 09-29-2011 |
20110246830 | Creating Virtual Appliances - Techniques for creating a virtual appliance in a virtualization environment are provided. The techniques include implementing a framework, wherein the framework comprises a knowledge representation scheme for describing library knowledge to specify one or more libraries that are used for interaction between two or more appliance components, and using the framework to instrument the one or more libraries via use of the library knowledge, record each of one or more communication parameter values in an original environment, and package one or more disk images, wherein the one or more disk images contain the one or more instrumented libraries, the one or more communication parameter values, and translation logic, to create a virtual appliance. | 10-06-2011 |
20110258490 | Testing Components for Thread Safety - A checking system is described for determining whether a component is thread safe in the course of interacting with two or threads in a client environment. The checking system uses a manual, automatic, or semi-automatic technique to generate a test. The checking system then defines a set of coarse-grained observations for the test, in which the component is assumed to exhibit linearizability when interacting with threads. The set of coarse-grained observations may include both complete and “stuck” histories. The checking system then generates a set of fine-grained observations for the tests; here, the checking system makes no assumptions as to the linearizability of the component. The checking system identifies potential linearizability errors as those entries in the set of fine-grained observations that have no counterpart entries in the set of coarse-grained observations. The checking system may rely on a stateless model checking module to perform its functions. | 10-20-2011 |
20110264959 | PARTIAL RECORDING OF A COMPUTER PROGRAM EXECUTION FOR REPLAY - A method, system and program product for recording a program execution comprising recording processor context for each thread of the program, results of system calls by the program, and memory pages accessed by the program during an execution interval in a checkpoint file. Processor context includes register contents and descriptor entries in a segment descriptor table of the operating system. System calls are recorded for each program thread, tracked by an extension to the operating system kernel and include returned call parameter data. Accessed memory pages are recorded for each program process and include data, libraries and code pages. The program address space, processor context, and program threads are reconstructed from checkpoint data for replaying the program execution in a different operating system environment. | 10-27-2011 |
20110283142 | METHOD AND SYSTEM FOR PERFORMING PARALLEL COMPUTER TASKS - A method and system for performing parallel tasks in a computer system includes invoking a single-threaded operating environment in a computer, invoking under the single-threaded operating environment a first task to be performed by a first processor, invoking under the single-threaded operating environment a second task to be performed by a second processor, while the first task is still being performed, and receiving results from the first and second tasks. | 11-17-2011 |
20110289354 | Distributed Batch Runner - Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test scripts for allocation to a plurality of test machines. A first request for a first test script task may be received from a first test machine of a plurality of test machines. A determination may be made as to whether each test script within the set of test scripts has been allocated. If not, a first unallocated test script to allocate to the first test machine may be determined, and a first test script task may be allocated to the first test machine where the first test script task includes the first unallocated test script. The first unallocated test script then may be identified as an allocated test script in the set of test scripts. | 11-24-2011 |
20110302453 | DEBUG METHOD FOR COMPUTER SYSTEM - A debug method for computer system is disclosed. The method includes the following steps. Firstly, a first index is increased. Next, a first debug data to a j | 12-08-2011 |
20110320872 | HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN - A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined. | 12-29-2011 |
20120131386 | VERIFICATION OF SPECULATIVE EXECUTION - A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths. | 05-24-2012 |
20120137178 | STREAM BASED DEBUGGING TECHNIQUES - Techniques are described for debugging a processing element (or elements) in a stream based database application in a manner that reduces the impact of debugging the processing element (or elements) on the overall running environment by selectively fusing (or un-fusing) processing elements running on a group of compute nodes. In addition to fusing and un-fusing processing elements or otherwise modifying a state of the stream application, a debugging application and stream manager may modify data flows within the application stream in a variety of ways to minimize any disruption resulting from a debugging session. | 05-31-2012 |
20120204062 | DATA RACE DETECTION - The claimed subject matter provides a method for detecting a data race. The method includes inserting a plurality of breakpoints into a corresponding plurality of program locations. Each of the program locations accesses a plurality of memory locations. Each of the program locations is selected randomly. The method also includes detecting one or more data races for the memory locations in response to one or more of the breakpoints firing. Additionally, the method includes generating a report describing the one or more data races. | 08-09-2012 |
20120210171 | COGNITIVE AGENT - Aspects relate to a cognitive agent that performs functions associated with a desired result. The functions performed by cognitive agent supplement other activities performed at a same time. In such a manner, the cognitive agent can function as a surrogate for a user. A performed activity can trigger implementation of another activity that is an extension of the performed activity. Cognitive agent can perform functions that can be represented as an avatar. Further, cognitive agent can be associated with a diagnostics component that evaluates an operating condition. Based on the operating condition cognitive agent can implement automatic actions associated with mitigating failures and/or prolonging the life of machinery. | 08-16-2012 |
20120266024 | PROTOCOL SOFTWARE COMPONENT AND TEST APPARATUS - A particular system includes a processor and a network interface configured to send and receive messages via a network using an asynchronous computer communication protocol. The system may include two or more buffers, such as an ingress buffer and an egress buffer. The system may include a memory accessible to the processor. The memory may include first node instructions that are executable by the processor to implement one or more functions of a first node. The memory may also include one or more script callbacks. The script callbacks may be executable by the processor to at least one of provide: the first content to a test script to be modified before the first content is provided to the first node instructions from the ingress buffer, and provide the second content to the test script to be modified before the outgoing message is provided to the egress buffer. | 10-18-2012 |
20130067281 | TESTING SYSTEM AND METHOD FOR HANDHELD ELECTRONIC DEVICE - A handheld electronic device testing system and a method for testing a handheld electronic device installed with an open operating platform and installed with a test instruction execution program are introduced. The test instruction execution program executes a functional test based on a test instruction received. The testing method involves integrating various test programs with a pre-stored test program library, sending sequentially an instruction to the test instruction execution program with each of the test programs through a transmission line in a scheduled manner, and recording a test result to achieve automated testing. | 03-14-2013 |
20130179735 | CONCURRENT TEST INSTRUMENTATION - A program can be instrumented to test the program. The test instruments are classified, and concurrency constraints applied based on the classifications. A testing tool determines classifications of a plurality of test instruments in the instrumented program. The testing tool prevents concurrent instantiation of multiple of the plurality of test instruments in a first classification of the classifications. Multiple of the plurality of test instruments in a second classification of the classifications are concurrently instantiated. | 07-11-2013 |
20130191689 | FUNCTIONAL TESTING OF A PROCESSOR DESIGN - According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence. | 07-25-2013 |
20130212436 | Method and system for detecting abnormality of network processor - The disclosure discloses a method and a system for detecting an abnormality of a network processor. The method comprises the following steps: an abnormality detection operation code is added into an execution flow of each thread in a network processor, and the network processor sets a flag bit corresponding to a current thread in an abnormality protection flag data area in a shared memory to a first flag when executing the abnormality detection operation code in the current thread; and when a period of a timer is expire, a coprocessor detects all the flag bits in the abnormality protection flag data area in the shared memory, determines that a thread corresponding to a flag bit which is not the first flag is abnormal when detecting that not all the flag bits are the first flag, and sets all the flag bits to a second flag when detecting that all the flag bits are the first flag. Through the disclosure, the abnormality of a thread can be detected timely and efficiently, so that the failure detection capability of the network device using the network processor as a core unit at run time is improved without influencing the forwarding performance and service processing flow of the network processor. | 08-15-2013 |
20130238936 | PARTIAL FAULT TOLERANT STREAM PROCESSING APPLICATIONS - In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment. | 09-12-2013 |
20130254595 | COMMUNICATION SYSTEM AND TEST APPARATUS - An instruction is assuredly transmitted. A test apparatus that tests a device under test, includes a test unit that tests a device under test by exchanging a signal with the device under test, a control apparatus that controls the test unit; and a relay apparatus that relays communication between the test unit and the control apparatus, where the control apparatus transmits an instruction to be given to the test unit a plurality of times to the test unit, and the test unit receives the instruction transmitted the plurality of times from the control apparatus, and executes the instruction once. | 09-26-2013 |
20130305090 | TEST CONFIGURATION RESOURCE MANAGER - A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion of the first test configuration as a test configuration resource in a library of test configuration resources, receive a user input identifying a stored test configuration resource, retrieve the identified stored test configuration resource, and incorporate the retrieved test configuration resource into a second test configuration. The library of test configuration resources may include one or more of port resources, protocol resources, and traffic resources. | 11-14-2013 |
20130305091 | DRAG AND DROP NETWORK TOPOLOGY EDITOR FOR GENERATING NETWORK TEST CONFIGURATIONS - There is disclosed a method and apparatus for editing test configurations. The method includes displaying a graphical representation of a test configuration to be tested by a test system on a user interface and receiving user input identifying network topology to be added to the test configuration, the network topology including a device group defined by a number of emulated traffic sources, a set of protocols and a number of ports. The method further includes updating the graphical representation of the test configuration to include the network topology; the graphical representation of the network topology including graphical representations of the test system, the emulated traffic sources, the set of protocols, and the number of ports connecting the emulated traffic sources to the test system. | 11-14-2013 |
20140136898 | Run-Time Default Detection in a Component Associated with an Application Programming Interface Platform - Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been invoked to process a transaction. A forward progress counter is monitored to determine whether the component is processing the transaction, wherein the forward progress counter increments at determined intervals when the component is processing the transaction. A test transaction is executed for the component when a determination is made that the forward progress counter has not incremented for a threshold fault period. A fault alarm indicator is generated based on the determination that the forward progress counter has not incremented for the threshold fault period. | 05-15-2014 |
20140143600 | DEBUGGING IN A SEMICONDUCTOR DEVICE TEST ENVIRONMENT - A test system that enables real-time interactive debugging of a device under test (DUT) using native customer code. A translation module may format, in real time, debug commands, corresponding to a user input, into a format recognizable by instruments in a tester. The user input may be a test program or test instructions written in a high-level programming language. The translation module may translate the user's debug commands into lower-level test instrument commands, based on which the tester may apply control signals to a processor in the DUT to test subsystems of the DUT. A result of the test may be provided to the translation module, which may, in real time, format another debug command, or provide an indication of the result to the user. The translation module may thus enable a user to step-through and modify native customer code in an interactive manner to debug a DUT. | 05-22-2014 |
20140250329 | SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices. | 09-04-2014 |
20150339177 | PROCESSING DEVICE AND METHOD OF EXECUTING AN INSTRUCTION SEQUENCE - A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words. | 11-26-2015 |
20160092332 | CONTROLLING A BYTE CODE TRANSFORMER ON DETECTION OF COMPLETION OF AN ASYNCHRONOUS COMMAND - Controlling a byte code transformer on detection of completion of an asynchronous command. An asynchronous command is received by an asynchronous manager from a test framework. The asynchronous command manager issues the asynchronous command to an application. A transformer is loaded for transforming byte code associated with the application in order to output one or more method names and associated timestamps of one or more method entry points and one or more method exit points. A check is made as to whether an expected result has been generated by the application. In response to determining that an expected result has been successfully generated, a time period associated with successful generation of the expected result is compared with the timestamps in order to determine matching timestamps and associated matching method names. The transformer is modified in accordance with the matching method names such that a subsequent transformation executes on byte code associated with the matching method names. | 03-31-2016 |