Class / Patent application number | Description | Number of patent applications / Date published |
714034000 | Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) | 32 |
20080276126 | Methods and Apparatus for Measuring Performance in Processing System - Techniques are disclosed for measuring performance in processing systems such as communications systems and computing systems. For example, a method of measuring performance in a processing system having a plurality of processing devices includes the following steps. A measurement system coupled to the plurality of processing devices generates an interrupt signal. The measurement system applies the interrupt signal to a set of processing devices under test, wherein the set of processing devices under test is selected from the plurality of processing devices, such that each processing device of the set under test makes data available to the measurement system. The available data represents data associated with the execution of at least one function performed by each processing device of the set under test. The measurement system obtains the available data and utilizes at least a portion of the available data to determine a measure of performance associated with each of the processing devices of the set under test. | 11-06-2008 |
20080288823 | JTAG Interface - Implementations are presented herein that relate to improved Joint Test Action Group (JTAG) compatible devices. | 11-20-2008 |
20090006894 | METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN - An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software. | 01-01-2009 |
20090083580 | Techniques for Background Testing a Hard Disk Drive - A technique for background testing a hard disk drive, when an associated system is powered and the hard disk drive is available, includes receiving an interrupt test indication that indicates that the background testing of the hard disk drive is to be interrupted. The technique also includes discontinuing, at a current test location, the background testing of the hard disk drive in response to the interrupt test indication. Finally, current test results are saved in response to the interrupt test indication. | 03-26-2009 |
20090217095 | MEANS AND METHOD FOR DEBUGGING - A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register. | 08-27-2009 |
20090249122 | DEBUGGER AND DEBUGGING METHOD - A debugger includes: a break detecting circuit which, when the state of a microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of the microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of the predetermined signal; and, an execution control circuit which, when the trigger request signal has been transmitted, outputs a trigger signal for observing the predetermined signal by means of a logic analyzer and outputs a break signal for causing the microprocessor core to transition to the debug state. | 10-01-2009 |
20090265581 | Data system having a variable clock pulse rate - A data processing system includes an execution unit operating in a clocked manner, a clock pulse generator for delivering a clock signal for the execution unit, and a monitoring unit for monitoring the regular operation of the execution unit. The clock pulse generator is configured for delivering the clock signal having a controllable frequency. The monitoring unit is functionally connected to the clock pulse generator in order to reduce the frequency of the clock signal when irregular operation of the execution unit is detected. | 10-22-2009 |
20100064174 | Data processing system and debug method - An exemplary aspect of the present invention is a data processing system, including a function block that operates based on a clock, a clock supply control circuit that controls supply of the clock based on an enable signal, a storing part that stores a command table in which a debug command and a number of clocks needed to process the debug command by the function block are made correspondent to each other, and a debug system part that executes debug processing based on an input debug command, in which the debug system part refers to the command table and outputs the enable signal in accordance with the number of clocks corresponding to the input debug command. | 03-11-2010 |
20110072308 | ELECTRONIC DEVICE AND METHOD FOR TESTING SERIAL SIGNALS - An electronic device includes a serial signal test system to test serial signals generated by a serial signal generator. A test method tests serial signals using the electronic device. The test method sets test parameters that tests serial signals. Furthermore, the test method identifies an error bit from coded bits of each of the serial signals, and identifies abnormal attribute data of each of the serial signals. In addition, the test method generates a test report according to all identified error bits and abnormal attribute data. | 03-24-2011 |
20110131452 | Validation of Processors Using a Self-Generating Test Case Framework - A method for testing processors is disclosed. The method includes generating a plurality of pools, where each pool includes a test program that includes a plurality of test cases, and setting a flag for each of the plurality of pools indicating that the pool is ready to be executed. Each processor performs a pool execution cycle a predetermined number of times. The pool execution cycle includes selecting a pool that is ready to be executed and unsetting the flag for the selected pool, performing an execution cycle of the test program included in the selected pool, and setting the flag indicating that the pool is ready to be executed upon completion of the execution cycle of the test program. The execution cycle of the test program includes regenerating a test case to create a new case that is flagged as the next test case for execution in the execution cycle. | 06-02-2011 |
20110145644 | PROTOCOL SEQUENCE GENERATOR - A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells. | 06-16-2011 |
20110154111 | Memory Based Hardware Breakpoints - A mechanism is provided for managing hardware breakpoints within a computing environment comprising a processor and a memory unit with addressable words being extended using metadata. A setting or deleting of a breakpoint is issued at a specific address within the memory unit by forwarding from the processor to the memory unit the metadata. An addressable word is requested from the memory unit by forwarding a physical address of the addressable word via an address bus from the processor to the memory unit. The physical address is decoded to find the addressable word within the memory unit. Responsive to the metadata associated with the addressable word being available, the metadata is provided to the processor. A checking is made as to whether a breakpoint is set in the metadata. Responsive to the breakpoint being found in the metadata, an interrupt is triggered thereby executing the breakpoint. | 06-23-2011 |
20110161736 | Debugging module to load error decoding logic from firmware and to execute logic in response to an error - A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error. | 06-30-2011 |
20110264958 | TEST FRAMEWORK FOR A NOTEBOOK COMPUTER - The disclosed simplified test framework comprises a first module substituting the mobile network module of the computer to communicate with a mobile phone network, configured with signal pins of VCC connected to a voltage of +3V, RST, VPP, CLK, and DATA while enabling the VCC to power source; and a second module substituting the subscriber identity module of the computer to identify a subscriber's identity on the computer, configured with signal pins of VCC, GND, RST, VPP, CLK, and DATA; wherein the VCC, RST, CLK, and DATA of the first module is connected to those of the second module, respectively, a light emitting diode connects the VCC and RST of the second module, the RST and CLK of the first module are connected to each other, an impedance connects the CLK and DATA of the second module, and the DATA is connected to an electric ground. | 10-27-2011 |
20110302452 | CIRCUITRY TO FACILITATE TESTING OF SERIAL INTERFACES - Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data. | 12-08-2011 |
20120110383 | Method and apparatus for off-line analyzing crashed programs - In a method for off-line analyzing crashed programs, a simulator of a debugger is made to enter into a running state, and set breakpoints in the running state. Register and memory signals are separated from a dump signal outputted by a platform during crash. The debugger is used to replace, at the breakpoints, register and memory signals of the simulator originally in the running state with the register and memory signals separated from the dump signal. A debugging signal in the running state is replaced with a debugging signal during crash. The debugger is used to analyze reasons of crash based on the debugging, register, and memory signals after replacement. By separating the register and memory signals from the dump signals outputted by the platform during crash without involving any OS signal, there is no need to modify the platform and the GDB debugger when analyzing the reasons of crash. | 05-03-2012 |
20120144240 | DEBUG STATE MACHINE AND PROCESSOR INCLUDING THE SAME - A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs. | 06-07-2012 |
20120151264 | Debug Registers for Halting Processor Cores after Reset or Power Off - A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal. | 06-14-2012 |
20120254666 | PASS-BY BREAKPOINT SETTING AND DEBUGGING METHOD AND DEVICE - A method and device for pass-by breakpoint setting and debugging are disclosed. The pass-by breakpoint setting method comprises: receiving a breakpoint setting command; determining an instruction at a breakpoint in a source program code according to the breakpoint setting command; if one of the instruction at the breakpoint and an instruction prior to the instruction at the breakpoint is a relative jump instruction, setting an instruction duplicate, and setting the instruction at the breakpoint in the source program code as a first abnormal instruction. Accordingly, the memory space occupied by the duplicate can be reduced. | 10-04-2012 |
20120272100 | PROGRAMMABLE ACTIVE THERMAL CONTROL - Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test. | 10-25-2012 |
20120304010 | CODE COVERAGE-BASED TAINT PERIMETER DETECTION - A code coverage-based taint perimeter detection system and method for testing software code by determining code coverage and detecting new coverage of the code. Embodiments of the system and method perform tainted data flow analysis on execution traces of the code to determine tainted branch targets. The tainted branch targets may be filtered to remove any tainted branch targets that have already been covered. New coverage can be determined by monitoring the filtered tainted branch targets, which in some embodiments involves the use of software breakpoints that are automatically placed at the locations in the tainted branch targets at runtime. Embodiments of the system and method use an iterative process to ensure that only tainted branch targets that have not already been covered or tested are examined. | 11-29-2012 |
20120324290 | Key Based Cluster Log Coalescing - An approach is provided to trace a software program running in a multi-nodal complex computing environment. A trace request is sent from a requestor node to the nodes with the trace request associated with the software program and also associated with a transaction identifier. The software program is executed on the nodes. While the program is executing, trace data entries resulting from the execution of the software program are logged at the respective nodes with each trace data entry being associated with the transaction identifier. A log request is subsequently sent from the requestor node to the other nodes. The resulting trace data is then received by the requestor node from the target nodes and logged in a transaction based log. The transaction-based log is then provided to a user of the requestor node. | 12-20-2012 |
20130007525 | TEST ARCHITECTURE BASED ON INTELLIGENT TEST SEQUENCE - A method, data processing system, and computer program product for testing a computer system. A sequencer tests the computer system using test modules arranged in a first sequence, wherein each of the test modules is for testing at least a portion of the computer system. The sequencer determines if an operator is available, in response to an interrupt generated by a test module. If an operator is available, the sequencer arranges the test modules into a second sequence based on a first policy. If an operator is unavailable, the sequencer arranges the test modules into a third sequence based on a second policy. | 01-03-2013 |
20130091384 | SYSTEM AND METHOD FOR MEASURING THE EFFECT OF INTERRUPTIONS ON SOFTWARE APPLICATION USABILITY - An exemplary embodiment of the present techniques may request a user to execute a task using a software application under test. An interruption may be generated that interrupts the user while the user is attempting to complete the task, and measuring an effect of the interruption on the ability of the user to successfully complete the task. | 04-11-2013 |
20130159775 | Debug Registers for Halting Processor Cores after Reset or Power Off - A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal. | 06-20-2013 |
20140082421 | CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TESTING OF AN INTEGRATED CIRCUIT - A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module. | 03-20-2014 |
20140208162 | GENERATION OF SIMULATED ERRORS FOR HIGH-LEVEL SYSTEM VALIDATION - A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation. | 07-24-2014 |
20140281722 | DEBUGGING PROCESSOR HANG SITUATIONS USING AN EXTERNAL PIN - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 09-18-2014 |
20140344621 | DIAGNOSING CODE USING SINGLE STEP EXECUTION - A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. | 11-20-2014 |
20150095705 | Instruction and Logic for Machine Checking Communication - A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank. | 04-02-2015 |
20160062863 | MULTICORE PROCESSOR SYSTEM HAVING AN ERROR ANALYSIS FUNCTION - A method for operating a multi-core processor system, wherein different of a program are each executed simultaneously by a different respective processor core of the multi-core processor system includes inserting a breakpoint in a first of the threads for interrupting the first processor core and instead executing an exception handling routine. At least one processor core to be additionally interrupted is determined with the exception handling routine on the basis of an association matrix, and an inter-processor interrupt (IPI) is sent to the at least one processor core by the exception handling routine in order to interrupt the at least one processor core. | 03-03-2016 |
20160147588 | CONTROL MECHANISM BASED ON TIMING INFORMATION - There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range. | 05-26-2016 |