Class / Patent application number | Description | Number of patent applications / Date published |
714028000 | Substituted emulative component (e.g., emulator microprocessor) | 37 |
20080222453 | METHOD FOR INTEGRATING EVENT-RELATED INFORMATION AND TRACE INFORMATION - A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed. | 09-11-2008 |
20080282109 | Debugging system and debugging method - A debugging system includes an emulator connected via a communication line for two-way communication and a target device to be debugged by the emulator. The emulator includes a serial signal transmitting unit to transmit a control signal as serial data to the target device and an A/D converter to convert an analog signal into a digital signal and to output the digital signal, the analog signal is input from the target device via the communication line. The target device includes a trace circuit, a serial signal receiving unit to receive the serial data and a D/A converter to convert, in response to the control signal received, trace information into an analog signal, and to output the analog signal, the trace information is output by the trace circuit. | 11-13-2008 |
20090083578 | METHOD OF TESTING SERVER SIDE OBJECTS - There is disclosed a method and system of testing server side objects in a client-server environment. A proxy is created of a first object on a server side on a client side. The proxy invokes a method of the first object on the server side to conduct a test by a test case deployed on the client side. A proxy is created of a second object on the client side by the proxy of the first object by the process of invoking the method of the first object on the server side. The creation of the proxies and objects are performed recursively. | 03-26-2009 |
20090106590 | SERVICE AND DIAGNOSTIC LOGIC SCAN APPARATUS AND METHOD - A diagnostic and service logic program for a programmable logic controller (PLC) is provided in parallel with the main machine logic program. The diagnostic and service logic program has the same functionality as the main machine logic program, but can be modified and operated independently of the main machine logic program for testing and debugging a faulty main machine logic program. The PLC can be switched between programs for testing and debugging. | 04-23-2009 |
20100100767 | AUTOMATICALLY CONNECTING REMOTE NETWORK EQUIPMENT THROUGH A GRAPHICAL USER INTERFACE - Embodiments of the present invention provide a method and system for designing a test network in an integrated application, and configuring remote network devices through a network design application to test a network design. One embodiment of the present claimed subject matter is provided as a system for automatically configuring remote network devices to simulate a network connection. The system includes a plurality of computing devices which are physically coupled to one or more network devices, wherein the network devices are automatically configured to comprise a test network corresponding to a remote test network topology design. | 04-22-2010 |
20110113285 | SYSTEM AND METHOD FOR DEBUGGING MEMORY CONSISTENCY MODELS - A system and method for analyzing a test program with respect to a memory model includes preprocessing a test program into an intermediate form and translating the intermediate form of the test program into a relational logic representation. The relational logic representation is combined with a memory model to produce a legality formula. A set of bounds are computed on a space to be searched for the memory model or on a core of the legality formula. A relational satisfiability problem is solved, which is defined by the legality formula and the set of bounds to determine a legal trace of the test program or debug the memory model. | 05-12-2011 |
20110258489 | TEST SYSTEM WITH DIGITAL CALIBRATION GENERATOR - The present invention relates to calibration of a computerized test system ( | 10-20-2011 |
20110307739 | MULTIMEDIA HARDWARE EMULATION FOR APPLICATION TESTING - A multimedia testing system is described herein that uses a virtual hardware driver to test software application behavior using virtual hardware in place of physical hardware devices. The virtual hardware driver receives customized input patterns that emulate behavior and formatting of data from a wide variety of hardware devices. For webcams, the system can send a steady stream of frames like those that would be provided as output from a physical webcam. A test environment can observe software interaction with the received customized input patterns to determine how the software will interact with various physical hardware devices. Thus, the multimedia testing system allows automated testing of a software application that interacts with multimedia hardware without physically buying and installing hardware devices. | 12-15-2011 |
20120066548 | Automated Operating System Test Framework - A method of automating testing of a first computing system comprises identifying a plurality of system interface elements of a second computing system; determining an untested state at the first computing system of one of the identified plurality of system interface elements; determining the existence of any dependency of the one of the identified plurality of system interface elements upon another of the identified plurality of system interface elements; responsive to a finding of no the dependency, seeking in a repository a system interface element test corresponding to the one of the identified plurality of system interface elements and having an expected output according to a structure of the second computing system; and executing the system interlace element test at the first computing system. | 03-15-2012 |
20120173928 | Analyzing Simulated Operation Of A Computer - Analyzing simulated operation of a computer including loading user-defined dynamically linked analysis libraries that each include specifications of events to be traced for analysis, including: executing, in separate hardware threads, one trace buffer handler for each analysis library, and associating, with each trace buffer handler, one or more analysis functions; translating static binary instructions for the simulated computer into binary instructions for the executing computer, including: inserting, into the translation, implementing code for each specification of an event to be traced and inserting, into the translation for each static instruction, a memory address of a separate static instruction buffer; executing the translation, including executing the implementing code and generating, in a trace buffer, one or more trace records for each specified event; and processing the trace buffer, including calling analysis functions and associating by the analysis functions through the separate static instruction buffers event analysis data with static instructions. | 07-05-2012 |
20120254660 | PROCESSING TEST CASES FOR APPLICATIONS TO BE TESTED - The present invention discloses a method and system for processing test cases for applications to be tested. The method includes evaluating two applications to be tested; obtaining test cases for the two applications to be tested and determining resources and execution times needed by the test cases for the two applications to be tested. According to the compatibility relationship between the two applications to be tested, and the resources and execution times needed by the test cases for the two applications to be tested, the test cases for the two applications to be tested are clustered to a virtual machine instance to test the test cases for the two applications to be tested on the virtual machine instance. | 10-04-2012 |
20120331344 | Quasi Disk Drive for Testing Disk Interface Performance - Embodiments of the invention relate to diagnostic evaluation of hardware components of a computer machine. A conventional storage device is replaced with a modified storage device. Read and write operations are received by the modified storage device. Issuance of a response to the read and write operations is limited to an acknowledgement receipt, which is employed to evaluate performance and/or bandwidth of the machines with respect to hardware for data storage. | 12-27-2012 |
20130055022 | FLEXIBLE SOC DESIGN VERIFICATION ENVIRONMENT - A system and method of various SoC design verification techniques. A model of an SoC design is simulated in an emulator, and the emulator is connected to a debugger. Scripts are conveyed from a host computer to the debugger. The debugger translates the commands in the scripts from a first language into commands in a second language. The debugger then conveys the commands in the second language to the emulator. The debugger is also configured to utilize the same scripts to perform tests on an actual SoC on a development board. | 02-28-2013 |
20130124919 | End User Remote Enterprise Application Software Testing - A system and method for remote testing of enterprise software applications (ESA) allows one or more testers to remotely access an ESA and remotely test the ESA. In at least one embodiment, the ESA resides in a testing platform that includes one more computers that are provisioned for testing. “Provisioning” a computer system (such as one or more servers) refers to preparing, configuring, and equipping the computer system to provide services to one or more users. In at least one embodiment, the computer system is provisioned to create an ESA operational environment in accordance with a virtual desktop infrastructure (VDI) template interacting with virtualization software. | 05-16-2013 |
20130262931 | SYSTEMS AND/OR METHODS FOR TESTING CLIENT REACTIONS TO SIMULATED DISRUPTIONS - Certain example embodiments described herein relate to approaches for testing client reactions to simulated disruptions in a real production environment that leverages the publish/subscribe messaging model (or one of its variants), optionally in connection with JMS messages and/or triggers. In certain example embodiments, a test driver reads a script that includes an instruction flow that brings down brokers in a broker cluster similar to (or in a manner as inflicted by) broker crashes (e.g., where a process or application does not have a chance to save its state or data before it is terminated), and/or broker stop/start events, e.g., to simulate the problems and determine whether the client application remains intact in the presence of errors. The simulations may leverage hardware and/or software means for intentionally causing disruptions in a live production environment. Thus, it advantageously becomes possible to test an application integration's client-side failover and/or load-balancing implementations. | 10-03-2013 |
20130346799 | GENERATION OF SIMULATED ERRORS FOR HIGH-LEVEL SYSTEM VALIDATION - Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test. | 12-26-2013 |
20140095931 | Method and system for automating the process of testing a device - Device Test Automation framework. This embodiment provides a device test automation framework for automating testing of embedded systems. The device test automation framework—DTAF allows user to test embedded device software using test scripts, which can capture various interfaces of device under test. A Graphical User Interface—GUI tool is created based on device under test configuration and user input. This GUI tool shows various interface of device under test. A device test automation framework hardware enables communication between test tool and the device under test. DTAF allows testing process to dramatically improve productivity, effectiveness, efficiency and coverage of embedded software testing | 04-03-2014 |
20140108865 | FAULT SUPPORT IN AN EMULATION ENVIRONMENT - An emulator is disclosed that allows for diagnoses of failures or defects within the emulator. A map of faulty resources is generated to identify which resources should be avoided during compilation. Thus, in a transparent and automated manner, defects found during diagnostics are stored in a database of unusable emulator resources. A compiler has access to the database and compiles the design taking into account unusable resources. In another embodiment, the defects of an emulator board are stored on the emulator board itself. This allows each board to store its own maintenance information that can be used at the manufacturing site for changing defective chips. Defects stored on the board itself allow the defects to be obtained independent of a position of a board within the emulator to simplify identification of the faulty resource. | 04-17-2014 |
20140157050 | TEST SYSTEM AND TEST METHOD BY GENERATING VIRTUAL TEST UNIT OUTSIDE DEVICE TO BE TESTED - A test system and a test method by generating a virtual test unit outside a device to be tested are provided, where a virtual test unit is generated outside a device to be tested, and the virtual test unit executes test tools according to a test script, so as to test the device to be tested. Through such a technical means, overall performance of the device to be tested and including multiple entities can be tested, and a technical efficacy of expanding an application scope of an existing test model can be achieved. | 06-05-2014 |
20140215269 | TEST INFRASTRUCTURE SIMULATION - Systems, methods, and machine-readable and executable instructions are provided for operating a test infrastructure simulation. Operating a test infrastructure simulation can include executing a test on a number of units under test (UUT) coupled to a test infrastructure and determining capabilities of the test infrastructure based on results of the test executed on the number of UUTs coupled to the test infrastructure. | 07-31-2014 |
20140258779 | Communication Analyzer - Descriptions of communication interactions can be used to create a simulation of actual systems that send and receive communications including but not limited to messages complying with a protocol, events and so on. The communication interaction, event, state and state transitions of protocol or software components can be modeled to determine outcome and to validate the format and semantics of events, interaction values, etc. to identify variances against established policies or architectural guidelines. | 09-11-2014 |
20140281715 | METHOD AND APPARATUS FOR SCALING NETWORK SIMULATION - Embodiments disclosed herein enable network simulation including a range of networking technologies to be scaled to include large numbers of devices under test (DUTs) even though computing resources, such as a total number of simulation hosts or IP addresses, may be limited. By enabling a network simulator to scale with limited computing resources, developers may be enabled to reduce the requirements for physical space, power, cost, and maintenance for network simulation. For example, developers may be able to determine capacity, such as a total number of DUTs that a network management system (NMS) is capable of managing, even though few simulation hosts or IP addresses may be available for simulation of the DUTs. | 09-18-2014 |
20150121138 | METHOD AND APPARATUS FOR EMULATION AND PROTOTYPING WITH VARIABLE CYCLE SPEED - A hardware verification system includes, in part, a multitude of programmable devices and a system clock. The hardware verification system receives a circuit design and generates a variable period clock from the system clock by analyzing propagation delays in different signal paths of the circuit design. The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, in which M>N. The variable period clock is applied to at least one of the programmable devices to verify the circuit design. | 04-30-2015 |
20150293825 | TEST DEVICE AND OPERATING METHOD THEREOF - A test device includes a circuit modelling portion suitable for generating one or more model circuits by modelling a test-object circuit with a one-to-one or a one-to-multi relationship between the test-object circuit and the model circuits, and a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits. | 10-15-2015 |
20160062861 | METHOD FOR CONNECTING AN INPUT/OUTPUT INTERFACE OF A TESTING DEVICE EQUIPPED FOR TESTING A CONTROL UNIT - A method for connecting an input/output interface of a testing device equipped for testing a control unit to a model of a technical system present in the testing device. The interface connects the control unit to be tested or connects a technical system to be controlled, and the model to be connected to the input/output interface is a model of the technical system to be controlled or a model of the control unit to be tested. The testing device has a plurality of input/output functions connected to the model. The method has provides an interface hierarchy structure and a function hierarchy structure. The method has an automatic configuration of compatible connections between the interface hierarchy structure and the function hierarchy structure so that the model present in the testing device communicates through at least a part of the compatible connections with the control unit to be tested or the technical system to be controlled. | 03-03-2016 |
20160124824 | METHOD FOR MEASURING THE EFFECT OF MICROSCOPIC HARDWARE FAULTS IN HIGH-COMPLEXITY APPLICATIONS IMPLEMENTED IN A HARDWARE ELECTRONIC SYSTEM, AND CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT - A method for measuring the effect of microscopic hardware faults in high-complexity applications includes carrying out on a processing system a step of simulation of an electronic system that executes a software instance of the application. The simulation step includes injecting faults at a microscopic level and measuring a corresponding final effect. The operation of injecting faults includes selecting a microscopic fault to be injected, selecting a mutant corresponding to the microscopic fault, applying the selected mutant to the software instance to obtain a mutated instance, simulating the electronic system that executes the mutated instance, and measuring the corresponding effect. | 05-05-2016 |
20160132373 | SYSTEM ANALYSIS DEVICE, SYSTEM ANALYSIS METHOD AND SYSTEM ANALYSIS PROGRAM - A system analysis device | 05-12-2016 |
20160132414 | SIMULATION DEVICE AND DISTRIBUTION SIMULATION SYSTEM - A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus. | 05-12-2016 |
20160132424 | SIMULATING SENSORS - Simulating sensors can include hooking an application associated with sensory data and associating the sensory data with an automation instruction. Simulating sensors can include providing the sensory data to a support device having an ability to modify the application and automatically causing the support device to simulate a sensory input using the sensory data by executing the automation instruction. | 05-12-2016 |
714029000 | Memory emulator feature | 8 |
20090049339 | Programmable Diagnostic Memory Module - A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation. | 02-19-2009 |
20090100295 | RELIABLE MEMORY MODULE TESTING AND MANUFACTURING METHOD - A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells. | 04-16-2009 |
20100223502 | MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT - A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration. | 09-02-2010 |
20110119529 | VIRTUAL HARD DISK DRIVE - A virtual hard disk drive includes at least one test transmission interface and a processing unit, wherein the test transmission interface is used for electrically connecting with the processing unit. The test transmission interface can electrically connect with a transmission interface under test of a computer. The processing unit includes an obtaining module and a simulation module. When an access instruction is received through the test transmission interface from the transmission interface under test of the computer, the obtaining module obtains a number of accessed blocks from the access instruction. The simulation module simulates a step of accessing a set of accessed data with the number of accessed blocks with respect to the transmission interface under test via the test transmission interface. | 05-19-2011 |
20130179733 | Cost effective use of simulated storage in a storage subsystem test environment - A data receiver module receives, at a storage device simulator, a data transmission from a storage controller being tested. The data transmission includes data and metadata. The metadata is associated with the data. A signature receiver module receives a signature from the storage controller as part of the data transmission. The signature is used to distinguish the metadata from the data. A data/metadata determination module examines the data transmission and determines data from metadata using the signature. A metadata storage module stores the metadata of the data transmission on the storage device simulator in response to the data transmission including metadata. The data storage simulator includes a data storage device. A data discard module discards the data of the data transmission in response to the data transmission including data. | 07-11-2013 |
20140215270 | METHOD FOR MANIPULATING A MEMORY OPERATION OF A CONTROL UNIT PROGRAM ON A VIRTUAL OR REAL MEMORY - A method for manipulating a memory operation of a control unit program on a memory of a virtual or real electronic control unit (ECU), such as is used in vehicles, for example. The manipulation of the memory operation is accomplished by a memory manipulation program component, via which a set of manipulation functions is provided, from which at least one manipulation function is selected, so that this function, by activating the memory manipulation program component, changes a memory access initiated by the control unit program in accordance with the selected manipulation function during execution of the control unit program. | 07-31-2014 |
20150121139 | PROVIDING BUS RESILIENCY IN A HYBRID MEMORY SYSTEM - In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error. | 04-30-2015 |
20160117233 | Quasi Disk Drive For Testing Disk Interface Performance - Embodiments relate to diagnostic evaluation of hardware components of a computer machine. A conventional storage device is replaced with a modified storage device. Read and write operations are received by the modified storage device. Issuance of a response to the read and write operations is limited to an acknowledgement receipt, which is employed to evaluate performance and/or bandwidth of the machines with respect to hardware for data storage. | 04-28-2016 |