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Subclass of:

714 - Error detection/correction and fault detection/recovery


714001000 - Reliability and availability

714025000 - Fault locating (i.e., diagnosis or testing)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
714030000 Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) 75
714028000 Substituted emulative component (e.g., emulator microprocessor) 18
714031000 Additional processor for in-system fault locating (e.g., distributed diagnosis program) 16
20130031410METHOD AND SYSTEM FOR REMOTE DIAGNOSTICS - Diagnostic apparatus for computers, including a diagnoser that connects to a PC, including an SD connector for connecting the diagnoser to an SD port of a PC, a storage medium for storing diagnostic program code that automatically runs on the PC via the SD connector, in response to connecting the diagnoser to the SD port of the PC, wherein the diagnostic program code performs specific diagnostic tests on the PC in response to input instructions, and generates test results as output, a modem for receiving input instructions from a remote online help-desk facility, specifying which diagnostic tests the diagnostic program code should perform on the PC, and for transmitting the test results to the help-desk facility, and a processor for controlling the storage medium and the modem.01-31-2013
20130031409DEVICE AND METHOD FOR TESTING A MEMORY OF AN ELECTRIC TOOL - The device for testing a memory of an electric tool has a memory, a control unit for controlling the electric tool and a testing module. The memory has a plurality of memory cells for storing data, a first interface and a second interface that is independent of the first interface. The control unit is coupled to the memory via the first interface. The testing module is configured for testing the memory cells of the memory and for this purpose, it is coupled to the memory via the second interface. A tool and method are also provided.01-31-2013
20130031408DEVICE AND METHOD FOR TESTING A MEMORY OF AN ELECTRIC TOOL - The device for testing a memory of an electric tool has a control unit, a testing module, a buffer memory and an address translator. The control unit is coupled to the memory and configured to control the electric tool. The testing module is coupled to the memory and configured to test a specific memory cell from among a plurality of memory cells of the memory. The buffer memory is configured to provide temporary storage of the data that is stored in the specific memory cell during the testing of the specific memory cell. The address translator is configured to translate the address of the specific memory cell to the address of the buffer memory during the testing of the specific memory cell. A tool and method are also provided.01-31-2013
20110191632SMALL FORM FACTOR PLUGGABLE (SFP) CHECKING DEVICE FOR READING FROM AND DETERMINING TYPE OF INSERTED SFP TRANSCEIVER MODULE OR OTHER OPTICAL DEVICE - A SFP checking device (SFP Check) connects to a SFP transceiver and a PC or laptop via a USB cable. The SFP Check uses the default web browser of the PC, without an internet connection, to display details of the SFP transceiver such as wavelength, description, range, manufacturer, among other information, in accordance with program code provided to the PC via the SFP Check. All of the information a technician in the field needs to determine which SFP transceiver is the right one for a selected application and optical link is available from the SFP Check. The SFP Check and SFP transceiver both receive power via the USB cable connection to the PC. The SFP Check appears to the PC as a memory stick. A method is provided for determining the drive letter associated with the SFP Check and the program coder or file(s) it provides to the PC.08-04-2011
20110202799PROCESS FOR MAKING AN ELECTRIC TESTING OF ELECTRONIC DEVICES - The disclosure relates to a process for making an electric testing of electronic devices DUT, of the type comprising the steps of: connecting at least one electronic device DUT to an automatic testing apparatus or ATE apparatus suitable for making the testing of digital circuits; sending, through said ATE apparatus, control signals for the electric testing to said electronic device DUT. Advantageously, the process also comprises the steps of: making the electric testing of said electronic device DUT through at least one reconfigurable digital interface RDI connected to said ATE apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information; and sending from said electronic device DUT to said ATE apparatus response messages, if any, containing measures, failure information and data in response to said control signals and through said digital communication channel.08-18-2011
20110202798REMOTE TECHNICAL SUPPORT EMPLOYING A CONFIGURABLE EXECUTABLE APPLICATION - In a remote technical support system, in response to a request for service, a user device receives an executable application from the technical support controller, which executable application is subsequently invoked at the user device. Additionally, the user device receives configuration information from the technical support controller. The executable application then performs technical support processing of the user device in accordance with the configuration information. The executable application can be configured, based on the configuration information, to engage in dynamic workflow, i.e., to make decisions about what activities to perform based on previous results. Because the configuration information can be selected according to the specific nature of the user device and/or the specific nature of the service request, the executable application can be tailored to best address the requesting end user's needs with minimal attention from a remote technician.08-18-2011
20130042143Circuit Arrangement and Method for Testing Same - The invention relates to a circuit arrangement and to a method for testing same. A circuit arrangement is provided that includes a plurality of functional units which are coupled by at least one streaming data bus. Each of the functional units includes a plurality of hardware modules and a switch matrix. At least one of the streaming data busses is provided with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement. The switch matrices are configurable to establish a streaming data path between and through the plurality of functional units which is used as a test link for any of the hardware modules of the circuit arrangement. The invention provides for non-intrusive real-time tracing in SoCs with a minimum of additional hardware resources and at low cost in terms of die size and power consumption.02-14-2013
20130139001ONLINE DEBUG SYSTEM AND ONLINE DEBUG METHOD FOR INFORMATION PROCESSING DEVICE - An online debug system for an information processing device is provided that enables easily connecting a debug device for online debugging to an information processing device while maintaining minimum required functions of the information processing device as a product. The online debug system has a debug device that transfers a directive from outside to thereby debug a navigation system. The navigation system includes a debug daemon that debugs the navigation system and a data expansion unit that reads a communication driver group stored in a USB memory via a connection terminal and validates it. A serial communication driver as the communication driver group validated in the navigation system enables the debug device to communicate with the debug daemon.05-30-2013
20100042874DEVICE TESTING METHOD AND ARCHITECTURE - The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.02-18-2010
20130042142DEBUG CARRIER TRANSACTIONS - An integrated circuit 02-14-2013
20090044055METHOD FOR SERVICING HARDWARE OF COMPUTER SYSTEM AND METHOD AND SYSTEM FOR GUIDING TO SOLVE ERRORS - A method for guiding to solve system errors is applied to a computer system. The method of the invention includes the step of calling a debugging application software to check a system state of the computer system when a request for detecting errors inputted by a user is received. When a system error occurring in the computer system is detected, a client database is connected to determine whether a corresponding solution for the user to debug the computer system exists. When the solution corresponding to the system error is not searched out from the client database, a network is connected to transfer a detected error message to a client service terminal.02-12-2009
20120192009TESTING METHOD AND TESTING SYSTEM OF KEYBOARD MODULE - A keyboard module testing system includes a computer host, a test frame, an encoding program and a main test program. The encoding program and the main test program are both installed in the computer host. The test frame is connected with the keyboard module and the computer host for generating plural key codes. The encoding program is used for assigning plural key codes to respective keys. According to the plural key codes, the main test program can recognize which key is being tested.07-26-2012
20130073905Systems, Methods, and Apparatus to Debug a Network Application by Utilizing a Cloned Network and an Interactive Debugging Technique - A method includes instantiating a cloned network that includes a second set of virtual service nodes. The second set of virtual service nodes includes at least one cloned virtual service node that is a clone of a corresponding virtual service node in a first set of virtual service nodes. The at least one cloned virtual service node has access to a history of events that occurred at the corresponding virtual service node in the first set of virtual service nodes. The method includes initiating an interactive debugging session that includes processing of the events of the history of events.03-21-2013
20130073904SYSTEM AND METHOD FOR MANAGING TEST OF BASEBOARD MANAGEMENT CONTROLLER - A baseboard management controller (BMC) server connects to an electronic device. The electronic device includes a BMC. The BMC server stores test instructions of test items of the BMC. If a user selects test items of the BMC, the BMC server download the corresponding test instructions to the electronic device. The electronic device executes the test instructions and acquires test results. If the test results accord with standard test results of the test items, the BMC server prompts that tests of the test items pass. If the test results do not accord with the standard test results of the test items, the BMC server determines that the tests of the test items fail.03-21-2013
20130061094Apparatus and Method for the Protection and for the Non-Destructive Testing of Safety-Relevant Registers - The present invention enables a safety management of safety measures as well as the non-destructive testing of safety-relevant registers which are required for the configuration of a system, wherein the test method according to the invention can be carried out during each operating phase of a system to be tested.03-07-2013
20130061093DISTRIBUTED TEST SYSTEM AND METHOD, DISTRIBUTED TEST CONTROL SYSTEM AND METHOD, DISTRIBUTED TEST PLAN CREATING APPARATUS AND METHOD, DISTRIBUTED TEST AGENT, AND DISTRIBUTED TEST PLAN PERFORMING METHOD - A distributed test plan creating apparatus and method, a distributed test control system and method, and a distributed test agent and method are provided which control a plurality of agents to generate a good number of virtual clients, monitor test results, and reflect feedback information. A master plan scenario is created to control a large-scale server test by using at least one or more distributed test agents, and based on the master plan scenario, a per-agent plan is created to control the operation to be fulfilled by each distributed test agent. The distributed test agent is controlled according to the per-agent plan. Test results are received and read to generate feedback information which is used to create a new master plan. Therefore, a large-scale distributed test may be performed to properly respond to changes in data and situations.03-07-2013
20130067279TEST SYSTEM WITH MOTHERBOARD AND TEST CARD - A test system includes a motherboard and a test card. The motherboard includes a number of electronic components and a first connector. The test card includes a second connector and a number of indicating circuits. The first connector includes a number of signal pins. Each signal pin of the first connector is connected to a corresponding signal terminal of the electronic components, to receive a power good signal. The second connector includes a number of signal pins. Each signal pin of the second connector is connected to a corresponding signal pin of the first connector, to receive a corresponding power good signal. Each indicating circuit is connected to a corresponding signal pin of the second connector, and indicates whether the corresponding signal pin of the second connector outputs a power good signal.03-14-2013
20130067278TESTING DEVICE, SWITCHING SYSTEM AND SWITCHING METHOD - A testing device communicating with an input device is capable of executing a plurality of programs. The testing device includes a displaying unit, a detecting unit, and a judging unit. The displaying unit displays the working windows of the executing program in an overlapping manner. The detecting unit detects whether a controlling signal corresponding to a predetermined program of the testing device is received from the input device. The judging unit judges whether the working window of the predetermined program is the top-level working window in response to the controlling signal and switches the working window of the predetermined program to be the top-level working window when the working window of the predetermined program is not the top-level working window.03-14-2013
20120117426METHOD AND PROGRAM FOR VERIFYING OPERATION OF PROCESSOR - A method for verifying an operation of a processor, the method includes executing, by a software simulator, a test instruction used for verifying a model dependent operation of the processor, obtaining an expectation value from a result of the executed test instruction, obtaining a result value of the test instruction executed by the processor, and comparing, by a verification processor, the obtained expectation value with the obtained result value to determine a match or mismatch between the expectation value and the result value.05-10-2012
20110022892AUTOMATIC TESTING APPARATUS - The present invention relates to an automatic testing apparatus, which comprises a device under test and a testing module. The device under test has a testing program and includes a plurality of functional modules. The testing module is coupled to the device under test. The device under test executes a testing program and communicates with the testing module so that the testing module can test the plurality of functional modules of the device under test. By adopting automatic testing, no tester is needed for performing testing. Thereby, the personnel cost can be reduced and the total testing time can be shortened.01-27-2011
20130166954TEST APPARATUS FOR TESTING SIGNAL TRANSMISSION OF MOTHERBOARD - A test apparatus for testing peripheral component interconnect express (PCIe) signals transmission of a motherboard includes a printed circuit board including an edge connector, a number of first switches having a same number with the type of the PCIe signals to be test, an encoder, and a microprocessor. The first switches are used to select a type selection signal. The encoder converts signals outputted from the first switches to binary data. The microprocessor outputs clock signals to a PCIe controller according to the binary data to make the PCIe controller transmit the PCIe signal to the PCIe slot.06-27-2013
20110283140NETWORK COMMUNICATION AT UNADDRESSED NETWORK DEVICES - A method of network testing relies on communication with an unaddressed test device. The method includes collection of network addresses from packets passing through the test device and a discovery procedure. The collected addresses are provided to a remote control device, and used for communication between the test device and the control device.11-17-2011
20130219217SYSTEM AND METHOD FOR AUTOMATED TEST CONFIGURATION AND EVALUATION - A comprehensive system for enabling automated configuration and testing of software applications and services is disclosed. The system includes test interfaces, a test database and test functionality. Configuration functionality allows for rapid, accurate and efficient set up of one or more test accounts. Data manipulation interfaces and methods allow for the inspection of state variables and manipulating state-based data to simulate, initiate and reverse transactional data. Application programming interfaces enable the testing of external systems with a target system that is simulated in the testing environment.08-22-2013
20100115336MODULE TEST DEVICE AND TEST SYSTEM INCLUDING THE SAME - A test system includes a host, a module to communicate with the host, and a test device to test the module while the module is connected to the host. The host includes a pulse width modulator circuit to supply a power to the module, and the test device varies a feedback resistance value provided to the pulse width modulator circuit.05-06-2010
20100268990TRACING SUPPORT FOR INTERCONNECT FABRIC - Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect.10-21-2010
20110197097INCREMENTAL PROBLEM DETERMINATION AND RESOLUTION IN CLOUD ENVIRONMENTS - Installation files are annotated, which annotations may trigger system snapshots to be taken at a plurality of points during the execution of the installation files and/or collected. During a test run, the generated snapshots are examined incrementally to determine whether the installation is success or failure at that point. Checkpoint snapshots are stored, and those indicating failure are recorded with description of the error and/or remediation that suggest how the errors may be resolved or fixed. During a production run, the annotated installation files may be executed and the checkpoint snapshots generated during the production run may be compared with those stored of the test run to incrementally identify and resolve potential problems in the production run.08-11-2011
20100083045METHODS AND APPARATUS TO PERFORM QUALITY TESTING IN INTERNET PROTOCOL MULTIMEDIA SUBSYSTEM BASED COMMUNICATION SYSTEMS - Methods and apparatus to perform quality testing in Internet Protocol (IP) Multimedia subsystem (IMS) based communication systems are disclosed. An example IMS-based system comprises a web portal to allow a user to configure quality testing for a user endpoint and to present results of the quality testing, a test server to exchange packets with the user endpoint to perform the testing, an IMS application server to implement a state machine to establish a test session between the test server and a test module of the user endpoint, the packets to be exchanged between the test server and the test module via the session, and a data analyzer to determine one or more parameters representative of performance of the session based on the exchanged packets, and to provide the same to the web portal, the web portal to present information representative of the one or more parameters to the user.04-01-2010
20090019311METHOD OF TESTING AN ELECTRONIC SYSTEM - A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.01-15-2009
20090265580ERROR DETECTION METHOD FOR A COMPUTER SYSTEM, AND ELECTRONIC DEVICE - An error detection method for a computer system includes the steps of: enabling an error-detecting computer to communicate with a keyboard controller of a computer-under-test through a communication interface; enabling the error-detecting computer to issue an error detection command to the keyboard controller that causes the keyboard controller to issue a request command to the basic input/output system (BIOS) of the computer-under-test; enabling the BIOS, in response to the request command, to access the keyboard controller and determine hardware status information that is being requested from the error detection command, and subsequently, to obtain the hardware status information of the computer-under-test, and to transmit the hardware status information to the keyboard controller; and enabling the keyboard controller to transmit the hardware status information received thereby to the error-detecting computer through the communication interface.10-22-2009
20090164845DEVICE TESTING ARCHITECTURE, METHOD AND SYSTEM - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.06-25-2009
20110145641 Method and system for VoiceXML quality assurance. - A software quality assurance tool (“IVRT”) for VoiceXML applications is described. IVRT makes speech and telephony irrelevant to the testing of VoiceXML logic. IVRT follows a machine-readable “Test Plan” to execute the logic of an application. The Plan provides the results of telephony interactions. Testing is done without live callers, and runs at computer speed. A Plan contains any number of calls, to guide the application execution through all logic paths. The tool executes the application in a live environment with respect to all non-telephony functions, particularly web interactions, to test the application's web logic. IVRT executes multiple threads, acting as simultaneous callers, to provide controlled load web logic testing. The tool summarizes Plan “coverage”. For regression testing, IVRT tests an updated application with its original Test Plan and compares the log to previous logged output. Differences indicate potential regression failures.06-16-2011
20110225456COMMANDED JTAG TEST ACCESS PORT OPERATIONS - The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.09-15-2011
20090240984TEST APPARATUS FOR TESTING AN INFORMATION PROCESSING APPARATUS - A test apparatus for testing an information processing apparatus includes a control unit connected to the control signal line through the connector unit to receive command information from the processing unit to execute the program, and a switching unit connected to the control unit to connect the second communication signal line and the fourth communication signal line under the control of the control unit.09-24-2009
20090100294System and Method for Path Saturation for Computer Storage Performance Analysis - A system and method for path saturation in a storage area network so that the throughput of the storage area network may be determined. The system and method includes a software utility suite that uses either a system administration scripting language, e.g., Perl or Korn shell, or by compiled or machine language software. The software utility suite includes a set of software tools to be installed on one or more computer systems sharing access to a data storage system, such as a storage area network (SAN). The software tools running on these separate computer systems communicate and collaborate in a peer-to-peer fashion in order to coordinate loading, testing and measurement of storage throughput on the shared data storage system. The software tools further coordinate the collection, storage and presentation of results data obtained through such loading, testing and measurement of the storage throughput of the shared data storage system.04-16-2009
20110231705ADAPTIVE DIAGNOSTICS FOR IMPLEMENTATION OF AN AUTOMATED TELLER MACHINE("ATM") THIN-CLIENT MODE - Thus, methods and apparatus for providing adaptive diagnostics for ATM fault conditions are provided. Such methods and apparatus may include one or more computer-readable media storing computer-executable instructions which, when executed by a processor on a computer system, perform a method for diagnosing an electronic self-service device fault condition. The method may include receiving an input from a self-service device. The input may include information regarding a fault-related event. The method may also include assessing a plurality of system-level ramifications of the fault-related event. In response to the assessing, the method may further include determining continued viability of a plurality of ATM services. The method may also include electronically providing a notification of a list of remaining viable self-service device services.09-22-2011
20090204849TEST SYSTEM AND METHOD WHICH CAN USE TOOL DURING DEBUGGING - A test process executed by a test system includes a test class thread for executing a test class in which a procedure for testing a device is described, and a tool thread for executing a tool which includes a function that can be used for the test of the device. Then, during debugging of the test class, the test system controls the test class thread so that the test class thread is in a stopped state, and controls the tool thread so that the tool thread is in an operating state.08-13-2009
20100275061SERVER AND METHOD FOR REMOTELY TESTING ELECTRONIC DEVICES - An agent server for remotely testing an electronic device is connected to the electronic device via a control interface. The control interface includes a direct power supply and a keyboard test device. The agent server receives test requirements sent from a client via a network, supplies power to a dummy of the electronic device using the direct power supply, so as to start up the electronic device. Furthermore, the agent server operates a keyboard of the electronic device according to the test requirements using the keyboard test device, so as to establish a communication between the electronic device and another electronic device. A video camera captures video and audio information of the electronic device during the communication, and transmits the video and audio information to the client. The client analyzes the video and audio information to determine a test result of the electronic device.10-28-2010
20130219218Mobile Communication Platform for Test System Applications - A mobile communication platform for a test facility to monitor various testing devices. The mobile communication platform is configured to transmit data or information to a remote test platform remote from a test facility or laboratory. In embodiments described, the communication platform is configured to interface with the one or more controller units to receive input or output data from the one or more test devices and transmit the input output data to the remote test platform via a messaging protocol initiated by the communication platform coupled to the testing device.08-22-2013
20080307260SEMICONDUCTOR IC INCORPORATING A CO-DEBUGGING FUNCTION AND TEST SYSTEM - A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.12-11-2008
20120124424ENHANCED DEBUG/TEST CAPABILITY TO A CORE RESET PROCESS - A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes receiving a first test data, which identifies a state of a state machine, wherein the state machine performs reset and initialization operations for a processor. The method also includes halting the state machine in the state identified by the first test data upon reaching the state.05-17-2012
20100229037MASTER UNIT DEVICE AND BAND MANAGEMENT METHOD USED BY THE SAME MASTER UNIT DEVICE - In a network including at least two transmission paths whose bands are respectively managed, an RTT test of DTCP-IP may fail due to a relay wait time generated by the band management regardless of retrials. An objective of the present invention is to assure success of the RTT test. A master unit device (09-09-2010
20100162046ON-CHIP SERVICE PROCESSOR - An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.06-24-2010
20100229040METHOD AND DEVICE FOR CREATING PATTERN MATCHING STATE MACHINE - A method and a device for creating a pattern matching state machine are provided. The method includes: obtaining a predefined keyword set; generating a Goto function according to the keyword set; constructing a Failure function according to the generated Goto function, and setting that an acceptable input set of the Failure state of each state is not a subset of an acceptable input set of the state, where the acceptable input set of the state indicates that when any symbol within the symbol set is input in the state, the Goto function of the state does not fail; and generating an Output function according to the Goto function and the Failure function.09-09-2010
20100229038System and Method for Testing a Module - In an embodiment, a system is disclosed. The system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected.09-09-2010
20100251021METHOD AND SYSTEM FOR EXPANDING MICRO TELECOM COMPUTING ARCHITECTURE - A method and a micro telecom computing architecture (MicroTCA) system for expanding MicroTCA are provided. On a backplane of a MicroTCA system, an advanced mezzanine card (AMC) connector and a joint test action group (JTAG) testing unit connector are set into at least one AMC slot. Setting the JTAG testing unit connector by using the existing AMC slot prevents occupying exclusive backplane space by setting another JTAG slot, and thus saves backplane space. Furthermore, after the test is completed, an AMC can be plugged in and the normal use of the AMC is not affected.09-30-2010
20120144238SYSTEM AND METHOD FOR LOCATING AN OPERATOR IN A REMOTE TROUBLESHOOTING CONTEXT - A system locates a user in a remote troubleshooting environment. An office device is utilized to perform at least one of a copy, a facsimile, a print, and an email. A headset facilities audio communication between the user and a remote troubleshooter. A compass is located proximate to the office device wherein the headset is placed in a predetermined location proximate to the compass to establish a datum point such that movement from the datum point is recognized as a location proximate to the office device. A remote processing component displays the location of the headset relative to the office device based on information provided by the compass.06-07-2012
20100146337METHOD AND DEVICE FOR DETECTING NON-REGRESSION OF AN INPUT/OUTPUT SYSTEM IN A SIMULATION ENVIRONMENT - The object of the invention is in particular a method and a device for detecting non-regression of an input/output system from a remote station comprising a test tool adapted for executing a test command of the said input/output system. The said input/output system and remote station are each connected to a communication network. The method comprises transmitting (06-10-2010
20110066887SYSTEM AND METHOD TO PROVIDE CONTINUOUS CALIBRATION ESTIMATION AND IMPROVEMENT OPTIONS ACROSS A SOFTWARE INTEGRATION LIFE CYCLE - A method and system of calibrating estimates for software projects is provided. More particularly, a method and system is provided to continuously provide calibration estimation and improvement options across a software integration life cycle. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to: compare actual data associated with a phase of a project to expected results used to develop a strategic development plan for the project; and calibrate efforts in the strategic development plan for future activities of the project based on the actual data.03-17-2011
20100223501Recording method for video/audio data - In order to provide a recording method for data which have been or are being generated at a data source in a time sequenced manner and are transmitted via a digital network to at least one recording device for storage, by means of which method the data can be reliably recorded, it is provided that the data are stored at the data source before the transmission on the digital network in such a way that, after a fault on the digital network, data which were intended for transmission during the period of the fault can be made available to the at least one recording device.09-02-2010
20090132856SYSTEM AND METHOD FOR DISTRIBUTED MONITORING OF A SOAP SERVICE - A computer implemented method, apparatus, and computer usable program code for the distributed monitoring of a SOAP service is provided. A test configuration file specifying a test input is distributed from a central reporting location to at least one remote data processing system that has access to a SOAP service to be tested. The test configuration file is created without accessing the SOAP service to be tested. Furthermore, the user that created the test configuration file is not allowed access to the SOAP service to be tested.05-21-2009
20110214019HIGH RESILIENCY NETWORK INFRASTRUCTURE - The invention provides a highly resilient network infrastructure that provides connectivity between a main network such as the Internet and a subnetwork such as a server-based (e.g., web server) local area network. In accordance with the invention, a network interface incorporated into a server hosting center provides a resilient architecture that achieves redundancy in each of three different layers of the Open System Interconnect (OSI) stack protocol (i.e., physical interface, data link, and network layers). For every network device that is active as a primary communication tool for a group of subnetworks, the same device is a backup for another group of subnetworks. Based on the same connection-oriented switching technology (e.g., asynchronous transfer mode (ATM)) found in high-speed, broadband Internet backbones such as that provided by InternetMCI, the network interface architecture provides a high degree of resiliency, reliability and scalability. In accordance with the invention, interface network routers which provide routing functionality and connectivity between the Internet backbone and the customer subnetworks are fully meshed with those deployed in the Internet backbone. Permanent virtual circuits (PVCs) providing a multitude of logical transmission paths between each hosting center router and every router in the Internet backbone, greatly reduces processing delays of data traffic through the infrastructure as only a single “hop” routing step is required between any external access point on the Internet backbone and a hosting center router.09-01-2011
20110072306Method and System for Automated Test of End-User Devices - A test system, for example for set top boxes or game consoles, includes logic to reformat media signals output by a device under test, logic to receive the reformatted media signals and to analyze them for errors, and a pluggable interface coupling the device under test to the logic to reformat the media signals.03-24-2011
20080320329ROW FAULT DETECTION SYSTEM - An apparatus and program product check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.12-25-2008
20120311385CONTROL SERVER AND METHOD FOR SWITCHING RUNNING OF TEST PROGRAMS STORED IN MULTIPLE STORAGE MEDIUMS OF TEST SERVER - A control sever electronically connects a test server via network interfaces. The test server includes multiple storage mediums that store multiple test programs for testing the test server. The control server includes a switching control unit. The switching control unit selects one storage medium from the storage mediums as a startup device of the test server, and sends a control command to run one or more test programs stored in the startup device. In response to receiving a test result from the test server, the switching control unit selects a next storage medium from the storage mediums as a new startup device, and runs one or more test programs stored in the new staring device until all the storage mediums have been selected as startup devices one by one.12-06-2012
20120311384WAKE-UP SIGNAL TEST SYSTEM AND TEST CARD - A wake-up signal test system to test a wake-up signal output by a platform controller hub (PCH) of a motherboard includes a test card and an oscillograph. The test card includes a board with an edge connector, and a button. The button is connected between a first ground pin and a first wake-up signal pin of the edge connector. When the edge connector is inserted into a peripheral component interconnect express (PCIe) socket of the motherboard, the first ground pin is connected to a second ground pin of the PCIe socket, the first wake-up signal pin is connected to a second wake-up pin of the PCIe socket. When the button is pressed, the first wake-up signal pin is connected to the first ground pin to output a low level signal to the PCH to wake up the motherboard. The oscillograph displays a voltage state of the low level signal.12-06-2012
20080256390Project Induction in a Software Factory - A computer-implemented method, system, and computer-readable medium for inducting a software project into a software factory is presented, wherein an induction process identifies what processes and sub-processes are needed to create the software factory, and wherein the induction process identifies potential risks to the software factory. In a preferred embodiment, the computer-implemented method comprises the steps of: submitting a factory project proposal to a service definition process; creating a service definition template from a compilation of selected checklists; scoring and classifying the service definition template to determine if the candidate project may be executed in the software factory; in response to the service definition template scoring above a pre-determined acceptable score, transmitting the factory project proposal to a service induction process; and in response to the candidate project passing a final review process, transmitting the candidate project to the software factory for execution.10-16-2008
20110138226SYSTEM AND METHOD FOR TESTING COMPUTING DEVICE - A system for testing a computing device includes a test device, a switch module connected between the test device and the computing device, and a display module connected to the test device for displaying a plurality of test parameters. The testing device is connected to the computing device via a USB connection. The test device has a power cycling test program and a display driving program. The test device sends trigger signals to turn the computing device on or off and receives signals from computing device via the USB connection, for detecting the occurrence of errors during testing. A method utilizing the system is also disclosed.06-09-2011
20100017656System on chip (SOC) device verification system using memory interface - A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.01-21-2010
20120042208TEST OPTIMIZATION - A method for optimizing tests of a software application. The method includes determining a test run time for each test of a plurality of tests of a software application; and dividing the tests into a plurality of test groups. The method further includes assigning a worker system of a plurality of worker systems to each test group; and causing the worker systems to run the tests.02-16-2012
20120023370BULK TRANSFER OF STORAGE DEVICES USING MANUAL LOADING - A storage device transfer station is provided for transferring storage devices from a human operator to automated machinery for testing. The storage device transfer station includes a plurality of slots each capable of holding a storage device. The plurality of slots is arranged in at least one field, and the field is arranged between two parallel planes. Each slot has a first open end and a second open end, such that each open end is accessible for loading and unloading a storage device. The first open ends are accessible at a first plane of the two parallel planes and the second open ends are accessible at a second plane of the two parallel planes.01-26-2012
20120233502SYSTEM AND METHOD FOR TESTING HIGH-DEFINITION MULTIMEDIA INTERFACE OF COMPUTING DEVICE - In a method for testing a high-definition multimedia interface (HDMI) of a computing device, tests are individually selected and applied to the HDMI. A source code file of the selected test is obtained from a storage system of the computing device. The parameters of the selected test and display resolutions of a display device of the computing device are set. The obtained source code file are executed to apply the selected test to the HDMI according to the set parameters and the display resolutions. After the source code has been executed, the test results are stored.09-13-2012
20090132857SYSTEM AND METHOD FOR TESTING AN EMBEDDED SYSTEM - A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.05-21-2009
20110185232DYNAMIC CONFIGURATION OF VIRTUAL MACHINES - A computer implemented method for configuring virtual internal networks for testing is provided, such that affects of testing are internally isolated. The method includes deploying a virtual firewall and deploying a public switch enabling access to an external local area network through a first interface of the virtual firewall. A private switch enabling access to a plurality of virtual machines through a second interface of the virtual firewall is provided. The plurality of virtual machines defines a private network behind the firewall. A network address is assigned to the virtual firewall and a private address is assigned to each of the virtual machines. The plurality of virtual machines is then tested through a test launcher in communication with the public switch.07-28-2011
20110185231SOFTWARE APPLICATION TESTING - An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices.07-28-2011
20120124423METHOD AND SYSTEM FOR PROVIDING EFFICIENT ON-PRODUCT CLOCK GENERATION FOR DOMAINS COMPATIBLE WITH COMPRESSION - A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.05-17-2012
20120221893MANAGING TEST AUTOMATION - Systems, methods and computer program products relating to test automation management are described. In some aspects, a request for initiating at least one test automation task is received by an electronic computing device from a mobile device. A web service associated with the received request and at least one automation tool are identified. At least one automation tool is launched in response to the received request. The launched at least one automation tool executes at least one test script based on the received request, the at least one test script can include a sequence of instructions. Test data are loaded based on at least a portion of the executed a sequence of instructions for the at least one test automation task, and one or more test results associated with the executed at least one test script are stored.08-30-2012
20120221894TEST DATA MANAGEMENT SYSTEM AND METHOD - In a test data management method, an electronic signal that needed to be tested of an electronic device is select. A predefined template file of a test report of the electronic signal is generated. Test data of the electronic signal is obtained from a test file, and is inserted into predetermined locations of the template file. The test report of the electronic signal is generated according to the template file and the inserted test data, and the test report is stored into a storage system of a computing device.08-30-2012
20120226941DEBUG CARD AND METHOD FOR DIAGNOSING FAULTS - A debug card for diagnosing a motherboard and a power supply unit (PSU) of a same computer includes a plurality of first nixie tubes, a plurality of second nixie tubes, a first port, a second port, and a control unit. The control unit is electronically connected to the plurality of first nixie tubes, the plurality of second nixie tubes, the first port, and the second port. The first port is electronically connected to the motherboard, and the second port is electronically connected to the PSU. Under the control of the control unit, fault codes of the motherboard are displayed by the plurality of the first nixie tubes, and fault codes of the PSU are displayed by the plurality of the second nixie tubes.09-06-2012
20120233503NETWORK SYSTEM AND MANAGEMENT SERVER - A network system configured from a test device that executes a test including a continuity test and a performance test of a network configured from a plurality of transfer devices and a management server that requests an execution of the test for the test device, in this way, one or more backup session used for executing the test is selected from a plurality of sessions, the test is executed for a processing interval in a success, a next test is executed by the backup session when the processing time for the test exceeds over a specified time, thereby, a large number of tests can be executed and the test can be executed regularly even when the processing time becomes longer caused by a failure etc.09-13-2012
20110004790Asynchrony Debugging Using Web Services Interface - A system and method for debugging a running process of an application or component is disclosed. A debugging client has a user interface for receiving user commands to configure and control a debugging program. A debugging agent is resident in a local network area with the running process and has a direct connection with the running process. The debugging agent is configured to execute the debugging program to obtain debugging information on the running process, and to send the debugging information to the debugging client. A Web services communication link is established between the debugging client and the debugging agent for communicating signals to the debugging agent from the debugging client representing the user commands to configure and control the debugging program.01-06-2011
20110131449PROCESSING SYSTEM HARDWARE DIAGNOSTICS - A method for diagnosing hardware failures in a data processing system includes a configuring a portion of a programmable logic device to create a state machine. The state machine tests a communication bus and a plurality of component devices connected by the communication bus and identifies the test failures. The state machine communicates the test information to external test equipment. The communication bus is used in the operation of the data processing system and the testing includes tests at full clock speed of the data processing system.06-02-2011
20120266021AUTOMATIC TESTING APPARATUS - The present invention relates to an automatic testing apparatus used for testing a tested device. The automatic testing apparatus is fixed on a first side of a testing platform. The tested device executes a testing program while being tested, and transmits a test signal to a control unit of the testing platform for controlling a driving testing unit or a multimedia testing module to test the tested device and hence testing the tested device automatically. Thereby, testing costs can be saved and artificial factor affecting the test results can be avoided.10-18-2012
20120324287COMPUTING DEVICE AND METHOD FOR EXECUTING TEST PROGRAMS IN COMMAND-LINE INTERFACE - A computing device and method executes one or more test programs in a command-line interface (CLI). The computing device downloads one or more test programs for testing one or more parts from a server. The computing device sends the one or more test programs to the SUT via a specific cable, wherein the specific cable can transmit the one or more test programs at different baud rates. The computing device starts the CLI and control the SUT to execute the one or more test programs via the CLI, and receives a test report from the SUT after the one or more parts has been tested.12-20-2012
20120096313RECOVERY FROM HDD FAILURE AND TECHNICAL SUPPORT THROUGH WWAN - A user of a user computer whose hard disk drive (HDD) is “fried” can press a special key to cause BIOS to automatically gather location information about the computer from its GPS receiver and gather information about the HDD, activate a WWAN transceiver, and automatically send the location and HDD information over the WWAN to a service computer, which may return a location of a nearest service center to the user computer and any other advice including recovery advice for the HDD that the service center might be able to divine from the information sent to it by the user computer.04-19-2012
20120102360SYSTEM AND METHOD FOR BUSINESS FUNCTION REVERSIBILITY - The invention may provide “undo” (e.g., rollback) features, along with data management simplification features, to an update package model of software suite development/evolution. New functions, which may have disruption effects for customers, may be installed into the core configuration data with inactive switches. Upon activation, a switch status may change, and a query filter may use the activated function (e.g., as associated with the switch ID). Original functions may be maintained, giving the user the ability to deactivate an activated function, and thereby reverting the system back to the prior configuration status.04-26-2012
20100229039TESTING APPARATUS, TESTING METHOD, AND PROGRAM - A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.09-09-2010
20120137175CORRELATED TESTING SYSTEM - A computer implemented system for testing electronic equipment where test inputs, test outputs, test applied environmental conditions, and test processes are recorded and correlated.05-31-2012
20130173960Method for Checking an Installation Location of a Component and Automation Component - A method for checking an installation location of a component in a failsafe automation system, wherein the components are connected to one another in series and uniquely defined addresses are continuously assigned from a first component to successor components, wherein, after the assignment of addresses to the components, a switching device is operated in the components such that a signal transit time measurement is performed incrementally with a test signal for each successor component, and wherein the test signal is emitted and re-received and the installation location of the successor component is check based on the time difference.07-04-2013
20080256389Strategies for Performing Testing in a Multi-User Environment - A strategy is described in which multiple testing agents perform multiple respective tests in a multi-user environment. One such multi-user environment allows multiple clients to interact with remote applications that are executed on a server. According to one exemplary case, a central test management module coordinates the execution of the multiple tests by the testing agents. For instance, the test management module can prevent testing agents that make demands on a global state of the multi-user environment from interfering with other testing agents.10-16-2008
20110246827Testing Device and Testing Method - A testing device for testing an embedded system includes an interface capable of being coupled to the embedded system by means of insertion, a storage unit for storing data, and a processor for receiving a testing message corresponding to a testing command from the embedded system via the interface according to an enabling signal and storing the testing message into the storage unit when the interface is coupled to the embedded system.10-06-2011
20080222452TEST APPARATUS FOR TESTING A CIRCUIT UNIT - Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold unit for sampling at least one voltage value of an output signal output from the circuit unit and for holding the sampled voltage value, and a logic unit for driving the sample-and-hold unit. The voltage value sampled by the second test device is fed to the first test device as a test result signal.09-11-2008
20130179732Debugging of Adapters with Stateful Offload Connections - An approach is provided in which a network hardware adapter stores offload information in a shared memory area that is located on a host system. The offload information includes connection information that was offloaded to the network hardware adapter by an application executing on the host system. An operating system (e.g., a network device driver) detects a network adapter error corresponding to the network hardware adapter and, in turn, retrieves the offload information stored in the shared memory area. As such, an analysis application utilizes the retrieved offload information to debug the network adapter error.07-11-2013
20130103984FAULT INSPECTION UNIT, CENTRAL PROCESSING UNIT, AND FAULT INSPECTION METHOD - A CPU changes the operating mode to a test mode in which the CPU does not terminate a program being executed even if an MMU outputs a CPU exception notification, outputs an address signal for causing the MMU to output a CPU exception notification to the MMU in the test mode, and detects whether or not a CPU exception notification is input after the address signal is output to the MMU. This allows inspection as to whether or not a fault that prevents detection of an illegal access has occurred in the MMU while executing another program.04-25-2013
20130145212Link Equalization Tester - A method and an apparatus for performing link equalization testing via a physical layer test and measurement system. The system includes a protocol aware test apparatus for transmitting testing data, a device under test for receiving the transmitted testing data, and an oscilloscope for receiving an output waveform from the device under test. The protocol aware test apparatus selects a first of a plurality of preset values, sends an equalization signal from the protocol aware test apparatus to the device under test, and changes a speed of communication to a predetermined speed and sends a compliance pattern to the device under test after placing the device under test in a loopback mode. A waveform output from the device under test is captured by the oscilloscope, and is analyzed to determine compliance of the device under test with a predetermined link equalization speed in accordance with a predetermined protocol.06-06-2013
20080201609METHOD AND SYSTEM FOR AUTOMATICALLY DIAGNOSING DISABILITY OF COMPUTER PERIPHERAL DEVICES - A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.08-21-2008
20130151898ELECTRONIC CONNECTION QUALITY TEST DEVICE FOR UNIVERSAL SERIAL BUS INTERFACES - An electronic connection quality test device includes a plurality of test circuits, a hot plug circuit, and a control circuit. The test circuits are respectively electrically connected to a plurality of universal serial bus (USB) interfaces. The hot plug circuit is electrically connected to each of the test circuits and a USB device. The control circuit is electrically connected to each of the test circuits and controls the test circuits to electrically connect selected ones of the USB interfaces with the USB device via the test circuits and the hot plug circuit, thereby forming tested electronic connections between the selected ones of the USB interfaces and the USB device.06-13-2013
20130151899DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes a decoding module, a first storing module, a first control module; and a signal receiving and transmitting module. The computer includes a second control module, a second storing module, and a display module. The decoding module decodes data from the LPC bus. The first storing module stores decoded data. The second control module sends a set address data to the first control module via the signal receiving and transmitting module. The first control module obtains a corresponding data from the first storing module according to the set address data and send the corresponding data to the second control module via the signal receiving and transmitting module. The second control module stores the corresponding data to the second storing module and displays the corresponding data on the display module.06-13-2013
20130151897DIAGNOSTIC HANDLING SERVER, DIAGNOSTIC HANDLING METHOD, AND PROGRAM FOR THE SAME SERVER - A diagnostic handling server is capable of supporting users without operator support, in which the proper handling of a problem, which users know through experience, can be reflected in the support. Preliminarily, data (e.g., dissatisfying item data) on the item with which a user feels dissatisfied and diagnostic data on the diagnoses of the electric appliances are collected from the electric appliances to be supported. The feature points of the respective electric appliances with which the user feels dissatisfied are then extracted from the collected diagnostic data. When the user feels dissatisfied with a specific electric appliance, the diagnostic data of the electric appliance is transmitted together with a search request for the proper handling, the transmitted diagnostic data is compared with the preliminarily extracted feature point, and information on the cause and the proper handling is provided to the user.06-13-2013
20130151900DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes an SPI reading and writing module, a first control module, a detecting module, and a signal receiving and transmitting module. The computer includes a second control module and a display module. The SPI reading and writing module is connected to an SPI device. The second control module sends an inputted write command to the first control module. The first control module writes data to the SPI device according to the inputted write command. The detecting module sends a fail signal to the first control module after detecting that the data is not written to the SPI device and a written times of the data is greater than a predetermined times. The first control module sends the fail signal to the second control module. The second control module displays the fail signal on the display module.06-13-2013
20130159770SYSTEM AND METHOD FOR ACQUIRING BASIC INPUT/OUTPUT SYSTEM DEBUG CODES - A system is used for acquiring Basic Input/Output System (BIOS) debug codes. The system includes a platform controller hub (PCH), a storage chip, and a baseboard management controller (BMC). The PCH reads power-on self tests (POST) codes from an address port of a bus, and converts the POST codes to binary data and stores the binary data in the storage chip. The BMC reads the binary data stored in the storage chip and defines the binary data as virtual sensor data, which conform with threshold type data, and decodes the virtual sensor data to POST codes and controls a display unit to display the POST codes.06-20-2013
20110314333System and Method of Providing Driver Software to Test Controller to Facilitate Testing by Wireless Transceiver Tester of a Device Under Test - A system and method of providing driver software to a test controller to facilitate testing by a wireless transceiver tester of a device under test (DUT). Using the wireless transceiver tester, executable tester instructions are accessed from one or more computer readable media and in accordance therewith bi-directional signal communications are established between the wireless transceiver tester and the test controller, and between the wireless transceiver tester and the DUT. Further accessed are executable driver instructions, including a plurality of executable driver program instructions for driving at least one of the wireless transceiver tester and the DUT, which are communicated to the test controller.12-22-2011
20130212434FIELD TESTER FOR TOPOLOGIES UTILIZING ARRAY CONNECTORS AND MULTI-WAVELENGTH FIELD TESTER FOR TOPOLOGIES UTILIZING ARRAY CONNECTORS - A test instrument provides suggested next operational step function to provide a user with assistance during testing. A display is provided to show the amount of a project that has been completed, for example as a percentage completed value. Individual test results may be saved to a ‘fix later’ list, which may be later accessed to re-test items that may not have passed on initial testing.08-15-2013

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