Class / Patent application number | Description | Number of patent applications / Date published |
714008000 | Isolating failed storage location (e.g., sector remapping) | 33 |
20080209265 | Information-Processing Method and Apparatus - At a stage of compiling of a source code, range information of a variable that a pointer points and information for a failure recovering are installed into the pointer variable. Since failure recovering information can also be acquired when an illegal pointer access is detected based on range information, a recovering processing suitable for data that has caused the failure is performed according to the failure recovering information. By relating the range information and the failure recovering information with the data address, a data type of a memory area at the failure location can be specified using the failure recovering information (UPPER, LOWER, and FIXED). | 08-28-2008 |
20080222450 | Zero-penalty RAID controller memory leak detection and isolation method and system utilizing sequence numbers - A method and system for detecting and isolating memory leak in RAID controllers utilizing sequence numbers. The system monitors whether the count of un-freed memory blocks for a sequence number (SN) zone (after a start-of-day SOD operation, but smaller than the current sequence number zone) is not eventually decremented to zero. The memory leak can be detected when un-freed memory blocks exist and follow a similar pattern with respect to all other adjacent SN zones. The detected memory leak can be isolated utilizing shell commands, task information, caller information, sequence number, memory allocation size and a pointer to the next allocated memory block. | 09-11-2008 |
20080235534 | INTEGRITY PROTECTION IN DATA PROCESSING SYSTEMS - A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine. | 09-25-2008 |
20080263394 | Disk array apparatus - A disk array apparatus where, when a failure occurs at a part of a cache memory, a memory area of an I/O processing controller other than the memory area where the failure has occurred is utilized without taking over the whole I/O processing to an I/O processing controller of other system is provided, so that influence of performance degradation can be minimized. In a disk array apparatus including dual cache memories, when a failure occurs at a part of the cache memory, only a memory area where the failure has occurred is closed, and reallocation thereof to another memory area of the same cache memory is conducted to continue an I/O processing. | 10-23-2008 |
20080282107 | Method and Apparatus for Repairing Memory - Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit. | 11-13-2008 |
20080294936 | SOFTWARE MEMORY LEAK ANALYSIS USING MEMORY ISOLATION - A computerized method, program product, and a service that allocates and isolates leaky memory during the execution of an application in a data processing system. A memory controller having several components first identifies a leaky section of memory and delegates to an allocation component to allocate more memory if possible. If, however, the problematic memory section should not be allocated more memory, an isolator component can isolate the memory section and further divide the memory section into subsections and so on. Each section and each subsection may then be tested to determine if more memory can be allocated, tested to determine if memory resources are strained so as to identify the application or its component causing the strain and then binding the memory. Each section and subsection and further divided and isolated until the leaky portion of memory is identified, and as a result, the software component causing the leak can also be identified. The software component associated with the leaky memory section or subsection can also be taken out-of-service. | 11-27-2008 |
20080313495 | Memory agent - In one embodiment a computer system comprises a processor, a memory controller, one or more memory modules coupled to the memory controller via a communication link, and a memory agent coupled to the communication link between the memory controller and the one or more memory modules, wherein the memory agent provides services to the memory controller. | 12-18-2008 |
20080320327 | Degeneration control device and degeneration control program - A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit. | 12-25-2008 |
20090063896 | SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE - A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line. | 03-05-2009 |
20090138756 | METHOD OF DETERMINING DEFECTS IN INFORMATION STORAGE MEDIUM, RECORDING/REPRODUCING APPARATUS USING THE SAME, AND INFORMATION STORAGE MEDIUM - A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a method comprises: seeking a defect entry whose state information indicates that a defect block or a replacement block has been re-initialized without certification from a defect list for managing an information storage medium and including state information of the defect block and state information of the replacement block, wherein the medium includes a spare area for recording the replacement block to replace the defect block occurring in a user data area on the medium; and certifying the defect block or the replacement block registered in the sought defect entry. As a result, defect information can be effectively rearranged for quick re-initialization without certification in order to improve the performance of a drive system. | 05-28-2009 |
20090164842 | METHOD AND SYSTEM FOR ENTERPRISE MEMORY MANAGEMENT OF MEMORY MODULES - A method and system for enterprise memory management of memory modules of a computer system. The method includes scanning memory chips of a memory module for errors, analyzing a scrub error map corresponding to a scrubbing operation of the memory module, generating a scrub map summary based upon the scrub error map analyzed, creating an error history map by adding the scrub map summary generated, analyzing the error history map created and tracking a chip location for each memory chip of the memory module including errors, and determining a scrubbing algorithm of the memory module based on the analyzed error history map. The enterprise memory management system includes a plurality of computers each including memory modules, and an enterprise memory manager which collects and analyzes error history maps corresponding to each computer and determines a scrubbing algorithm of the memory modules of each computer. | 06-25-2009 |
20090199043 | ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS - An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array. | 08-06-2009 |
20090204847 | REPAIRABLE BLOCK REDUNDANCY SCHEME - A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses. | 08-13-2009 |
20090217086 | Disk array apparatus, disk array control method and disk array controller - An error table stores information indicating the occurrence of an error. A statistical score addition table stores the number of scores for disk or path according to the error. A control unit adds the first number of scores to the error disk. Also, when the information indicating the occurrence of the error is not stored in the error table, the control unit adds the second number of scores smaller than the first number of scores to the path to the error disk, while when the information is stored, the control unit adds the third number of scores larger than the first number of scores to the path. The control unit separates the path or disk of which the number of scores exceeds a threshold from the disk array apparatus. | 08-27-2009 |
20090235115 | DATA STORAGE - A data storage system comprising a plurality of storage devices, each storage device comprising a plurality of storage nodes and each storage node comprising a plurality of logical partitions such that there are at least Q copies of a particular logical partition in the storage system. Each logical partition is divided into a plurality of sub-ranges which are individually lockable to both data input and data output whereby data in a particular logical partition is synchronisable sub-range by sub-range with the other copies of said particular logical partition. A method of maintaining such a data storage, including creating and updating data in the data store, recovering from failure of an element of the data store and/or increasing capacity in the data store. | 09-17-2009 |
20090287957 | METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT - A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell. | 11-19-2009 |
20090300413 | DISABLING PORTIONS OF MEMORY WITH DEFECTS - An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory. | 12-03-2009 |
20090307525 | DISK DRIVE AND METHOD FOR CONTROLLING THE DISK DRIVE - A disk drive. The disk drive includes a non-volatile memory that is incapable of being overwritten more than a limited number of times, a disk and a controller. The controller includes a memory management table used to manage a correlation between a logical block address (LBA) and a physical address of the non-volatile memory. In the absence of a replaceable region in the non-volatile memory and in response to an occurrence of a failure to write data in a region, defined as a failure region, in the non-volatile memory at a first physical address correlated with a first LBA, the controller is configured to write the data at a second physical address correlated with a second LBA of the non-volatile memory different from the first LBA, and is configured to correlate in the memory management table the first LBA with the second physical address. | 12-10-2009 |
20090327804 | WEAR LEVELING IN FLASH STORAGE DEVICES - A method of wear leveling in a flash storage device comprising a plurality of data blocks is provided. The method comprises the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks. | 12-31-2009 |
20100023804 | TCAM BIST WITH REDUNDANCY - A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry. | 01-28-2010 |
20100058109 | DISABLING PORTIONS OF MEMORY WITH DEFECTS - An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory. | 03-04-2010 |
20100153775 | REPLACEMENT DATA STORAGE CIRCUIT STORING ADDRESS OF DEFECTIVE MEMORY CELL - A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells are connected to the word lines and the bit lines to store an address of a defective memory cell. Each of the word lines is connected to a plurality of replacement data memory cells and each of the bit lines is connected to one replacement data memory cell. | 06-17-2010 |
20100192009 | OPERATION METHOD OF SUPPRESSING CURRENT LEAKAGE IN A MEMORY AND ACCESS METHOD FOR THE SAME - A method for suppressing current leakage in a memory includes a column redundancy evaluation which is executed when a memory is powered on so as to find out a failed memory unit of the memory. A current path between the failed memory unit and a pre-charging power source is disconnected according to the column redundancy evaluation result. Thus, bit lines in the failed memory cells are not pre-charged to avoid current leakage occurred between bit lines and word lines in the failed memory cells. | 07-29-2010 |
20100235679 | DEFECTIVE MEMORY BLOCK REMAPPING METHOD AND SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address. | 09-16-2010 |
20100275058 | Method and Apparatus for Management Between Virtualized Machines and Virtualized Storage Systems - To manage physical paths between a server system and a storage system and information about routing between virtual machines and virtual storage systems in an integrated fashion. A computer system of the present invention includes: a computer and a storage system that stores data, in which the computer includes first information for managing the first resource relating to the computer; and the storage system includes second information for managing the second resource provided in the storage system, and in which a relation between the virtual machine and the virtual storage system is defined based on the first information and the second information. | 10-28-2010 |
20100293410 | Memory Downsizing In A Computer Memory Subsystem - Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs. | 11-18-2010 |
20100306580 | Systems and Methods for Governing the Life Cycle of a Solid State Drive - Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable. | 12-02-2010 |
20100306581 | SOLID STATE STORAGE END OF LIFE PREDICTION WITH CORRECTION HISTORY - Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data. | 12-02-2010 |
20100306582 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes performing a program operation on memory cells included in a selected page, checking whether a verification operation for the programmed memory cells is passed or failed by performing the verification operation, counting a number of error bits for the selected page, if the verification operation is failed, performing an error checking and correction (ECC) algorithm using an error correction circuit, if the counted number of error bits is less than or equal to a number of correctable bits, and storing the counted number of error bits in a specific one of a plurality of memory blocks. | 12-02-2010 |
20100306583 | Memory Systems and Defective Block Management Methods Related Thereto - Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition. | 12-02-2010 |
20100332894 | BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE - Subject matter disclosed herein relates to remapping a memory device. | 12-30-2010 |
20100332895 | NON-VOLATILE MEMORY TO STORE MEMORY REMAP INFORMATION - Subject matter disclosed herein relates to remapping memory devices. | 12-30-2010 |
20110047411 | Handling of errors in a data processing apparatus having a cache storage and a replicated address storage - A data processing apparatus and method are provided for handling errors. The data processing apparatus comprises processing circuitry for performing data processing operations, a cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations, and a replicated address storage having a plurality of entries, each entry having a predetermined associated cache record within the cache storage and being arranged to replicate the address indication stored in the associated cache record. On detecting a cache record error when accessing a cache record of the cache storage, a record of a cache location avoid storage is allocated to store a cache record identifier for the accessed cache record. On detection of an entry error when accessing an entry of the replicated address storage, use of the address indication currently stored in that accessed entry of the replicated address storage is prevented, and a command is issued to the cache location avoid storage. In response to the command, a record of the cache location avoid storage is allocated to store the cache record identifier for the cache record of the cache storage associated with the accessed entry of the replicated address storage. Any cache record whose cache record identifier is stored in the cache location avoid storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach enables errors to be correctly handled, prevents errors from spreading in a system, and minimises communication necessary on detection of an error in a data processing apparatus having both a cache storage and a replicated address storage. | 02-24-2011 |