| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 713502000 | Counting, scheduling, or event timing | 58 |
| 20110185217 | Method and Apparatus for the Realization of a Failsafe Time Function - A method for enabling an oscillating crystal available in a system to be used to generate a software-realized time function, and an apparatus for implementing the method, without requiring additional hardware components, wherein a periodic interrupt signal is generated by the system-internal real-time clock, a table entry with a reference to a routine in an intra-system table is accessed upon receipt of the periodic interrupt signal and a counter is formed by the routine. | 07-28-2011 |
| 20110202787 | Single Wire Serial Interface - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 08-18-2011 |
| 20100037082 | REMOTE CONTROLLER, ELECTRICAL APPARATUS AND WIRELESS CONTROLLING SYSTEM - In a remote controller, a startup time or a first time duration until the startup time is input into an input unit. A timer unit counts a clock time or a second time duration. A control unit generates a signal to turn on an electrical apparatus when the second time duration reaches the first time duration, or when the clock time equals to the startup time. A transmitting unit transmits the signal. In the electrical apparatus, a main unit operates main function. A transformer supplies electricity from an external power source to the main unit through a switch. A rectifier rectifies the signal. A signal identifying unit identifies it. A reservation memory unit keeps parameter for main function. A control unit turns on the switch and controls the main unit according to the parameter when the signal is received. A battery supplies electricity to above units. | 02-11-2010 |
| 20100037081 | Method and Apparatus for Maintaining Time in a Computer System - A computer system is arranged with a circular buffer that includes a piecewise linear map from a high-resolution counter arranged to maintain International Atomic Time. The piecewise linear map includes a current leg that is currently being used and also a future leg that will be used in the future. The future leg is computed while the current leg is still being used. | 02-11-2010 |
| 20130080819 | MICROCONTROLLER WITH SCHEDULING UNIT - A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register. | 03-28-2013 |
| 20130042138 | METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION - Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units. | 02-14-2013 |
| 20100100759 | ELECTRONIC TIMER SYSTEM, TIME CONTROL AND GENERATION OF TIMING SIGNALS - An electronic timer system includes a counter-based time generator ( | 04-22-2010 |
| 20130047023 | Adaptive Clocking Scheme to Accommodate Supply Voltage Transients - Adaptive clocking schemes for synchronized on-chip functional Hocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example, in embodiments, the docking schemes allow for the capacity utilization of a logic path to be increased. | 02-21-2013 |
| 20120192004 | EVENT INFORMATION RELATED TO SERVER REQUEST PROCESSING - A method disclosed herein provides for receiving information relating to an event that occurred while processing server request from a compiled code snippet inserted into a compiled computer program, calculating diagnostic information relating to execution of the server request based on the received information, and providing the diagnostic information. Alternatively, a computer-readable medium, storing a set of instructions, is provided for, the instructions, when executed by a processor perform a method including, while a server request is being executed, receiving information from a compiled code snippet, in inserted into a compiled computer program, the received information relating to a thread starting to process the server request. Alternatively, an apparatus is provided to receive information from a plurality of compiled code snippets, inserted into a compiled computer program, the received information relating to a plurality of threads processing a server request and storage to store the received information. | 07-26-2012 |
| 20130073891 | METHOD FOR CHECKING SIGNAL AND MODULE ACTIVITIES IN A TIMER MODULE AND TIMER MODULE - A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the, external arithmetic unit. | 03-21-2013 |
| 20130067265 | METHOD AND APPARATUS FOR ALARM FOR AIR FILTER - An apparatus including an air filter for an air conditioning device, a warning device, a computer processor, a computer memory, a count setting device, and a reset device. The computer processor is programmed to set a value of a timer count variable to an operator input start value in the computer memory in response to the count setting device. The computer processor is programmed to count down the value of the timer count variable and when the value of the timer count variable has counted down to an alarm level, to activate the warning device. The reset device is actuated by an operator to cause the computer processor to deactivate the warning device and to reset the value of the timer count variable to the operator input start value, and to cause the value of the timer count variable to be counted down. | 03-14-2013 |
| 20130103969 | CLOCK GENERATION DEVICE FOR USB DEVICE - A clock generation device comprises a clock generation unit, a counter, a common factor calculation element, a first frequency divider, a phase-locked loop (PLL) and a second frequency divider. The counter receives a clock signal from the clock generation unit and a periodic signal from a USB host, and outputs a count value. The common factor calculation element calculates the common factor of the count value and a value to output a first adjustment value and a second adjustment value. The first frequency divider divides the frequency of the clock signal by the first adjustment value to output a reference signal. The second frequency divider divides the frequency of the output clock signal of the PLL by the second adjustment value to obtain a feedback signal input to the PLL. Based on the reference signal and the feedback signal, the PLL outputs a clock signal complying with the USB specification. | 04-25-2013 |
| 20130103970 | NETWORK DEVICE, NETWORK NOTIFYING DEVICE APPLIED TO NETWORK DEVICE AND ASSOCIATED NETWORK NOTIFYING METHOD - A network notifying device applied to a first network device is provided, where the first network device is coupled to a second network device, and the network notifying device includes an interface control circuit, a clock generator and a counter. The interface control circuit is coupled to the second network device, and stores a notify command. The clock generator is utilized for generating a clock signal. The counter is coupled to the interface control circuit and the clock generator, and the counter counts the clock signal to periodically generate a trigger signal to the interface control circuit to trigger the interface control circuit to transmit the notify signal to the second network device. In addition, operations of the clock generator and the counter are independent from a processor of the first network device. | 04-25-2013 |
| 20090265573 | DATA TRANSMISSION/RECEPTION CIRCUIT - The present invention provides a data transmission/reception circuit which stops the operation of a packet transmission/reception circuit during a data transfer-free time thereby to realize power savings. The data transmission/reception circuit includes a packet transmission/reception circuit for performing transmission/reception of data to and from an external USB host via a USB bus at one data transfer intervals per predetermined frame, a clock generator for generating a clock signal and supplying the clock signal to the packet transmission/reception circuit, and a clock gating signal generating circuit for stopping the supply of the clock signal to the packet transmission/reception circuit by the clock generator during a frame free of the transmission/reception of the data by the packet transmission/reception circuit. | 10-22-2009 |
| 20080215908 | Sleep Watchdog Circuit For Asynchronous Digital Circuits - The sleep watchdog circuit for asynchronous circuits of the present invention contains clock means, counting means with multiple trigger input function and a digital supply. When the circuit is in the normal operation state, a periodic reset or activity signal is present that will reset the watchdog counter. As a result the clock means will keep on running, and the digital supply is operating in “normal” mode. When the circuit is put into the “sleep/standby” state, the “activity” signal becomes inactive, and if no wakeup events occur before the counter is finished the clock means will be put to a halt and the digital supply changes into a low power mode. | 09-04-2008 |
| 20100088536 | PROCESSOR AND METHOD OF DECOMPRESSING INSTRUCTION BUNDLE - The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a program memory and creating an instruction bundle consisting of a sequence of instructions to be processed in parallel. A compression buffer is interposed between the program memory and an instruction decompression unit, such that a compression code read in a previous clock cycle is ready at the beginning of a decompression cycle of the subsequent instruction bundle thereby avoiding a delay due to memory read latency. | 04-08-2010 |
| 20090276653 | Presence server for discrete time updates - A presence server of an apparatus in one example is configured to receive at least one event message from a network entity in continuous time. The presence server is configured to determine at discrete time intervals if an update message should be sent for the network entity. The discrete time intervals comprise instances of an epoch. The presence server is configured to determine if the update message should be sent upon an epoch boundary. The presence server is configured to dynamically determine a duration of the epoch. | 11-05-2009 |
| 20080244302 | SYSTEM AND METHOD TO ENABLE AN EVENT TIMER IN A MULTIPLE EVENT TIMER OPERATING ENVIRONMENT - An information handling system including a local event timer operably associated with a management application interface is disclosed. The information handling system can also include a remote event timer accessible by a system management application. The remote event timer can be used relative to use of the local event timer. The information handling system can also include an event timer detection module operable to determine an availability of the local event timer relative to an operating system type. The event timer detection module can also initiate use of the local event timer, and disable use of the remote event timer in response to detecting a local event timer enabled operating system. A method and a chipset configured to be used by an information handling system are also disclosed. | 10-02-2008 |
| 20120297233 | SERIAL COMMUNICATIONS PROTOCOLS - Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock. By adjusting the denominator, the sampling clock can be tuned to match the baud rate of the asynchronous serial data stream received from the transmitting device. Embodiments described include power management, data acquisition (DAQ), etc. | 11-22-2012 |
| 20080270819 | Uncorrelated actions using a distributed system - A distributed system that uses distributed synchronized time to perform uncorrelated actions. A distributed system according to the present teachings includes a set of nodes each having a synchronized real-time clock. The nodes use the synchronized real-time clocks to trigger a set of uncorrelated actions from the nodes. | 10-30-2008 |
| 20090138746 | Method For Efficient Software Generation Of Multiple Pulse Width Modulated Signals - Pulse width modulation signals are generated by identifying an event table having a plurality of events, each event including a time to next event parameter. Each desired pulse width modulation signal is characterized by a first event designating a transition from a first state to a second state and a second event designating a transition from the second state back to the first state. An event pointer is set to select a current event and the event table is repeatedly cycled through by updating the output for at least each pulse width modulation signal associated with the current event having a designated state transition, detecting that a time period has lapsed corresponding to the time to next event parameter associated with the current event, incrementing the event pointer to point to a next event in the event table and conveying each pulse width modulation signal to a corresponding circuit. | 05-28-2009 |
| 20090259877 | Method to Implement a Monotonic Counter with Reduced Flash Part Wear - A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter. | 10-15-2009 |
| 20090249109 | STORAGE APPARATUS AND METHOD FOR STORING INTERNAL INFORMATION - A storage apparatus stores data in a storage area, and includes a judgment unit and an internal information management unit. The judgment unit judges whether a preconfigured given condition is satisfied. The internal information management unit associates the satisfied preconfigured condition with internal information relating to an operation or a status of the storage apparatus and manages the condition and the internal information when the judgment unit judges that the given condition is satisfied. | 10-01-2009 |
| 20090249108 | SILENT TIME TAMPERING DETECTION - Computers and other electronic devices typically include a timing operation such as a clock in an operating system. It is anticipated that hackers may tamper with this clock. This tampering might be especially advantage in the context of systems which provide for rental of audio and video content, such as movies. Tampering with the system clock on the playing device would allow an extension of the rental period to the detriment of the provider of the rental content. Hence the present method is directed to detecting clock modifications both in terms of time shifting and clock rate tampering. This detection is done using digital signal processing. | 10-01-2009 |
| 20090199037 | Wake-up timer with periodic recalibration - A power saving sleep timer has a first clock and a second clock having greater frequency and temporal stability than the first clock. The second clock has an associated second clock period value which is accumulated once for each said second clock interval during one or more first clock periods, thereby forming a calibrated period value. During an operational interval, the calibrated period value is accumulated once per first clock interval until the accumulated value is equal or greater than a sleep time value, after which a power-up output is asserted. | 08-06-2009 |
| 20090240972 | MODELING RECURRING EVENTS IN A DATA STORE - Time-related properties may be modeled independent of a base object. Rather than storing time properties with the object, they may be stored independently. A given object may be stored once, even if it has a recurrent time property. The description of a “meeting,” for example, may be stored once. Each occurrence of that object over time may be stored in a “timeslot” (object occurs at time ‘t’ on day ‘d’). If it is a recurring property, recurrence information may be stored independently. “Exception” information may be stored independently as well. | 09-24-2009 |
| 20090210740 | OFF-CHIP ACCESS WORKLOAD CHARACTERIZATION METHODOLOGY FOR OPTIMIZING COMPUTING EFFICIENCY - A system, apparatus, and method are provided which allows for reducing power consumption in dynamic voltage and frequency scaled processors while maintaining performance within specified limits. The method includes determining the off-chip stall cycle in a processor for a specified interval in order to characterize a frequency independent application workload in the processor. This current application workload is then used to predict the application workload in the next interval which is in turn used, in conjunction with a specified performance bound, to compute and schedule a desired frequency and voltage to minimize energy consumption within the performance bound. The apparatus combines the aforementioned method within a larger-scale context that reduces the energy consumption of any given computing system that exports a dynamic voltage and frequency scaling interface. The combination of the apparatus and method form the overall system. | 08-20-2009 |
| 20110029802 | INFORMATION PROCESSING SYSTEM - An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit. | 02-03-2011 |
| 20100211813 | Watchdog timer and control method therefor - A watchdog timer includes an execution address detection section comparing a value of a program counter of a central processing unit with an address of a predetermined area, a timer count section having a first overflow time set thereto when the execution address detection section indicates that the value of the program counter has entered the predetermined area, and a counter clear control section generating a request signal for clearing the timer count section when the execution address detection section indicates that the value of the program counter has exited from the predetermined area. | 08-19-2010 |
| 20110119520 | Hardware Function Generator Support in a DSP - The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis. | 05-19-2011 |
| 20100332888 | DERIVING ACCURATE MEDIA POSITION INFORMATION - Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock. | 12-30-2010 |
| 20100037084 | METHOD FOR RECOVERING A POSITION AND CLOCK PERIOD FROM AN INPUT DIGITAL SIGNAL - A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal and is stored, and a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal is provided. | 02-11-2010 |
| 20090307519 | POWER SAVING SCHEDULER FOR TIMED EVENTS - The disclosed system and methods include a power saving scheduler that maintains timed events in an event table. Each timed event has an associated tolerance period within which the event should begin execution following a trigger, and a timestamp indicating a scheduled execution time for the event. When a device is in a low-power sleep mode, a trigger may wake up the device to a wake state. The power scheduler then accesses the event table of upcoming timed events, and reorders the event table from the event having the shortest tolerance period to the event having the longest tolerance period. Each event for which the timestamp is within the tolerance period as measured from the trigger time is executed. After a plurality of such events are executed, the device may return to the sleep mode. | 12-10-2009 |
| 20100037083 | Method for Controlling Time Based Signals - A method controls time based signals that are outputted from at least two processes of unit. A first signal is converted into a first signal value and indicates over a first time range of a first process with a first defined start time and a defined end time, in which present time is signalized by a spatially extensible and uniformly highlighted portion of the first time range defined between the first start time and the present time. A second signal is converted into a second signal value and indicates over a second time range of a second process with a second defined start time and free of an end time, in which the present time is signalized by a spatially extensible portion of the second time range onto which a variably highlighted and superposed section is overlaid, the section being defined between the second start time and the present time. | 02-11-2010 |
| 20100058103 | Apparatus and Method Using First and Second Clocks - Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part. | 03-04-2010 |
| 20110093736 | METHOD AND CIRCUIT FOR TRIMMING AN INTERNAL OSCILLATOR OF A USB DEVICE - A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator. | 04-21-2011 |
| 20110029803 | CLOCK RECOVERY OF SERIAL DATA SIGNAL - A method and a receiver for recovering clock timing information from a serial data signal by determining data symbol transition times. The method comprises determining data symbol transition times of the serial data according to a first determination scheme, and further data symbol transition times of the serial data according to a second determination scheme. The transition times are then combined by a voting process, wherein the first determination scheme votes for the transition times that it determined, and wherein the second determination scheme votes for the transition times that it determined. The actual transition times are then determined as being the times that have the most votes. | 02-03-2011 |
| 20110161716 | SYSTEMS, METHODS, AND APPARATUSES FOR PROVIDING ACCESS TO REAL TIME INFORMATION - Methods, apparatuses, and systems are provided for providing access to real time information. A method may include running an application on top of a virtual platform. The method may further include determining a real time. The real time may define a non-simulation time that is maintained independently of the virtual platform such that the real time is not affected by performance of the virtual platform or of the application running on top of the virtual platform. The method may additionally include providing the determined real time for access by the application. Corresponding apparatuses and systems are also provided. | 06-30-2011 |
| 20110154090 | Controlling Time Stamp Counter (TSC) Offsets For Mulitple Cores And Threads - In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed. | 06-23-2011 |
| 20080222444 | Variable instruction width software programmable data pattern generator - A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state. | 09-11-2008 |
| 20080222443 | Controller - The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( | 09-11-2008 |
| 20110022877 | PWM TIMER FOR POWER SUPPLY - A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds. | 01-27-2011 |
| 20110040999 | TICK SOURCE - A tick source device ( | 02-17-2011 |
| 20090300402 | EMBEDDED SOFTWARE TESTING USING A SINGLE OUTPUT - An integrated circuit includes a processor and a circuit. The processor is configured to execute software. The software includes a plurality of software events. The circuit is configured to output a pulse on a single pin or pad of the integrated circuit in response to executing each software event. A pulse width of each pulse identifies a software event. | 12-03-2009 |
| 20090292939 | BROADCAST/VOD RECEIVER AND VIEWING MANAGEMENT METHOD - According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program. | 11-26-2009 |
| 20100017640 | EFFICIENT TIME-BASED MEMORY COUNTERS - Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of predefined time intervals. Furthermore, a set of pointers may be used to reference the set of arrays of counters. An index is maintained to provide time-based management of the arrays of counters. The index includes a timestamp and the set of pointers. Each pointer logically points to a distinct one of the set of arrays. | 01-21-2010 |
| 20120030499 | Distribution of an incrementing count value - Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount. | 02-02-2012 |
| 20120072760 | TIMER, METHOD OF IMPLEMENTING SYSTEM TIME USING A TIMER, AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset. | 03-22-2012 |
| 20090083568 | TIMER CIRCUIT, MOBILE COMMUNICATION TERMINAL, USING THE SAME, AND ELECTRONIC DEVICE USING THE SAME - In a timer circuit mounted on a mobile communication terminal etc, a plurality of time measurements with different sets of measurement time are realized with measurement errors reduced, and the power consumption is reduced. The timer circuit includes a counter | 03-26-2009 |
| 20090132846 | VIRTUAL MACHINE MONITOR, VIRTUAL MACHINE SYSTEM AND CLOCK DISTRIBUTION METHOD THEREOF - A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock resource; intercepting an access operation of said GOS to a virtual clock resource; sending said access operation to the corresponding real clock resource according to said correspondence, and then performing a write operation, or injecting an interrupt of said real clock resource into a local Advanced Programmable Interrupt Controllers (APIC) of a virtual CPU of the corresponding GOS of said GOSs. | 05-21-2009 |
| 20120166862 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY AND A MEMORY DEVICE - A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 06-28-2012 |
| 20100058102 | Methods for Managing the Transmission and Reception of Data Fragments - This invention relates to methods for managing the transmission and reception of data fragments that contains one or more data blocks using a single timer. The methods include the following steps: A method for managing the transceiving of data fragments, comprising the steps of: processing said fragments sequentially, wherein each fragment having a processing index that corresponds to the sequential processing of that fragment; processing each of said fragments until a termination upon the meeting of a first pre-defined condition; assigning a timer to an un-terminated fragment having the lowest processing index; starting said timer having a timeout value; and running said timer until the processing of said un-terminated fragment is terminated. The methods of this invention use only one timer for each connection and therefore reduce memory and operational needs in the management of the data fragments that are being received or transmitted. | 03-04-2010 |
| 20100011237 | Controlling real time during embedded system development - Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock. | 01-14-2010 |
| 20080301484 | INFORMATION PROCESSING DEVICE - An information processing device, such as cellular phone, includes a first timer set for executing count processing applied to a preassigned first processing, a second timer set for executing count processing applied to the preassigned first processing, a display state determination unit configured to determine a display state of a display unit, and a timer switching unit configured to select and set the first timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “ON” state and to select and set the second timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “OFF” state. | 12-04-2008 |
| 20120331331 | MICROCONTROLLER AND CONTROL METHOD THEREFOR - A microcontroller includes a first voltage detector that detects whether a power supply voltage is equal to or lower than a first voltage value to generate a first signal, a second voltage detector that detects whether the power supply voltage is equal to or lower than a second voltage value to generate a second signal, the second voltage value being lower than the first voltage value, a real-time clock that includes a memory and a clock counter responsive to a clock signal, and a Central Processing Unit (CPU) that receives the first signal. The first voltage detector, the second voltage detector, the real-time clock and the CPU are formed on a single chip. The clock counter receives the second signal. The memory stores a first value according to a second signal, and stores a second value according to a setup of time information to the clock counter. | 12-27-2012 |
| 20110239033 | Bus Interface and Clock Frequency Control Method of Bus Interface - A bus interface includes a chip select terminal, a first transmission bus terminal, a second transmission bus terminal, and a clock control device. The chip select terminal transmits a chip select signal to start the data transmission. When the data transmission starts, the first transmission bus terminal sends data to the second device, and the second transmission bus terminal sends the data from the second device to the first device. The clock control device includes a frequency processing unit and a transmission clock generating unit. The frequency processing unit outputs a clock control signal when a frequency to set value changes. The transmission clock generating unit receives the clock control signal and generates a transmission clock in accordance with the frequency setting value. | 09-29-2011 |
| 20120278648 | TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP - An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address. | 11-01-2012 |
| 20110161717 | IMAGE FORMING APPARATUS - Even in a case where a master-CPU of an image forming section and a slave-CPU of a sheet transportation section are driven by respective oscillation circuits with different oscillation accuracies, a large difference in accuracy is not caused in transfer sheet transportation speed driven by clock signals formed by the respective oscillation circuits. In the master-CPU and the slave-CPU that are cascadingly connected to each other, in order to calculate a clock frequency of an oscillation circuit of the target-CPU, a predetermined time transmitted from the other CPU connected to the target-CPU is counted by the clock signal of the target-CPU. With reference to the predetermined time, an operating process, such as division of an acquired counter value by the predetermined time, acquires an error of the clock frequency of the oscillation circuit driving the slave-CPU, and corrects the error, thereby improving the accuracy thereof. | 06-30-2011 |
