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CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS

Subclass of:

713 - Electrical computers and digital processing systems: support

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
713501000 Multiple or variable intervals or frequencies 88
713502000 Counting, scheduling, or event timing 63
713503000 Correction for skew, phase, or rate 62
Entries
DocumentTitleDate
20090193281APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS - A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.07-30-2009
20090193282Method for processing time values in a computer or programmable machine - Modern computers (07-30-2009
20100077248CLOCK GENERATING DEVICE, METHOD THEREOF AND COMPUTER SYSTEM USING THE SAME BACKGROUND OF THE INVENTION - A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.03-25-2010
20130080818CONVERSION OF TIMESTAMPS BETWEEN MULTIPLE ENTITIES WITHIN A COMPUTING SYSTEM - Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.03-28-2013
20100037080PORTABLE TERMINAL DEVICE - A portable terminal device includes a supplying unit for supplying, to a CPR, an operating frequency of a clock signal used to operate the CPU, a setting unit for setting one cock level out of a plurality of clock levels assigned with the operating frequency in accordance with an operating state of the CPU and changing an operating frequency stepwise at the clock levels to set the clock level of the operating frequency, a control unit for controlling the operating frequency supplied to the CPU at the clock levels based on settings made by the setting unit, and an input accepting unit for accepting a key input. If the input accepting unit accepts the key input, the setting unit sets the clock level to a predetermined level irrespective of an operating state of the CPU.02-11-2010
20090158076TECHNIQUE TO IMPLEMENT CLOCK-GATING - A system and method for providing clock gating while reducing area and power on an integrated circuit (IC) chip. An array of registers or memory cells may have a single clock gating circuit, rather than multiple circuits such as one clock gating circuit for each bit of storage. The single clock gating circuit may be larger in size than each of the multiple clock gating circuits, but the single clock gating circuit may still have less capacitive loading. A reduction in overall allocated area allows floorplanning to offer less congested signal routing. Clock generation circuitry may be configured to provide a clock signal from a last ungated stage to clock enabling circuitry. A power reduction control unit may be configured to determine when the last ungated stage clock waveform is enabled/disabled within the clock gating circuitry.06-18-2009
20090158077Circuit and method for generation of duty cycle independent core clock - A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock.06-18-2009
20090125748Methods for the Support of JTAG for Source Synchronous Interfaces - Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.05-14-2009
20110010574Security device meant to be connected to a processing unit for audio/video signal and method using such a device - The invention relates to a security device intended to be connected to a processing unit for an audio/video signal. This device comprises means to decrypt an audio/video stream, an interface of the ISO 7816 type and at least one high speed serial communication interface. It is characterised in that it includes a clock frequency detection module connected to a clock input of the 7816 interface, this detection module comprising means to distinguish the input frequency according to at least two different frequency ranges, the different frequency ranges activating the different communication functions.01-13-2011
20090307517Apparatus and Method for Processing Wirelessly Communicated Data and Clock Information Within an Electronic Device - An electronic device (12-10-2009
20090094474INFORMATION PROCESSING DEVICE - An information processing device controls an access unit which accesses a memory corresponding to an address space where an address belongs, the address being generated using at least two pieces of address generation source information. The information processing device includes: a prediction unit which predicts one or more address spaces where the address to be accessed may potentially belong, using one piece of the address generation source information; an activation unit which activates accesses from the access unit to memories corresponding to all the address spaces predicted by the prediction unit; a determination unit which determines the address space where the address to be accessed belongs, the address being generated using the at least two pieces of the address generation source information; and an access stop unit which stops the accesses from the access unit, except for the access corresponding to the address space determined by the determination unit, out of the accesses activated under control of the activation unit.04-09-2009
20090070619MULTI-CYCLE PATH INFORMATION VERIFICATION METHOD AND MULTI-CYCLE PATH INFORMATION VERIFICATION DEVICE - For example, multi-cycle path information is extracted from a logic synthesis constraint (S03-12-2009
20110022875Integrated Circuit with Interpolation to Avoid Harmonic Interference - An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.01-27-2011
20110022874DATA PROCESSING SYSTEM AND ADJUSTING METHOD THEREOF - A data processing system and an adjusting method thereof are disclosed. The data processing system includes a processor, a clock generator, a monitoring module and a determining module. When a target program is processed, the monitoring module monitors a first loading level of the processor, and transmits the first loading level to the determining module for recording. Furthermore, when a present program is processed, the monitoring module monitors a second loading level of the processor, and transmits the second loading level to the determining module. The determining module determines whether the second loading level matches with the first loading level within a preset period, and if it matches, the determining module generates and transmits a control signal to the clock generator, thereby making the clock generator generates a first clock signal to the processor, so as to increase the operating frequency of the processor.01-27-2011
20090265572FAST ADAPTIVE VOLTAGE SCALING - A method, digital circuit, and computer program product control a supply voltage of a processing circuit based on a processing clock of the processing circuit. A first clock frequency and at least one second clock frequency are generated, wherein the first clock frequency is used as the processing clock and the second clock frequency is adjusted based on a clock control information issued by the processing circuit. A voltage conversion ratio for converting the supply voltage to a scaled supply voltage applied to the processing circuit is directly controlled in response to the result of a monitored performance under said second clock frequency. Thereby, a new fast automatic voltage scaling approach can be provided which allows to meet critical timing requirements of portable systems and to reduce power consumption significantly.10-22-2009
20090235109HYBRID COMPUTER SECURITY CLOCK - A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every read of the monotonic time from the clock object. The clock object can also include an indication of a level of trust of the clock time.09-17-2009
20090235108AUTOMATIC PROCESSOR OVERCLOCKING - Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.09-17-2009
20090013205Information Leakage Prevention Apparatus and Information Leakage Prevention Method - A clock signal extractor (01-08-2009
20130166939APPARATUS, SYSTEM, AND METHOD FOR PROVIDING CLOCK SIGNAL ON DEMAND - Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently.06-27-2013
20130166940SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.06-27-2013
20100223487Time Synchronization of Master and Slave Devices - A time synchronized measurement system has a master device and a slave device. The master device and the slave device each have a time measurement device for assigning a corresponding time of sending and/or receiving a piece of measurement information. The master device also has a reference clock pulse-generating device for transmitting a reference clock signal to the slave device. The reference clock signal is modulated by a piece of information on a common time basis for the master device and the slave device.09-02-2010
20100268978APPARATUS AND METHOD TO INTERFACE TWO DIFFERENT CLOCK DOMAINS - A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.10-21-2010
20080209249Use of a UUID as a Time Epoch to Determine if the System Clock Has Been Reset Backwards in Time - A method, system and program are provided for determining if a system clock has been reset backwards in time by using a randomly generated set of bytes (such as a randomly generated or type 4 UUID) as a time epoch. By generating a time epoch at boot time and whenever the system clock is set back in time, an application can compare the time epoch value at an earlier point in its execution, with the current time epoch. If the time epoch values are different, the application will know that the system clock has been set back in time.08-28-2008
20090049326CLOCK SIGNAL GENERATOR FOR GENERATING STABLE CLOCK SIGNAL, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHODS OF OPERATING - A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.02-19-2009
20100023794APPARATUS AND METHOD OF GENERATING POWER-UP SIGNAL OF SEMICONDUCTOR MEMORY APPARATUS - An apparatus for generating a power-up signal of a semiconductor memory apparatus includes a first power-up signal generator that generates a first power-up signal to be activated on the basis of a comparison between a power supply voltage level supplied to the semiconductor memory apparatus and a first set voltage level, and a second power-up signal generator that generates a second power-up signal to be activated with a predetermined delay time on the basis of a comparison between the power supply voltage level and a second set voltage level.01-28-2010
20100169697Control Device Having Output Pin Expansion Function and Output Pin Expansion Method - A control device having an output pin expansion function and an output pin expansion method thereof are provided. The method includes: connecting at least a shift register unit having a plurality of data transmission pins to a control unit such that the shift register unit can receive strobe signals, a multi-bit data stream, clock signals and enable signals generated by the control unit; sending an enable signal by the control unit so as to allow the shift register unit to shift and store each bit of a multi-bit data stream according to a clock signal generated by the control unit; and sending a strobe signal by the control unit so as to allow the shift register unit to output the multi-bit data in parallel format as opposed to the received serial format through the plurality of data transmission pins, thereby allowing a processing device to interface with more devices (such as LED state indicators) than its fixed number of dedicated output pins would conveniently allow, thus saving costs and board space.07-01-2010
20090319817Clock Selection for a Communications Processor having a Sleep Mode - A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.12-24-2009
20100268977METHOD AND APPARATUS FOR ACCESSING MEMORY UNITS - An apparatus for accessing a memory is provided, and comprises a first device, a second device, an adjusting unit, a buffer and a memory. The first device operates at a first clock. The second device operates at a second clock. The buffer reads data from the second device to be written to the memory unit and reads from the memory unit to be read by the first device. The adjusting unit masks a portion of pulses of the first clock to generate an adjusted clock, wherein the first device reads the buffer according to the adjusted clock. The apparatus for accessing a memory is a video processor, and the first device and the second device are an input unit and an output unit of the video processor.10-21-2010
20080215907Method and apparatus for the generation and control of clock signals - Methods and apparatuses for the dynamic configuring of profiles used for the control of the frequency of clock signals. At least one embodiment of the present invention provides a means of dynamically generating, storing, updating and using spread spectrum profiles in a clock circuit to provide spread spectrum modulated clock signals and to slew clock frequency.09-04-2008
20120036389Precision Oscillator for an Asynchronous Transmission System - A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART.02-09-2012
20110173480SYSTEMS, METHODS, SOFTWARE, AND COMPONENTS USING TAMPER-PROOF REAL-TIME CLOCK - The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.07-14-2011
20110197086DATA PROCESSING UNIT AND A METHOD OF PROCESSING DATA - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.08-11-2011
20110271134Apparatus and Methods Employing Variable Clock Gating Hysteresis for a Communications Port - An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.11-03-2011
20120297232ADJUSTING THE CLOCK FREQUENCY OF A PROCESSING UNIT IN REAL-TIME BASED ON A FREQUENCY SENSITIVITY VALUE - A system, method, and medium for adjusting an input clock frequency of a processor in real-time based on one or more hardware metrics. First, the processor is characterized for a plurality of workloads. Next, the frequency sensitivity value of the processor for each of the workloads is calculated. Hardware metrics are also monitored and the values of these metrics are stored for each of the workloads. Then, linear or polynomial regression is performed to match the metrics to the frequency sensitivity of the processor. The linear or polynomial regression will produce a formula and coefficients, and the coefficients are applied to the metrics in real-time to calculate a frequency sensitivity value of an application executing on the processor. Then, the frequency sensitivity value is utilized to determine whether to adjust the input clock frequency of the processor.11-22-2012
20110208988Latency signal generator and method thereof - A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.08-25-2011
20080244301REAL-TIME CLOCK CORRECTION METHODS AND APPARATUS - A real-time clock (RTC) correction method is provided. Correction data for correcting an RTC of the electronic device is calculated and stored before a power off operation of an electronic device. When the power off operation is performed between two correction operations of the RTC, the period between the two correction operations of the RTC is also calculated. The RTC is corrected utilizing the correction data and the period.10-02-2008
20080288806Clock generation circuit and semiconductor memory apparatus having the same - A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.11-20-2008
20080276113ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING SAME - An electronic apparatus with a wireless unit includes a multiplier to receive a clock signal at a predetermined frequency. The electronic apparatus further includes a modulator configured to modulate the frequency of the clock signal generated by the multiplier, and a controller configured to change the frequency of the clock signal generated by the multiplier and a modulation rate of the modulation performed by the modulator according to a state of the electronic apparatus.11-06-2008
20120144224Adjusting a Device Clock Source to Reduce Wireless Communication Interference - Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.06-07-2012
20080282103Lightweight time change detection - A timer service uses a single timer function to perform timing services for both relative and absolute timers. The first timers from a sorted array of absolute timers and relative timers are used in a function that will return when the earliest absolute timer expires or will timeout when the earliest relative timer expires. The timer function may be interrupted when a new timer is added to one of the arrays. The function will operate in a predictable and consistent manner, even when a system clock is adjusted.11-13-2008
20080270818Serial Communication Interface with Low Clock Skew - A communication interface for use in an integrated circuit comprises a clock root circuit (10-30-2008
20090164827METHOD AND APPARATUS FOR GENERATING OR UTILIZING ONE OR MORE CYCLE-SWALLOWED CLOCK SIGNALS - An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is configured to generate a second clock signal having a second frequency and configured to swallow one or more clock cycles of the first clock signal in generating the second clock signal. The first clock signal has even cycles, and the second clock signal has uneven cycles. The first frequency is greater than the second frequency. The module may include a cycle-swallowing counter. A method and a computer-readable medium are also provided.06-25-2009
20090259875Store Clock and Store Clock Fast Instruction Execution - Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results.10-15-2009
20090259874DATA TRANSFER DEVICE AND METHOD THEREOF - A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.10-15-2009
20110231693NUMERICALLY CONTROLLED OSCILLATOR AND OSCILLATION METHOD FOR GENERATING FUNCTION VALUES USING RECURRENCE EQUATION - Numerically controlled oscillators and oscillation methods for generating function values in respective clock cycles by using a recurrence equation are provided. The oscillation circuit generates, in each of the clock cycles, a current one of the function values by multiplying, using a multiplier having a latency of k clock cycles, a first one of the function values generated in a first one of the clock cycles that is j cycles before a current one of the clock cycles by a coefficient and adding an output of the multiplier and at least one of the function values generated in previous ones of the clock cycles that are 1 to i−1 cycles before the current one of the clock cycles excluding the first one of the clock cycles, where 209-22-2011
20110231694DATA PROCESSING DEVICE AND MOBILE DEVICE - A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.09-22-2011
20080263381DYNAMIC PHASE ALIGNMENT - A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal.10-23-2008
20090240970CLOCK DISTRIBUTION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.09-24-2009
20090222685DISTRIBUTED SYNCHRONIZATION AND TIMING SYSTEM - A method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a periodic data structure containing information about the frequency and phase of a distributed clock frequency, and phase and circuitry for receiving the periodic data structure and generating from at least the periodic data structure a local clock signal locked in both frequency and phase to the periodic data structure. The circuitry for receiving the periodic data structure and generating the local clock signal can generate the local clock signal with a frequency that is a non-integral multiple of a frequency of the periodic data structure.09-03-2009
20100180142METHOD, CAN BUS DRIVER AND CAN BUS SYSTEM FOR THE RECOVERY OF A CLOCK FREQUENCY OF A CAN BUS - A method, a CAN bus driver and a CAN bus system for the recovery of a clock frequency of a CAN bus, which couples a master device, that has a clock generator for providing the clock frequency, to at least one slave device. A phase-locked loop is used in the slave device, in this context, which utilizes a predetermined bit pattern, that is extracted from a frame sent by the master device via the bus system, as reference signal.07-15-2010
20090094475DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE - A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.04-09-2009
20100174936Communicating Via An In-Die Interconnect - In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.07-08-2010
20100235673SIMPLIFIED RECEIVER FOR USE IN MULTI-WIRE COMMUNICATION - An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs.09-16-2010
20100250997INTEGRATED CIRCUIT HAVING FREQUENCY DEPENDENT NOISE AVOIDANCE - An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.09-30-2010
20100250996Preventing Hangs in a System with Synchronized Operation Using Stalls - This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention selects a set of the finite state machines to participate in an operation. If one or more of the finite state machines are selected for operation, the method waits until all selected finite state machines generate the ready signal. If none of the finite state machines are selected for operation, the method waits until at least one non-selected finite state machine generates the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.09-30-2010
20090113230SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.04-30-2009
20100223488STORAGE APPARATUS AND METHOD OF CONTROLLING STORAGE APPARATUS - A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.09-02-2010
20120144225VERIFICATION - A circuit simulator includes at least one clock generator. The at least one clock generator is configured to generate at least one root clock signal for an associated clock domain part of the circuit under simulation. The circuit simulator also includes a clock modifier configured to generate at least one delay to be applied to at least one of the at least one root clock signal.06-07-2012
20100306568SYMMETRICAL CLOCK DISTRIBUTION IN MULTI-STAGE HIGH SPEED DATA CONVERSION CIRCUITS - Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).12-02-2010
20100313058System and Method of Clocking an IP Core During a Debugging Operation - According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.12-09-2010
20130145197METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY MODULE - A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.06-06-2013
20110010575MULTI-DROP SIGNALING SYSTEM AND METHOD EMPLOYING SOURCE TERMINATION - A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order.01-13-2011
20090031159On-chip logic analyzer using compression - One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.01-29-2009
20090327791METHOD OF PROVIDING A CLOCK FREQUENCY FOR A PROCESSOR - A method of providing a clock frequency to a processor is described. The method in accordance with the invention comprises the step of providing at least one reference signal and the step of determining a control value which relates to a desired first frequency. A second signal that relates to the control value is then used in a subsequent step as an input signal for a noise shaper. Then, a first signal which has the first frequency is generated by combining the output of the noise shaper with one of the at least one reference signals. The first signal is used as a clock frequency of the processor. In a preferred embodiment, one reference signal with a fixed reference frequency is provided. The reference signal is gated or enabled and hold by the output signal provided by a 1-bit noise shaper, whereby the first frequency is generated which is then used as processor clock frequency. The method in accordance with the invention is particularly advantageous as it allows for the control of the processor's clock frequency via the second signal that is fed into the noise shaper.12-31-2009
20110252266KEEPING TIME IN MULTI-PROCESSOR VIRTUALIZATION ENVIRONMENTS - A virtual machine receives a request for a current time. The virtual machine determines an approximation of the current time based on readings from one of a plurality of processors and compares the approximation to a virtual machine time stamp value. If the approximation is smaller than the virtual machine time stamp value, the virtual machine returns the global time stamp value as the current time and if the approximation is not smaller than the virtual machine time stamp value, the virtual machine returns the approximation as the current time.10-13-2011
20100058101SYSTEM AND METHOD FOR REDUCING LATENCY ASSOCIATED WITH TIMESTAMPS IN A MULTI-CORE, MULTI-THREADED PROCESSOR - A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.03-04-2010
20090217075Signal Phase Verification for Systems Incorporating Two Synchronous Clock Domains - The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violation in device under test designs comprising two different clock domains where the fast clock is an integer multiple of the slow clock by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainly of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.08-27-2009
20110214004PACKAGED CIRCUIT - A packaged circuit includes an internal circuit, an embedded clock generator, a plurality of multi-function pins and a control pad. The embedded clock generator is for generating an internal clock. The pins include a clock output pin and a clock input pin. The clock output pin outputs the internal clock generated by the embedded clock generator. The clock input pin is for receiving an external clock. The control pad receives a control signal to determine whether the internal circuit utilizes a system clock according to the internal clock generated by the embedded clock generator or the external clock received by the clock input pin.09-01-2011
20110072297SPI DEVICES AND METHOD FOR TRANSFERRING DATA BETWEEN THE SPI DEVICES - A method for transferring data between a serial peripheral interface (SPI) master device and an SPI slave device generates a first clock signal for the SPI master device and a second clock signal for the SPI slave device. Clock frequency of the first clock signal and the second clock signal is twice than a serial clock signal between the SPI master device and the SPI slave device. Data are transferred with double data rate or single data rate based on the first clock signal and the second clock signal.03-24-2011
20110060935Generating A Random Number In An Existing System On Chip - A system for generating a true random number and implemented within an existing System on Chip (SoC) is provided herein. The system includes one or more sub circuitry synchronous modules configured to operate in a specified nominal clock rate, wherein each sub circuitry synchronous modules yields expected deterministic results when operating in its nominal clock rate; and a control module configured to clock the one or more sub circuitry synchronous modules each in a clock rate higher than its respective the nominal clock rate and beyond a specified value, to yield a non deterministic behavior of the one or more sub circuitry synchronous modules, resulting in one or more random signals, wherein the system is implemented within an existing system on chip (SOC).03-10-2011
20100325467MEMORY SYSTEM AND CONTROLLER - A memory system, which is connected to a host device, includes a memory, a host interface which receives a command and an address, which are output from the host device, and a controller which operates in one of a first mode in which the controller converts the address which is received by the host interface and accesses the memory by using the converted address, and a second mode in which the host device directly accesses the memory by using the address which is received by the host interface, the controller controlling switching between the first mode and second mode in accordance with the command.12-23-2010
20100313057CLOCK SIGNAL TEST APPARATUS AND METHOD - A clock signal test apparatus for testing a computer system includes a frequency generator to generate a clock pulse signal, a real-time clock (RTC) chip to receive the clock pulse signal from the frequency generator, and a micro control unit (MCU). The MCU is to receive a test command signal from the computer system to set a first current time of the RTC chip equal to a current system time of the computer system, and to receive a time comparing command from the computer system after a test interval to retrieve a second current time of the RTC chip and transmit the second current time of the RTC chip to the computer system.12-09-2010
20090006881Data fetch circuit, data fetch system and control method of the data fetch circuit - To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 01-01-2009
20110258476APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.10-20-2011
20080307247Time Certifying Server, Reference Time Distributing Server, Time Certifying Method, Reference Time Distributing Method, Time Certifying Program, and Communication Protocol Program - An object is to perform time certification at a low cost while ensuring high precision and high reliability. In a time stamp server according to the present embodiment, a time is measured by the unit of, for example, 100 milliseconds, and a time stamp is issued by using the time. However, what is important is generally a date in a time stamp although it depends on a certification target. Therefore, it is thought that no adverse affect occurs substantially, even if a second hand is doctored. Accordingly, in the present embodiment, the time measured by the internal clock of the time stamp server is divided into a part regarding the units equal to or larger than the unit of minute (year, month, day, minute) and a part regarding the unit of second (including the units smaller than one second, such as millisecond), and the part regarding the units equal to or larger than the unit of minute is audited by an auditory office, whereas the part regarding the unit of second is synchronized with a time distributed from a time distributing office. That is, as to the part regarding the units equal to or larger than the unit of minute, the coincidence with the reference time is confirmed, whereas the part regarding the unit of second is corrected by using the time distributed from the time distributing office.12-11-2008
20090049325DATA PROCESSOR - It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 02-19-2009
20080276114Micro-controller having USB control unit, MC unit and oscillating circuit commonly used by the USB control unit and the MC unit - A micro-controller includes a USB control unit, an MC unit having an operation mode and a stop mode and an oscillating circuit, which is commonly used by the USB control unit and the MC unit. The USB control unit includes a watching circuit for watching a condition of a first data and a second data, which is complement data of the first data. The operation of the oscillating circuit is controlled in response to an operation control signal, which is generated by a watching result, and an oscillation control signal whose voltage level is changed in response to the mode of the MC unit.11-06-2008
20110047401Providing Adaptive Frequency Control For A Processor - In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.02-24-2011
20080209250Single wire communication circuits and methods - Embodiments of the present invention include systems and methods of control using a single wire. The systems and methods presented allow sending or receiving commands and data through a single wire. In one embodiment, commands and data are received by the control system through a single terminal. In another embodiment, commands and data are received and transmitted from the control system through a single terminal.08-28-2008
20080256379Clock architecture for multi-processor systems - In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.10-16-2008
20080256380SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME - A functional block is divided into a plurality of regions. In each region, a clock main line extending along a first direction, a clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the clock main line, a clock driving cell electrically connected to the clock main line and a clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the clock main line or the clock branch line group are provided. The clock branch line groups of the respective regions are electrically separated from each other, and the clock driving cell singly drives the clock main line connected thereto and the clock branch line group connected to the clock main line.10-16-2008
20110138215CLOCK SIGNAL GENERATING DEVICE AND ELECTRONIC DEVICE - To provide a clock signal generating device that changes the frequency of a predetermined clock signal in a short time and prevents or mitigates instability in the operation of the supply destinations of the clock signal when the frequency of the clock signal is changing.06-09-2011
20110138214CLOCK GENERATOR AND USB MODULE - A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.06-09-2011
20110191620MULTICORE PROCESSOR AND ONBOARD ELECTRONIC CONTROL UNIT USING SAME - A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.08-04-2011
20110191619Reducing Latency in Serializer-Deserializer Links - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.08-04-2011
20110040998Oversampling-Based Scheme for Synchronous Interface Communication - In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.02-17-2011
20100122105RECONFIGURABLE INSTRUCTION CELL ARRAY - A reconfigurable processor architecture, compiler and method of program instruction execution provides reduced cost, short design time, low power consumption and high performance. The processor executes program instructions having datapaths of both dependent and independent program instructions. Simultaneous multithreading is also Interconnects Network supported. The processor has a reconfigurable core (05-13-2010
20110093735Semiconductor memory device, method of adjusting the same and information processing system including the same - Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.04-21-2011
20100192003Method and apparatus for supporting client data transport with timing transparency - Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.07-29-2010
20120042192Frequency Reference Correction for Temperature-Frequency Hysteresis Error - A method is disclosed for improving the effective frequency stability of a frequency reference source, wherein an algorithm utilizing parameters determined from frequency and temperature sensing measurements of the source or a similar source over a number of temperature excursions of different magnitude is used in conjunction with temperature history to correct the frequency reference output accounting for effects of hysteresis in the frequency-temperature characteristic of the source. Devices and manufacturing systems are also claimed.02-16-2012
20090070618SYSTEM AND METHOD FOR CALIBRATING A TOD CLOCK - A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The system implements steps for obtaining samples of timing values of a computing device in the network, the values including a physical clock value maintained at that device and a TOD-offset value; computing an oscillator skew value from the samples; setting a fine steering rate value as equal to the opposite of the computed oscillator skew value; and, utilizing the fine steering rate value to adjust the physical clock value and correct for potential oscillator skew errors occurring in the oscillator crystal at the computing device.03-12-2009
20120210157INTERFACE CLOCK MANAGEMENT - The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.08-16-2012
20120005517SYNCHRONISATION AND TIMING METHOD AND APPARATUS - A method and system for synchronising a first device and at least one second device, each having a local oscillator and a microcontroller, and the second device being in data communication with the first device via a communication bus. The method comprises the first device transmitting a plurality of signals to the second device, the second device using the plurality of signals to measure the frequency of its local oscillator, the first device transmitting a signal to the second device indicative of a required frequency to be synchronised to, and the second device employing its microcontroller to configure itself to generate a local clock signal with the required frequency using the frequency of its local oscillator.01-05-2012
20120023358HOST DEVICE, PERIPHERAL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD - In a communication system in which data is transmitted and received in synchronization with a clock signal, a peripheral device cannot transfer data to a host device when the host device stops outputting the clock signal and thus the peripheral device cannot promptly transmit an interrupt request to the host device. A peripheral device transmits an interrupt request to a host device using a signal line for a clock signal when the clock signal output has been stopped. The host device receives the interrupt request, and resumes outputting a clock signal to enable data transmission and reception to and from the peripheral device. This enables the peripheral device to transmit an interrupt request to the host device promptly when the output of the clock signal from the host device has been stopped.01-26-2012
20120166858Apparatus and Method for Processing Wirelessly Communicated Data and Clock Information Within an Electronic Device - An electronic device (06-28-2012
20120233488ADJUSTMENT OF A PROCESSOR FREQUENCY - A system comprises a processor, a connection to the processor, a monitoring component arranged to monitor the connection to the processor, a performance counter connected to the monitoring component and arranged to establish a ratio between processor idle time and processor busy time, and a policy component connected to the performance counter and the processor, and arranged to adjust the processor frequency according to the established ratio of processor idle time to processor busy time.09-13-2012
20120084593METHOD AND SYSTEM FOR PROVIDING A CURRENT TIME VALUE - A method for providing applications with a current time value includes receiving a trap for an application to access a time memory page, creating, in a memory map corresponding to the application, a mapping between an address space of the application and the time memory page in response to the trap, accessing, based on the trap, a hardware clock to obtain a time value, and updating the time memory page with the time value. The application reads the time value from the time memory page using the memory map.04-05-2012
20120221882Reducing Latency In Serializer-Deserializer Links - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.08-30-2012
20120239962METHOD AND A DEVICE FOR CONTROLLING A CLOCK SIGNAL GENERATOR - A device for controlling a clock signal generator includes a processor (09-20-2012
20110239032CONVOLUTION OPERATION CIRCUIT AND OBJECT RECOGNITION APPARATUS - In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder.09-29-2011
20110320853COMMUNICATION INTERFACE DEVICE AND COMMUNICATION METHOD - A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal12-29-2011
20110320852CLOCK CIRCUIT AND RESET CIRCUIT AND METHOD THEREOF - A clock circuit is suitable for use in a timing circuit which provides time information according to a reference clock. The clock circuit includes a clock detector to detect whether or not an interruption of the reference clock occurs. When the interruption of the reference clock occurs, a clock interruption signal is issued as a reference whether or not to reset the timing circuit.12-29-2011
20120102353DATA PROCESSING APPARATUS, DATA PROCESSING SYSTEM, MEASUREMENT SYSTEM, DATA PROCESSING METHOD, MEASUREMENT METHOD, ELECTRONIC DEVICE AND RECORDING MEDIUM - Provided is a data processing system that processes input data, comprising a data generating apparatus that generates the input data and a data processing apparatus that processes the input data generated by the data generating apparatus. The data processing apparatus includes a time interpolation section that generates time interpolated data, in which level differences between pieces of data adjacent in time are a constant value, based on the input data.04-26-2012
20100199119COMPUTER SYSTEM AND METHOD FOR OVERCLOCKING THE SAME - A computer system includes a clock generator, a system chipset, a controller and a multiplexing unit. The clock generator generates a reference clock according to a plurality of setting values in a frequency setting table. The system chipset generates a piece of first clock control information and a first clock. The controller is used to switch the level of the control signal and generates a piece of second clock control information and a second clock. The multiplexing unit is used to receive the control signal to select either the first clock control information or the second clock control information to be a piece of main clock control information and select either the first clock or the second clock to be a main clock. The clock generator adjusts the setting values according to the main clock control information and the main clock to change the frequency of the reference clock.08-05-2010
20100199118MICROCONTROLLER WITH COMPATIBILITY MODE - A microcontroller is operable to enable a compatibility mode where a clock source of the microcontroller is adjusted to support timing requirements of applications written for legacy microcontrollers. In some implementations, one or more scaling factors and/or wait state factors are applied to the clock source of the microcontroller to ensure timing compatibility.08-05-2010
20130019120METHOD AND SYSTEM FOR REDUCING THERMAL LOAD BY FORCED POWER COLLAPSEAANM SALSBERY; BrianAACI SuperiorAAST COAACO USAAGP SALSBERY; Brian Superior CO USAANM Medrano; Christopher LeeAACI LongmontAAST COAACO USAAGP Medrano; Christopher Lee Longmont CO US - A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t01-17-2013
20130091375Advanced Array Local Clock Buffer Base Block Circuit - A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.04-11-2013
20130097452COMPUTER APPARATUS AND RESETTING METHOD FOR REAL TIME CLOCK THEREOF - A computer apparatus and a resetting method for a real time clock (RTC) of the computer apparatus are provided. The resetting method for the RTC includes: generating a judging result by determining whether the computer apparatus is in an S04-18-2013
20130124907CLOCK GATING CIRCUIT AND BUS SYSTEM - The present technology provides an excellent advantageous effect in terms of reducing power consumption of a bus system adapted to treat a transaction as a unit. Disclosed herein is a clock gating circuit including: a clock enable signal generation portion adapted to count the number of outstanding transactions in each of a plurality of regions into which a bus system is divided so as to generate a clock enable signal for each of the plurality of regions; and a masked clock generation portion adapted to mask a clock by using the clock enable signal for each of the plurality of regions so as to generate a masked clock.05-16-2013
20130124906SIGNAL COLLECTION SYSTEM WITH FREQUENCY REDUCTION UNIT AND SIGNAL COLLECTION METHOD - An exemplary signal collection system includes a signal transmitting module and a computer. The signal transmitting module outputs a high-speed signal with a high frequency. The signal collection system further includes a data collection module interconnecting the signal transmitting module and the computer. The data collection module includes a frequency reduction unit. The frequency reduction unit reduces the frequency of the high-speed signal output from the signal transmitting module and outputs the high-speed signal with a reduced frequency to the computer. A signal collection method based upon the signal collection system is also disclosed.05-16-2013
20130124905SENSE AMPLIFIER AND METHOD FOR DETERMINING VALUES OF VOLTAGES ON BIT-LINE PAIR - A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.05-16-2013
20110231692Programmable Drive Strength in Memory Signaling - Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.09-22-2011
20110239031MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.09-29-2011
20130151883METHOD AND DEVICES FOR CONTROLLING OPERATIONS OF A CENTRAL PROCESSING UNIT - Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry controls (06-13-2013
20100313056Secure Computing Device with Monotonic Counter and Method Therefor - A secure computing device (12-09-2010
20130191677Regional Clock Gating and Dithering - A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.07-25-2013

Patent applications in class CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS

Patent applications in all subclasses CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS