Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES

Subclass of:

713 - Electrical computers and digital processing systems: support

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
713401000 Using delay 90
Entries
DocumentTitleDate
20090193280Method and System for In-doubt Resolution in Transaction Processing - A method and system are provided for in-doubt resolution in transaction processing involving at least two distributed transaction processing systems. The method includes a resynchronization method when re-establishing a connection between two distributed transaction processing systems. The method includes re-establishing a connection between a first transaction processing system and a second transaction processing system following a failure; the first transaction processing system searching for any unresolved units of recovery and resynchronizing each unresolved unit of recovery with the second transaction processing system; and when the first transaction processing system has finished processing its unresolved units of recovery, the second transaction processing system then searches for any unresolved units of recovery and resynchronizes each unresolved unit of recovery with the first transaction processing system.07-30-2009
20100083024Electronics Device Having Timekeeping Function and Computer-Readable Record Medium Storing Program for Timekeeping Function - An electronics device comprising a time information acquisition unit which acquires time information representing present time from an external device, an update unit which updates reference time stored in a reference time storage unit to time represented by the latest time information acquired by the time information acquisition unit each time the time information is acquired, a counter circuit which is formed by hardware and updates its count value at fixed cycles, an elapsed time measurement unit which measures an elapsed time since the update of the reference time by use of the counter circuit, a present time calculation unit which calculates present time by adding the elapsed time to the reference time stored in the reference time storage unit, and a response unit which makes the present time calculation unit calculate the present time and outputs the calculated present time if a present time output request is issued.04-01-2010
20110202785METHOD AND DEVICE FOR SYNCHRONIZING DATA BROADCASTS - A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is provided. After a data word has been sent, a synchronizer in the transmitting data processing unit collects an acknowledge signal from each of the receiving data processing units and then generates an indication that the next data word can be transmitted. This allows to speed-up data delivery to parallel working processing units in a system-on-a-chip since data delivery has no longer to account for a maximum predictable latency of the respective receiving units.08-18-2011
20100077247COMPUTER AUDIO INTERFACE UNITS AND SYSTEMS - A computer audio interface unit (03-25-2010
20130080815SYNCHRONIZING TIMING OF COMMUNICATION BETWEEN INTEGRATED CIRCUITS - An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.03-28-2013
20130036321INTERACTIVE DEVICE WITH TIME SYNCHRONIZATION CAPABILITY - An interactive device having time synchronization capability is provided. In one embodiment, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements based on a particular time of the internal clock. A user may input and adjust the time of the internal clock. In another embodiment, a setup module is provided which includes a computer processor that stores a setup time. The setup module establishes a connection with an interactive device, and time synchronizes the interactive device such that the internal clock of the interactive device is running the same time as the setup module. The setup module is capable of synchronizing the internal clock of multiple interactive devices, despite the interactive devices being programmed on separate occasions. The interactive device may be synchronized by the setup module via a hard-wired connection or wireless means.02-07-2013
20130042136METHOD, APPARATUS, AND SYSTEM FOR PERFORMING TIME SYNCHRONIZATION ON PCIE DEVICES - Embodiments of the present invention provide a method, an apparatus, and a system for performing time synchronization on PCIE (PCI Express, peripheral component interconnect express) devices. The method mainly includes: a PCIE device receiving, through a hardware interface, a time synchronization signal sent from a clock source device; parsing, by the PCIE device, the time synchronization signal to obtain clock information carried in the time synchronization signal, and using the clock information as a clock of the PCIE device. The PCIE devices are supported to access a synchronous network, and the PCIE devices are supported to be used as a global clock source.02-14-2013
20130042135CONTROLLER CORE TIME BASE SYNCHRONIZATION - A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.02-14-2013
20090125747Asymmetrical IO Method and System - An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.05-14-2009
20090125746INTEGRATED CIRCUIT WITH INTRA-CHIP CLOCK INTERFACE AND METHODS FOR USE THEREWITH - An integrated circuit includes a substrate. A first integrated circuit die includes a first circuit and a first intra-chip clock interface that transmits a first clock signal via the substrate. A second integrated circuit die includes a second circuit that operates based on the first clock signal and a second intra-chip clock interface that recovers the first clock signal from the substrate.05-14-2009
20120166857INTERFACE CIRCUIT, INVERTER DEVICE, INVERTER SYSTEM, AND TRANSMITTING AND RECEIVING METHOD - An interface circuit includes a general-purpose CPU configured to transmit a clock to a serial encoder with which bidirectional serial communication of clock synchronization type is to be performed, the CPU being configured to transmit and receive data to and from the serial encoder; and an additional circuit configured to detect a start bit of reception data transmitted from the serial encoder. The general-purpose CPU starts counting the number of bits of the reception data in response to a detection signal from the additional circuit, the detection signal indicating the detection of the start bit. The CPU stops transmitting the clock to the serial encoder upon completion of counting a predetermined number of bits of the reception data.06-28-2012
20120166856SIGNAL SYNCHRONIZING SYSTEMS AND METHODS - Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.06-28-2012
20090044037IMAGE PROCESSING APPARATUS AND CONTROL METHOD THEREOF - Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a receiver to receive a print command from a user terminal, and a controller to differently set a clock ratio according to a use rate of the CPU based on the print command.02-12-2009
20090319814MEMORY POWER CONTROLLER - A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.12-24-2009
20130073890SIGNAL SYNCHRONIZING DEVICE - A signal synchronizing device includes a trigger module for capturing an input signal according to a first clock signal which corresponds with the input signal so as to generate a trigger signal, a storage unit for forming a first pulse signal by pulling an output thereof to a first logic level according to the trigger signal, and by pulling the output thereof to a second logic level according to a feedback reset signal, and a synchronizing module for performing synchronous transfer according to the first pulse signal so as to output an output signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the output signal.03-21-2013
20130061084Massively Scalable Object Storage - Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.03-07-2013
20130061083Quad-Data Rate Controller and Realization Method Thereof - A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, used to arbitrates commands and data according to the state of the control state machine; a read data sampling clock generating module, used to generate read data sampling clocks with the same source and same frequency and different phases; a read data path calibrating module, used to determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; a read data path module, used to synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks.03-07-2013
20090271651Method and System for Reducing Latency in Data Transfer Between Asynchronous Clock Domains - A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C10-29-2009
20120117412LOWER ENERGY COMSUMPTION AND HIGH SPEED COMPUTER WITHOUT THE MEMORY BOTTLENECK - A computer system encompasses a processor (05-10-2012
20090006880SYSTEM AND METHOD FOR POWER SAVING DELAY LOCKED LOOP CONTROL - The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.01-01-2009
20130166938ARBITRATION CIRCUITRY FOR ASYNCHRONOUS MEMORY ACCESSES - A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.06-27-2013
20080294926Globally synchronized timestamp value counter - The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters located on separate packet processing cards can be synchronized. The synchronizing of these packet processing cards provides tracking of how long it takes for packets to be processed, provides the ability to generate packet headers that include sequence numbers for robust header compression, and allows the use of encryption protocols without a time reference signal. The synchronization is provided by sending the cards with counter value information and this information can be used to update the card's internal counter value information so that the card is synchronized with other cards.11-27-2008
20090327789Memory System with Calibrated Data Communication - A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.12-31-2009
20110283133Glitch-Free Clock Switching Circuit - A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to receive a second clock signal, synchronous with the first clock signal, at a third frequency and an output intended to deliver a third clock signal at a frequency alternately equal to the first value or the third value.11-17-2011
20080270817PRECISION OSCILLATOR FOR AN ASYNCHRONOUS TRANSMISSION SYSTEM - A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART.10-30-2008
20110302443Method and System for Synchronizing Multiple Secure Clocks - A method for synchronizing secure clocks in a system without using any external clock, a system configured to perform the method, and a computer medium storing system code. Each secure clock is adjustable subject to a set of predetermined adjustment constraints. The intersection of the adjustment constraints of all the clocks is a limit intersection. The clocks may be synchronized to an average adjusted time of the secure clocks (if the average adjusted time is within the limit intersection) or to a substitute average adjusted time within the limit intersection if the average adjusted time is outside the limit intersection. Synchronization can occur in response to a request to adjust at least one of the clocks by a proposed clock adjustment value or to synchronize at least one of them without otherwise adjusting them.12-08-2011
20110302442Method and System for Combining and/or Blending Multiple Content From Different Sources in a Broadband Gateway - A method and system are provided in which a broadband gateway may receive different content from different sources, may combine the content to produce a combined content, and may communicate the combined content to a device connected to the broadband gateway. The content may be automatically and/or manually synchronized. The synchronization may be based on a clock signal received from the device, a clock signal from another device connected to the broadband gateway, and/or a clock signal received through one or more network access service providers. The content may be video image data and/or audio data. Moreover, user-generated content may be received and combined by the broadband gateway when in a peer-to-peer communication configuration with the source of the content. When more than two different content are received, the broadband gateway may be utilized to select which contents to combine.12-08-2011
20110289338AUTOMATIC REFERENCE FREQUENCY COMPENSATION - In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it.11-24-2011
20110296226Systems and Methods for Transporting Time-of-Day Information in a Communication System - Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that comprises receiving, by a time-of-day transmission convergence (ToD-TC) module in the CPE, ToD information relating to the master clock. Based on the received information, time stamps are applied to reference data samples. The method further comprises transporting the ToD information by transporting the reference data samples with applied time stamps and utilizing time stamps of the reference data samples to synchronize the CPE clock with the master clock.12-01-2011
20120023357CYCLEMASTER SYNCHRONIZATION IN A DISTRIBUTED BRIDGE - A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the peer portal sampling its local cycle timer to obtain a sample value when the peer portal receives the synchronization signal; a bridge manager at an upstream portal communicating the sample value to a bridge manager at an alpha portal; the bridge manager at the alpha portal using the sampled time value to compensate for delays through a bridge fabric, calculate the correction to be applied to a cycle timer associated with the alpha portal, and correct the cycle timer.01-26-2012
20090172456METHOD AND APPARATUS FOR CONTROLLING DATA PROCESSING MODULE - Provided are a method and apparatus for controlling a plurality of data processing modules that process data independently and output the processed data. A method of controlling a first data processing module and a second data processing module that process data independently and synchronize and output the processed data, the method including acquiring first data output rate information representing a current data output rate of the first data processing module, acquiring second data output rate information representing a current data output rate of the second data processing module, and adjusting a data output rate of at least one of the first data processing module and the second data processing module, on the basis of the first data output rate information and the second data output rate information.07-02-2009
20090259870MANAGING TIMERS IN A MULTIPROCESSOR ENVIRONMENT - Timers are managed in a multiprocessing environment. Some timers are local to a given logical processor; such a local timer is inserted on and will be canceled only from that logical processor. Other timers are global to a logical processor. A global timer which was inserted on a given logical processor may be canceled from that logical processor or from another logical processor. Global timers are serviced in response to expiration of an associated local timer.10-15-2009
20100169695AUTONOMOUS MULTI-DEVICE EVENT SYNCHRONIZATION AND SEQUENCING TECHNIQUE ELIMINATING MASTER AND SLAVE ASSIGNMENTS - An apparatus and method for event synchronization. One or more devices that have a plurality of events to be carried out in a scheduled order in time are connected to a single shared time position clock (TPCLK). There are one or more sequencing controllers coupled with the one or more devices and configured to control the timing of high and low states of the shared TPCLK in accordance with the scheduled order. The synchronization among the plurality of events in the scheduled order is achieved based on the high and low states of the shared TPCLK and such synchronization of the plurality of events in the scheduled order is operated without the presence of master and slave devices.07-01-2010
20100169694METHOD FOR ENSURING SYNCHRONOUS PRESENTATION OF ADDITIONAL DATA WITH AUDIO DATA - A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.07-01-2010
20090172455Using Travel-Time as Means for Improving the Accuracy of Simple Network Time Protocol - A method for improving accuracy of simple network time protocol. A time inquiry is sent from at least one device in a substation to a time provider. A message including a reference time is received from the time provider. An accuracy of the reference time is evaluated. If the accuracy of the reference time is less than a threshold value the accuracy of the reference time is improved. The reference time is utilized for synchronization.07-02-2009
20100115323DATA STORE SYSTEM, DATA RESTORATION SYSTEM, DATA STORE METHOD, AND DATA RESTORATION METHOD - A data store system and a data restoration system that can decrease power consumed in data store-processing or data restoration are provided.05-06-2010
20100268976Clock Distribution With Forward Frequency Error Information - This disclosure relates to providing an information signal to one or more sub-systems within a wireless communications device, where the information signal enables the sub-systems to operate based on virtually corrected reference frequency clock signal(s).10-21-2010
20080215905Interface Device, Circuit Module, Circuit System, Device for Data Communications and Method for Calculating a Circuit Module - An interface device allows data communication between a controller and a plurality of circuit units. The interface device has a first interface for a connection to the controller, a second interface for a connection to a second circuit unit, and a third interface for a connection to a second circuit unit. An interface calibrating unit is coupled to the second and third interfaces and a non-volatile calibrating parameter memory is arranged in the interface calibrating unit or coupled to the calibrating unit. The memory is adapted to store calibrating parameters for the second and third interfaces.09-04-2008
20090100284System and Method for Synchronizing Redundant Data In A Storage Array - Systems and methods for synchronizing redundant data in a storage array are disclosed. In accordance with a method, a pointer indicating the amount of data synchronized between a first storage resource to a second storage resource may be maintained and a power event may be detected. In response to the detection of the power event, an attempt may be made to flush a write cache associated with the second storage resource to transfer data from the write cache to a non-volatile storage area of the second storage resource. A determination may be made whether the attempt to flush the write cache is successful. In response to determining that the attempt to flush the write cache is successful, a flag may be set to indicate that the pointer accurately indicates the amount of data mirrored from the first storage resource to the non-volatile storage area of the second storage resource.04-16-2009
20120110364APPARATUS AND METHOD FOR DECOUPLING ASYNCHRONOUS CLOCK DOMAINS - A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.05-03-2012
20130219207Distributed MEMS Devices Synchronization Methods and Apparatus - A method is provided for time synchronization in a MEMS (MicroElectroMechanical system) based system having a MEMS processor and a plurality of MEMS devices. In a specific embodiment, the method includes, in the MEMS processor, transmitting a synchronization signal to the plurality of MEMS devices and saving a local time upon transmitting the synchronization signal. The MEMS processor also receives sampled data and time information from the plurality of MEMS devices, when the data and information become available. The method also includes, in one or more of the MEMS devices, receiving the synchronization signal from the MEMS processor and storing a local time upon receiving the synchronization signal. The MEMS device also performs a sensing operation and stores sampled sense data and sense time information.08-22-2013
20100005333MICROTCA CARRIER, CLOCK CARD AND METHOD FOR PROVIDING A CLOCK - A MicroTCA system is disclosed that includes an MCH, a clock card connected with the MCH, and multiple AMCs. The clock card includes a clock selecting unit, configured to select and output a clock source and a phase-lock unit, configured to generate a system synchronization clock according to the clock source selected by the clock selecting unit of the clock card. The MCH includes a clock drive unit, configured to drive the system synchronization clock generated by the clock card to multiple AMCs connected with the MCH. A clock card, a cascaded MicroTCA carrier, and a method for providing a clock are also provided. In this way, the implementation of the MicroTCA clock system is simplified, and the whole configuration cost of multiple cascaded MicroTCA carriers is reduced.01-07-2010
20110214003CLOCK CONTROL SIGNAL GENERATION CIRCUIT, CLOCK SELECTOR, AND DATA PROCESSING DEVICE - Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before- and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.09-01-2011
20110161714CORRELATION TECHNIQUE FOR DETERMINING RELATIVE TIMES OF ARRIVAL/DEPARTURE OF CORE INPUT/OUTPUT PACKETS WITHIN A MULTIPLE LINK-BASED COMPUTING SYSTEM - A method is described that comprises receiving a timing exposure packet having timestamp information. The timestamp information identifies a cycle of a clock signal at which the packet was made available for transfer from a core to a physical layer within a component of a link-based computing system. The packet having been transmitted from the physical layer and also having phase information. The phase information identifies a cycle of the clock signal at which the packet was transferred from the core to the physical layer.06-30-2011
20100122103CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE - Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.05-13-2010
20100083023NEGOTIATION BETWEEN MULTIPLE PROCESSING UNITS FOR SWITCH MITIGATION - A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.04-01-2010
20090204842Streaming Media Player and Method - A streaming media player receives a media stream from a server. A clock comparator of the media player compares a clock value of the server with a clock value of the media player and generates a clock state value representing how much the server's clock value lags or leads the player's clock value. An output component of the media player generates an output media stream corresponding to the input media stream. A rate component of the media player receives the clock state value from the clock comparator and varies the rate of output of the media stream from the output component in dependency on the clock state value.08-13-2009
20090204843MEDIA DATA SYNCHRONIZATION IN A WIRELESS NETWORK - A method of keeping global time in a wireless network, the method includes reading a Time Synchronization Function (TSF) to provide an initial time base. An interconnected clock control circuit is employed to read the TSF time from the circuitry used to read the TSF and to implement a local clock based on time values read from the TSF.08-13-2009
20090282279SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF - An internal circuit (11-12-2009
20090083565SDRAM SHARING USING A CONTROL SURROGATE - A system and method for sharing a single SDRAM unit between two chips, each having an SDRAM controller. Each SDRAM controller is effectively divided into a control block and a data block. The first SDRAM controller drives or reads directly from the SDRAM unit's data bus instead of employing a dedicated data bus for communication between the first and second SDRAM units. The data section of the second SDRAM controller responds to requests from the first SDRAM controller as if the requests had come from the second SDRAM controller's own control block. In other embodiments of the present invention, the second SDRAM controller can accept control signals generated by the first SDRAM. If the second SDRAM controller detects that the first SDRAM controller is initiating a request, the second SDRAM controller terminates any active requests of its own using burst termination. Thereafter, the second SDRAM controller processes the first SDRAM controller's request with the SDRAM unit as appropriate.03-26-2009
20100287400Apparatus providing locally adaptive retiming pipeline with swing structure - The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor using a low voltage. Thus, synchronization problems in a chip under different environments are solved for high reliability.11-11-2010
20100287401METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN ASYNCHRONOUS CLOCK DOMAINS - An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.11-11-2010
20100287402TIMESTAMPING APPARATUS AND METHOD - A timestamping apparatus and method are provided. The timestamping apparatus implements timestamping on a synchronization message at a physical layer when the synchronization message is transmitted to the physical layer. At an application layer of the timestamping apparatus, a bit stream including a start indicator bit informing a start of a pseudo random number sequence, the pseudo random number sequence, and an end indicator bit informing an end of the pseudo random number sequence is generated to check whether or not a message received from the physical layer is the synchronization message, and is inserted as signature information of the synchronization message. At the physical layer of the timestamping apparatus, the signature information included in the synchronization message is detected, and timestamping information is generated when the signature information is detected.11-11-2010
20100281289Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.11-04-2010
20100005334METHOD FOR ENSURING SYNCHRONOUS PRESENTATION OF ADDITIONAL DATA WITH AUDIO DATA - A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.01-07-2010
20100005332METHOD AND SYSTEM FOR DISTRIBUTING A GLOBAL TIMEBASE WITHIN A SYSTEM-ON-CHIP HAVING MULTIPLE CLOCK DOMAINS - A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code over a global timebase bus. A global timebase generator includes a binary counter and a binary-to-Gray-code converter. Each receiver module registers the global timebase count value with its own local clock and includes a Gray-code-to-binary converter. The converted value, in binary form, may be used as least significant bits of a globally synchronized local timebase. Most significant bits may be generated by a local binary counter incremented at each 1-to-0 transition of the most significant bit of the global timebase count value.01-07-2010
20100146319Method And Protection Device For A Power Network Accounting For Route Switching In A Telecommunication Network - A protection device for a power network performs a method to align measuring times of first and second measurements of an electric quantity, taken at different ends of a power network line transmitted with measuring times via a telecommunication network. In the method, a send transmission time from the local to remote end of the line and a receive transmission time from the remote to local end of the line are determined based on time signals from internal clocks. After a global time reference to synchronize the internal clocks is lost, a clock drift is determined between the internal clocks. The measuring times of the first and the second measurements are aligned using the send and receive transmission times as well as the clock drift. A sudden change in the clock drift is determined in order to recognize a route switching in the telecommunication network and the clock drift is corrected.06-10-2010
20090063886System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture - A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.03-05-2009
20090119531Digital Phase Relationship Lock Loop - In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.05-07-2009
20080270816Portable data storage apparatus and synchronization method for the same - The present invention discloses a portable data storage apparatus for use with a host device, including an interface coupled to the host device for data transmission therebetween, a real time clock (RTC) for synchronizing the portable data storage apparatus with a clock time, and a memory module for storing data and a detection program for detecting time discrepancy between system time of the host device and the clock time of the RTC after the storage apparatus is loaded to the host device.10-30-2008
20110016343Synchronizing a Clock in a Vehicle Telematic System - A telematic module (01-20-2011
20090259871SYNCHRONIZING SIGNALS RELATED TO THE OPERATION OF A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that synchronizes signals related to the operation of a computer system. During operation, a set of correlation coefficients between a first signal and a second signal is generated, wherein each correlation coefficient is associated with a different phase shift between the first signal and the second signal. Then, a synchronizing phase shift associated with the highest correlation coefficient in the set of correlation coefficients is determined in order to synchronize the first signal and the second signal.10-15-2009
20090204841Periodic signal processing apparatus - A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.08-13-2009
20090199034INTERACTIVE DEVICE WITH TIME SYNCHRONIZATION CAPABILITY - An interactive device having time synchronization capability is provided. In one embodiment of the present invention, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements based on a particular time of the internal clock. A user may input and adjust the time of the internal clock. In another embodiment of the present invention a setup module is provided. A setup module is an operative device that includes a computer processor that stores a setup time. The setup module establishes a connection with an interactive device, and time synchronizes the interactive device such that the internal clock of the interactive device is running the same time as the setup module. The setup module is capable of synchronizing the internal clock of multiple interactive devices, despite the interactive devices being programmed on separate occasions. In addition, the setup module is capable of programming a number of interactive devices in a quick and efficient manner, thereby keeping the manufacturer's costs low. The computer processor of the interactive device runs a software program which enables the interactive device to be synchronized by the setup module via a hard-wired connection or wireless means such as infrared (IR) and/or radio frequency (RF) signals.08-06-2009
20090083566Method and System for Using Meta-Information to Manage Data Object Synchronization - A system and method for synchronizing data items in a data processing system. In one embodiment, the method includes receiving a synchronization request that specifies a set of data items that are subject to synchronization. The set of data items subject to synchronization are identified from the synchronization request and a synchronization cycle of the identified set of data items is commenced. The synchronization cycle includes a step of processing meta-information associated with the identified set of data items. Synchronization filter parameters are determined from the processed meta-information and the data items to be synchronized are selected in accordance with the determined synchronization filter parameters.03-26-2009
20090049324Methods and systems for operating memory in two modes - A memory system permits synchronized transmission of data with multiple memory modules in a dynamically expandable bus system such as with a point-to-point memory bus using strobed data transmission. Memory modules of the system are selectively configured to switch transmission modes to either transmit data to a memory controller or a timing reference signal to another memory module from a common terminal coupled to a common path of the bus which may depend on the number of memory modules configured in the system. The system permits all memory modules to operate with a strobed based memory controller even when some memory modules of the system do not share a strobe signal path with the memory controller of the system.02-19-2009
20120079310COMMUNICATION SYSTEM, COMMUNICATION INTERFACE, AND SYNCHRONIZATION METHOD - An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.03-29-2012
20080263380GPS TIME SYNCRONIZATION FOR DATA DEVICE - A method is presented to improve the accuracy of time synchronization of data. The invention consists of a timing module compromising a GPS interface with ability controller-based timing standard, high speed inputs and outputs and an asynchronous interface to an external processor system. It attaches a time-stamp referenced to an absolute time standard to transitions on the high speed inputs and a means for delivering these time stamps referenced to the high speed input to a computer or network. Alternatively the computer or network can specify a high speed output and an absolute time for an output transition and the timing module can deliver the specified output transition at the specified absolute time. Compared to existing systems of time synchronization, it will improve the accuracy of the timed data from the current Ethernet tolerance of up to 5 milliseconds to a possible tolerance of 250 nanoseconds.10-23-2008
20090199035Network signal processing apparatus - A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals.08-06-2009
20090100285Internal Clock Signal Generating Circuits Including Frequency Division and Phase Control and Related Methods, Systems, and Devices - An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.04-16-2009
20090222684Fast, Automatically Scaled Processor Time Stamp Counter - In one embodiment, a processor comprises at least one processor time stamp counter (TSC) and a control unit coupled to the processor TSC. The processor TSC corresponds to a TSC that is defined to increment at a TSC clock frequency even though the processor is configurable to operate at one of a plurality of clock frequencies. The control unit is configured to maintain the processor TSC, and is configured to update the processor TSC when the processor is operating at a current clock frequency of the plurality of clock frequencies, wherein the update comprises adding a value to the processor TSC, and wherein the value is based on the ratio of the TSC clock frequency and the current clock frequency.09-03-2009
20090177909MEMORY BUS SHARED SYSTEM - The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared bus controller outputs the write/read address with respect to FLASH on the address bus. Then, after the end of data transfer on the data bus, either the shared bus controller outputs the write data, or FLASH can output the read data on the data bus by means of a strobe signal. Then, the input of address is established by FLASH, and, as the shared bus controller asserts a strobe signal, either FLASH fetches the write data on the data bus, or the shared bus controller fetches the read data on the data bus.07-09-2009
20090249107COMMUNICATION APPARATUS HAVING CLOCK INTERFACE - A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.10-01-2009
20100162026METHOD AND APPARATUS FOR ACCURATELY SYNCHRONIZING SIGNALS RELATED TO THE OPERATION OF A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that accurately synchronizes signals related to the operation of a computer system. During operation, the system receives a first time-domain signal associated with a first system variable and a second time-domain signal associated with a second system variable from the computer system. The system then transforms the first and the second time-domain signals into a first frequency-domain signal and a second frequency-domain signal, respectively. Next, the system computes a cross-power-spectral-density (CPSD) between the first and second frequency-domain signals to obtain a phase angle versus frequency graph between the two frequency-domain signals. The system subsequently extracts the slope of the phase angle versus frequency graph, and uses the value of the slope to synchronize the first time-domain signal and the second time-domain signal.06-24-2010
20100192002METHOD AND APPARATUS OF TESTING DATA COMMUNICATION PERFORMANCE OF A NETWORK SYSTEM - Machine-readable media, methods, apparatus and system for testing a data communication performance of a network system are described. In some embodiments, an apparatus may comprise a first channel to synchronize a local clock of the apparatus with another local clock of another apparatus by communicating a synchronization message with the another apparatus through a first connection. The apparatus may further comprise a second channel to analyze a transceiving activity performed by the apparatus through a second connection and a timestamp of the transceiving activity, wherein the timestamp is made based upon the local clock.07-29-2010
20100185889CHANNEL SUBSYSTEM SERVER TIME PROTOCOL COMMANDS - A protocol for communicating with the timing facility used in a data processing network to provide synchronization is provided via the execution of a machine instruction that accepts a plurality of commands. The interaction is provided through the use of message request blocks and their associated message response blocks. In this way timing parameters may be determined, modified and communicated. This makes it much easier for multiple servers or nodes in a data processing network to exist as a coordinated timing network and to thus more cooperatively operate on the larger yet identical data files.07-22-2010
20120124407SEMICONDUCTOR DEVICE AND RESET CONTROL METHOD IN SEMICONDUCTOR DEVICE - Reset request from external are held at a reset request holding unit having holding units connected in series; a reset switching unit performs a logical product operation of all of outputs of the holding units to set it as an asynchronous reset request, setting an output of the holding unit at a final stage of the holding units as a synchronous reset request, performing a logical product operation of the asynchronous reset request and the synchronous reset request, and outputs an operation result; the asynchronous reset request is masked in a synchronous reset mode; and a reset signal is output from a reset output unit based on the operation result at the reset switching unit.05-17-2012
20100192001DEVICE TIME ADJUSTMENT FOR ACCURATE DATA EXCHANGE - The clock of an endpoint device is adjusted to a collection system time in a meter reading system where the endpoint device is employed to read and record meter reading data for calculation of consumption data. Specifically, the meter reading data are recorded as a fixed number of intervals in such a way that the calculation of consumption data can be requested by indication of the number of intervals and the start interval. In one aspect, the endpoint device time is adjusted to an external clock to calculate accurate consumption while the process for adjusting the endpoint device time does not result in creating very short/long intervals, nor updating the meter reading data that have been already logged and stored in the endpoint device.07-29-2010
20120036388SYSTEM AND METHOD FOR SYNCHRONIZING MULTIPLE MEDIA DEVICES - Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to he displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed. The computer system executes a synchronization algorithm that uses the transmitted UST and UST/MSC pair to maintain the media devices in a synchronized state.02-09-2012
20100235672MULTI-CORE PROCESSOR, ITS FREQUENCY CONVERSION DEVICE AND A METHOD OF DATA COMMUNICATION BETWEEN THE CORES - A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed. In the invention, the dynamic frequency conversion function of a multi-core processor is achieved, the frequency conversion coefficient control may be performed by each processor core independently, and a highly effective synchronous communication may be maintained between the processor cores, so as to reduce the overall running consumption of the processor and save power on different processor cores of the multi-core processor or on different IP modules in SOC.09-16-2010
20100250994DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME - Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.09-30-2010
20090276652Method of Link Word Synchronization - A method for word synchronization can be applied to asynchronous devices including SERDES devices connected across serial lines. A state transition methodology characterizes the state of the device based on control characters received consistently across the serial lines and channels the system to a state of word synchronization. Loss of synchronization and transmission errors lead to a re-establishment of synchronization.11-05-2009
20110066874SNIFF MODE LOW POWER OSCILLATOR (LPO) CLOCK CALIBRATION - An apparatus for clock calibration on a remote device includes a first oscillator, a second oscillator, and a clock calibration module. The first oscillator generates a first clock signal during an active communication mode to facilitate communications between the remote and host devices. The first oscillator is inactive during a sniff mode. The second oscillator generates a second clock signal during both the active communication and sniff modes. The clock calibration module generates an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode. The estimated count is based on a clock ratio of a baseline count of the first clock signal relative to a baseline count of the second clock signal. The clock calibration module also calculates a difference between the estimated count and an actual count from the host device to determine whether to update the clock ratio.03-17-2011
20110066873MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS - Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.03-17-2011
20090113229METHOD AND A SYSTEM FOR SYNCHRONISING RESPECTIVE STATE TRANSITIONS IN A GROUP OF DEVICES - A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.04-30-2009
20080288805SYNCHRONIZATION DEVICE AND METHODS THEREOF - A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.11-20-2008
20100223486METHOD AND SYSTEM FOR I2C CLOCK GENERATION09-02-2010
20090106575Controlling Asynchronous Clock Domains to Perform Synchronous Operations - Mechanisms for controlling asynchronous clock domains to perform synchronous operations are provided. With these mechanisms, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.04-23-2009
20090070617Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture - A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.03-12-2009
20130132760Apparatus and Method for Achieving Glitch-Free Clock Domain Crossing Signals - A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.05-23-2013
20130132761MEMORY MODULE INCLUDING A PLURALITY OF SYNCHRONOUS MEMORY DEVICES - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.05-23-2013
20100313055MEMORY SYSTEM - A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data from stop of output of the Nth read clock and before a first predetermined time. The memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.12-09-2010
20130138991CLOCK SYNCHRONIZATION IN AN IMPLANTABLE MEDICAL DEVICE SYSTEM - This disclosure is directed to the synchronization of clocks of a secondary implantable medical device (IMD) to a clock of a primary IMD. The secondary IMD includes a communications clock. The communications clock may be synchronized based on at least one received communications pulse. The secondary IMD further includes a general purpose clock different than the communications clock. The general purpose clock may be synchronized based on at least one received power pulse. The communications clock may also be synchronized based on the at least one received power pulse.05-30-2013
20100185890SYNCHRONOUS GLOBAL CONTROLLER FOR ENHANCED PIPELINING - The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.07-22-2010
20090327790METHOD FOR SYNCHRONIZING A PLURALITY OF DRIVES, AND A DRIVE OPERATED WITH THE METHOD - In a machine with a supervisory unit and several drives, contour discrepancies can be eliminated and synchronization simplified by using a line which is commonly employed for actuating a drive, e.g. the Enable line, also for synchronously sending a clock pulse to the various coordinated drives operating as “slaves”. The clock pulse representing the synchronization signal has a predetermined duration which is shorter than pulses typically used to deactivate a drive. The drives are designed to distinguish between these two types of pulses and only interpret a pulse of longer duration where the Drive Enable signal is switched off for a longer time, as indicating removal of the Drive Enable, i.e. deactivation of the drive.12-31-2009
20100058099HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES - High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.03-04-2010
20100058098CONVEYANCE CONTROL SYSTEM AND CONVEYANCE CONTROL METHOD - Provided is a conveyance control system in which fast and smooth control is realized without causing a control delay by a processing delay of a control apparatus such as a PLC, and wiring between a control object and a central control unit is omitted. A conveyance control system according to the present invention includes a plurality of data processing slave stations connected through a common transmission line. The data processing slave station obtains information about a predetermined station from monitor/control data about a plurality of stations of the data processing slave station transmitted to the common transmission line, determines and adjusts control/monitoring of an own station and outputs information about an own station to the common transmission line. The information about an own station output to the common transmission line from the data processing slave station is obtained by a different station as part of the monitor/control data to become a control/monitor factor of the different station.03-04-2010
20100058097USB BASED SYNCHRONIZATION AND TIMING SYSTEM - A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.03-04-2010
20110252263SEMICONDUCTOR STORAGE DEVICE - Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The PCI-Express type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; a PCI-Express host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the PCI-Express host interface unit and the memory disk unit to control a data transmission/reception speed between the PCI-Express host interface unit and the memory disk unit. The storage device can support a low-speed data processing speed for the host and simultaneously support a high-speed data processing speed for the memory disk unit, so that there are advantages in that the performance of the memory disk can be fully utilized to enable high-speed data processing in an existing interface environment.10-13-2011
20110078483OBSERVING AN INTERNAL LINK VIA AN EXISTING PORT FOR SYSTEM ON CHIP DEVICES - Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.03-31-2011
20110078482Method and Apparatus for Audio Receiver Clock Synchronization - An audio receiver's output clock is synchronized based on a number of input and output audio samples measured over a predetermined sample period. In one embodiment, a sample difference may be determined by subtracting the measured number of input audio samples from the measured number of output audio samples. This sample difference may then be compared to a predetermined threshold. In one embodiment, if the absolute value of the sample difference is less than the predetermined threshold, no adjustment to the output clock may be needed. When the absolute value of the sample difference is greater than the predetermined threshold, the output clock rate may be adjusted either upwards or downwards.03-31-2011
20110252264PHYSICAL MANAGER OF SYNCHRONIZATION BARRIER BETWEEN MULTIPLE PROCESSES - The present invention relates to a computer device with synchronization barrier. The device comprises a memory and a processing unit, capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, said blocks being associated by groups in successive work steps, The device further comprises a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.10-13-2011
20110060933TEST APPARATUS AND TEST METHOD - There is provided a test apparatus for testing a device under test, including a plurality of test modules that test the device under test, and a synchronization module that is connected to each of the plurality of test modules, where the synchronization module synchronizes together the plurality of test modules. Here, based on a synchronization signal received from a digital module, the synchronization module synchronizes an analog module to the digital module, and the digital module is one of the plurality of test modules that exchanges a digital signal with the device under test, and the analog module is one of the plurality of test modules that performs an analog test on the device under test.03-10-2011
20120204054Memory System with Calibrated Data Communication - An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.08-09-2012
20080229136Controlling Asynchronous Clock Domains to Perform Synchronous Operations - A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation a manufacturing test sequence, debug operation, or the like.09-18-2008
20110154088FALLING CLOCK EDGE JTAG BUS ROUTERS - The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.06-23-2011
20080307246SYNCHRONIZING CONTENT BETWEEN CONTENT DIRECTORY SERVICE AND CONTROL POINT - In one embodiment, a method is performed at a control point (CP) in a network. An action is invoked to create a synchronization data structure on a media server that includes a content directory service (CDS) in the network, wherein the synchronization data structure includes a synchronization relationship describing a relationship between the CP and the CDS. Then an action is invoked to add synchronization pair information to one or more objects on the CDS. A change log is requested from the CDS. Then the change log is received from the CDS, wherein the change log contains information about changes to the one or more objects to which synchronization pair information for the CP was added.12-11-2008
20090138743METHOD AND APPARATUS FOR SECURE COMMUNICATION BETWEEN CRYPTOGRAPHIC SYSTEMS USING REAL TIME CLOCK - Provided are a method and apparatus for secure communication between cryptographic systems using a Real Time Clock (RTC). The method and apparatus allow a transmitting cryptographic system to transfer partial RTC data and a receiving cryptographic system to restore entire RTC data, thereby minimizing data to be transferred between the cryptographic systems. The method includes: calculating a largest RTC deviation between a transmitting cryptographic system and a receiving cryptographic system; calculating the smallest number of bits of partial data on an RTC required for restoring entire data on the RTC on the basis of the calculated largest RTC deviation; calculating the partial RTC data on the basis of the calculated smallest number of bits of the partial RTC data; and transferring the calculated partial RTC data to the receiving cryptographic system.05-28-2009
20080229135SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD - Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.09-18-2008
20110047400Systems and Methods to Efficiently Schedule Commands at a Memory Controller - Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.02-24-2011
20110055616Memory module - A memory buffer mounted on a memory module includes a pre-launch function of advancing outputs of address/command signal and a post-launch function of delaying outputs of control signal. A time step increment for pre/post-launch time adjustment is set to be equal to or finer than tCK/32 where tCK is one clock cycle.03-03-2011
20080256378Audio/Video Content Synchronization Through Playlists - A method is disclosed for performing bi-directional synchronization between a host device having a large capacity, e.g., a personal computer (10-16-2008
20100325466DISPLAY PANEL DRIVE CIRCUIT, LIQUID CRYSTAL DISPLAY DEVICE, AND METHOD FOR DRIVING DISPLAY PANEL - In at least one embodiment, a display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is configured such that: each of the unit circuits receives a clock signal and either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal; and the clock signal has a rising portion which is caused by activation of the clock signal and which is sloped or a falling portion which is caused by activation of the clock signal and which is sloped. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which hardly causes a poor gate-on pulse signal (which causes unevenness in electric potential during inactivation, for example.12-23-2010
20110138213Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.06-09-2011
20110258474METHOD AND SYSTEM FOR PRECISE SYNCHRONIZATION OF AUDIO AND VIDEO STREAMS DURING A DISTRIBUTED COMMUNICATION SESSION WITH MULTIPLE PARTICIPANTS - Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve synchronization, methods of introducing buffering delays to create handicaps for players with faster connections, methods which help players with synchronization (such as a synchronized metronome during a music conferencing session), methods for synchronized recording and live delivery of synchronized data to the audience watching the distributed interaction live over the Internet.10-20-2011
20100031077Alternate Signaling Mechanism Using Clock and Data - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.02-04-2010
20100023792SIGNAL SYNCHRONIZATION METHOD AND SIGNAL SYNCHRONIZATION CIRCUIT - There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in synchronization with a second clock signal with a different cycle from that of the first signal.01-28-2010
20090150705METHOD AND APPARATUS FOR OPERATING COOPERATING, DIFFERING DEVICES - A method for operating cooperating, differing devices, particularly of a plant, with different controls controlling the control sequences and in particular with different control cycles, is characterized in that the clocks (IPO06-11-2009
20090138742Automatic Clock and Data Alignment - A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.05-28-2009
20110167292COMPUTER SYSTEM WITH SYNCHRONIZATION/DESYNCHRONIZATION CONTROLLER - A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.07-07-2011
20120017108SERIAL CONTROLLER AND BI-DIRECTIONAL SERIAL CONTROLLER - A serial controller is adapted to receive an external clock and an input data, and output an inverted clock and an output data. The serial controller includes an inverter, a serial position detector, a synchronous clock generator, a serial register, and a half-cycle delay unit. Thereby, through the serial controller, the problem that the data signal and the driving clock are not synchronous when the clock series are inverted is avoided. Besides, a bi-directional serial controller further includes an identification unit and a data directing unit, and the serial controller is enabled to return the current status to a central control unit to serve as the reference for error detection.01-19-2012
20120060045METHOD AND APPARATUS FOR SYNCHRONISING THE LOCAL TIME OF A PLURALITY OF INSTRUMENTS - A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period.03-08-2012
20120159229METHOD FOR GENERATING A CLOCK SIGNAL - An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.06-21-2012
20120233487INFORMATION PROCESSING APPARATUS AND TIME-OF-DAY CONTROL METHOD - In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.09-13-2012
20120072758ANALYSIS AND VISUALIZATION OF CLUSTER RESOURCE UTILIZATION - An analysis and visualization depicts how an application is leveraging processor cores of a distributed computing system, such as a computer cluster, in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime and the amount of overhead used by libraries or middleware. Information regarding processes or threads running on the nodes over time is received, analyzed, and presented to indicate portions of computer cluster that are used by the application, idle, other processes, and libraries in the system. The analysis and visualization can help a developer understand or confirm contention for or under-utilization of system resources for the application and libraries.03-22-2012
20110099408CLOCK DATA RECOVERY AND SYNCHRONIZATION IN INTERCONNECTED DEVICES - For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.04-28-2011
20110099407Apparatus for High Speed Data Multiplexing in a Processor - A processer, for example a field programmable gate array (FPGA), comprises input/output (I/O) logic including timing adjustment logic operative to synchronize a time division multiplexed (TDM) line of the I/O logic using an a priori known test pattern. The timing adjustment logic may include clock cycle data alignment logic operative to adjust data on the TDM line by increments of a clock cycle to match it to an a priori known test pattern, and skew logic operative to prevent leading or trailing edges of the data from aligning with edges of a clock pulse leading or trailing edge. The I/O logic may be a Serializer/Deserializer (SerDes) logic that includes a state machine operative to control the clock cycle data alignment logic and skew logic to adjust and synchronize the data with the known test pattern.04-28-2011
20120131373Method for Sensing Input Signal Changes - A method for sensing input signal changes at an input of an input/output module operated in an automation system in which a signal is sampled by an input/output module. A change event and a timestamp associated with the change event are generated when a change in the sampled signal occurs and a value pair comprising the change event and the timestamp is stored in a higher-ranking automation component to the input/output module. The input/output module and the higher-ranking automation component are operated clock-synchronously with respect to one another by a clock pulse, and the timestamp is calculated centrally on the higher-ranking automation component based on the clock-synchronous operation.05-24-2012
20120317434Method and Apparatus for Processor to Operate at Its Natural Clock Frequency in the System - A mechanism to generate a self-clock within a synchronous processing unit of an asynchronous digital device. The self-clock is designed to match the worst-case delay of pipeline processing unit in such a way that the pipeline processing unit is operate at its own natural clock frequency and shutting off when there is no valid data to process. The synchronization logic of the processing unit consists of self-clock that generates output clock to synchronize with the internal clock edge if the processing unit is active or synchronize with the input clock edge if the processing unit is inactive.12-13-2012
20120272087Method For Ensuring Synchronous Presentation of Additional Data With Audio Data - A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.10-25-2012
20100058096SIGNAL PROCESSING APPARATUS AND METHOD THEREOF - A signal processing apparatus and method are provided. The signal processing apparatus includes a counter which counts the number of internal clocks; a clock adjustment value determiner which compares a count value of external clocks contained in a broadcast signal to a count value of internal clocks obtained by the counter, and determines a clock adjustment value according to a result of the comparing operation; and a clock adjuster which adjusts the number of the internal clocks based on the determined clock adjustment value. Therefore, it is possible to synchronize the count value of external clocks with the count value of internal clocks using a simple structure.03-04-2010
20120254649METHOD AND SYSTEM FOR PRECISE SYNCHRONIZATION OF AUDIO AND VIDEO STREAMS DURING A DISTRIBUTED COMMUNICATION SESSION WITH MULTIPLE PARTICIPANTS - Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve synchronization, methods of introducing buffering delays to create handicaps for players with faster connections, methods which help players with synchronization (such as a synchronized metronome during a music conferencing session), methods for synchronized recording and live delivery of synchronized data to the audience watching the distributed interaction live over the Internet.10-04-2012
20120185721MULTI-RATE SAMPLING FOR NETWORK RECEIVING NODES USING DISTRIBUTED CLOCK SYNCHRONIZATION - Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a first clock having a first clock frequency (f07-19-2012
20120221880MEMORY SYSTEM AND METHOD OF CONTROLLING SAME - A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.08-30-2012
20090319815Synchronizing Graphical Programs Executing on Respective Computer Systems - A first graphical program executing on a first device may execute a first graphical code portion for a plurality of iteration. Various systems and methods for synchronizing the execution of the iterations of the first graphical code portion with graphical code portions executing iteratively in graphical programs on other devices are described. Various systems and methods for synchronizing the execution of the iterations of the first graphical code portion with operation of measurement devices or other devices are also described.12-24-2009
20120221881METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MEASURING A COMMUNICATION FROM A FIRST DEVICE TO A SECOND DEVICE - In response to communications from a first device to a second device, respective phase differences are estimated between a first clock of the first device and a second clock of the second device. A first average phase difference is computed within a percentile of a first subset of the respective phase differences. The percentile is less than 100. A second average phase difference is computed within the percentile of a second subset of the respective phase differences. The second subset is a modification of the first subset. The second average phase difference is computed in response to the first average phase difference and the modification.08-30-2012
20120239960METHOD FOR COMPENSATING A TIMING SIGNAL, AN INTEGRATED CIRCUIT AND ELECTRONIC DEVICE - A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.09-20-2012
20120266008SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK - An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.10-18-2012
20120324270SYNCHRONOUS NETWORK - A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and a clock stability monitoring circuit which monitors internal control parameters (CP) of said timing circuit to detect an instability of the reference clock distributed within said synchronous network.12-20-2012
20080288804Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test - An integrated circuit (11-20-2008
20120278645CLOCK SYNCHRONIZATION ACROSS AN INTERFACE WITH AN INTERMITTENT CLOCK SIGNAL - The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system. During an active state of the interface, the system uses a local time base in the second component to generate a local clock signal that tracks a host clock signal from the first component. Next, during an inactive state of the interface, the system uses the local time base to maintain the local clock signal at the second component. Finally, during a subsequent active state of the interface after the inactive state, the system adjusts the local clock signal to remove clock drift between the local clock signal and the host clock signal.11-01-2012
20120278646WAKING A MEDIA BUS - Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.11-01-2012
20110276820Cross Controller Clock Synchronization - A system may include a plurality of subsystems, e.g. instrumentation units housed in separate chassis, each chassis including multiple instrumentation devices, e.g. data acquisition cards. Each subsystem may generate a local reference clock, which may be phase aligned and locked with respect to one or more similar reference clocks of other subsystems, via a high-level precision time protocol (PTP). Each instrumentation device within a given subsystem may generate its own sample clock based on the local reference clock, and may generate its own trigger clock based on its own sample clock. All trigger clocks may be synchronized with respect to each other through a future time event issued using the PTP, and each instrumentation device may then use its trigger clock to synchronize any received trigger pulses, which may also be issued through future time events using the PTP. This results in synchronizing the received triggers across all participating instrumentation devices across all participating subsystems, ensuring that data acquisition is properly synchronized across the multiple subsystems.11-10-2011
20120331325PROGRAMMABLE MECHANISM FOR DELAYED SYNCHRONOUS DATA RECEPTION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.12-27-2012
20120331324PROGRAMMABLE MECHANISM FOR SYNCHRONOUS STROBE ADVANCE - An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.12-27-2012
20110320850OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.12-29-2011
20130013951Method for Synchronizing an Operating Clock with a Time Clock of an Automation Network - A method for synchronizing an operating clock with a time clock in an automation network comprising a plurality of sync slaves that are to be coordinated and a time sync master, wherein the plurality of sync slaves are synchronized with respect to the time clock by the time sync master, and wherein the plurality of sync slaves derive their operating clock from the time clock.01-10-2013
20130013950CLOCK DOMAIN CROSSING INTERFACE - A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.01-10-2013
20130013952Method for Integration of Systems with Only One Sync Domain for Time of Day and Clock Pulse Synchronization into a Global Time of Day Synchronization Domain - A method for synchronizing the operating clock and the timing clock of a subordinate domain of an automation network, wherein sync slaves are synchronized by a clock sync master with respect to an operating clock, a clock sync master forms part of a subordinate domain, a single synchronization message serves to synchronize the sync slaves with respect to their respective operating clock and timing clock, wherein the method comprises providing a notification of the difference between the timing clock and the operating clock using the synchronization message, and accepting this difference into the synchronization message as additional information.01-10-2013
20120151244Method and System for Precise Temperature and Timebase PPM Error Estimation Using Multiple Timebases - Methods and systems for precise temperature and timebase ppm error estimation using multiple timebases may comprise measuring a coarse reading of a temperature corresponding to the plurality of timebases. The frequencies of the timebases may be compared to generate a fine reading of the temperature based, at least in part, on the coarse reading and the comparison of the frequencies with respect to models of temperature dependencies for each of the timebases. The timebases may be calibrated utilizing the generated fine reading. The plurality of timebases may comprise different order temperature dependencies. The models of temperature dependencies of each of the plurality of timebases may be updated based, at least in part, on the fine reading of the temperature corresponding to the plurality of timebases. A global navigation satellite system (GNSS) clock signal may be utilized periodically to improve the accuracy of the calibration of the plurality of timebases.06-14-2012
20120151243SYNCHRONIZATION CIRCUIT THAT FACILITATES MULTIPLE PARALLEL READS AND WRITES - The disclosed embodiments provide a synchronization circuit that supports multiple parallel reads and writes. This synchronization circuit includes multiple coupled data storage locations that synchronize data and control signals between two time domains and control logic that facilitates simultaneously accessing a variable number of such data storage locations in the same clock cycle. During operation, the synchronization circuit receives a request to simultaneously access (e.g., read and/or write) two or more synchronized data storage locations. In response to the request, the control logic in the synchronization circuit determines whether the present state of the synchronization circuit can accommodate the request, and if so, simultaneously accesses two or more synchronized data storage locations.06-14-2012
20130019119MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD - A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.01-17-2013
20110145622DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED - A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.06-16-2011
20110161713COMMAND LATENCY REDUCTION AND COMMAND BANDWIDTH MAINTENANCE IN A MEMORY CIRCUIT - A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.06-30-2011
20080250262Semiconductor memory device and method for generating internal control signal - A semiconductor memory device includes: a command input unit configured to receive a plurality of external commands in synchronization with a rising edge of an internal clock to generate a plurality of pre-control signals; an output control signal generating unit configured to receive the plurality of external commands to generate an output control signal in synchronization with a falling edge of the internal clock prior to the rising edge of the internal clock; an address input unit configured to receive a plurality of addresses to output a plurality of internal addresses in response to the output control signal; and an internal driving signal generating unit configured to receive the plurality of internal addresses and the plurality of pre-control signals to generate a plurality of internal driving control signals.10-09-2008
20080244298Clock synchronization scheme for deskewing operations in a data interface - A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.10-02-2008
20080222441Software programmable timing architecture - One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes. The at least one memory element may be configured to store particular values for M outputs of the circuit corresponding to the M nodes of the digital pattern generator and for N outputs of the circuit corresponding to the N nodes of the general purpose output controller. The selection circuit may be configured to select, independently for each of the M outputs of the circuit, whether the particular value stored in the at least one memory element or the corresponding output signal of the digital pattern generator is provided on that output, and may be further configured to select, independently for each of the N outputs of the circuit, whether the standby value stored in the at least one memory element or the corresponding output signal of the general purpose output controller is provided on that output.09-11-2008
20080222440Real time clock calibration system - A temperature-based real time clock calibration system and method for performing the same. The system in one embodiment includes a real time clock calibrated against a reference frequency, a temperature sensor being operative to measure a instantaneous temperature T09-11-2008
20090150706WRAPPER CIRCUIT FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS SYSTEM AND METHOD FOR OPERATING THE SAME - Provided are a high-performance wrapper circuit for a globally asynchronous locally synchronous (GALS) system and a synchronization method using the same, which are capable of solving a synchronization problem caused when data are transmitted between locally synchronous modules employing different clocks, and a method for operating the wrapper circuit. The GALS system includes a clock generator for supplying an operation clock to a locally synchronous module, a sender port for transmitting data to the outside according to a data transmission request signal output from the locally synchronous module, and generating a first clock stop signal for stopping an operation of the clock generator, and a receiver port for receiving data from the outside, and generating a second clock stop signal for stopping the operation of the clock generator. The sender port generates the first clock stop signal to the clock generator when a next data transmission request signal is received before completing a data transmission performed by a previous data transmission request signal output from the locally synchronous module.06-11-2009
20110314323SEMICONDUCTOR DEVICE AND DATA PROCESSOR - To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.12-22-2011
20110314322TIME SYNCHRONIZATION SYSTEM AND SERVER USING SAME - A time synchronization system includes a host system, a BIOS module, a BMC module, and a RTC module. The BIOS module is embedded in the host system. The BMC module is connected with the BIOS module and communicates with the BIOS module. The RTC module communicates with the BMC module and provides time signals to the BMC module. The host system acquires the time signals from the BMC module through the BIOS module.12-22-2011
20110239030MESOCHRONOUS SIGNALING SYSTEM WITH CORE-CLOCK SYNCHRONIZATION - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.09-29-2011
20130159757MEMORY ARRAY CLOCK GATING SCHEME - Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.06-20-2013
20130159758SYNCHRONIZING COMPUTE NODE TIME BASES IN A PARALLEL COMPUTER - Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.06-20-2013
20120017107SYNCHRONOUS BUS DRIVING WITH REPEATERS - Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.01-19-2012
20120030498INTERACTIVE DEVICE WITH TIME SYNCHRONIZATION CAPABILITY - An interactive device having time synchronization capability is provided. In one embodiment, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements based on a particular time of the internal clock. A user may input and adjust the time of the internal clock. In another embodiment, a setup module is provided which includes a computer processor that stores a setup time. The setup module establishes a connection with an interactive device, and time synchronizes the interactive device such that the internal clock of the interactive device is running the same time as the setup module. The setup module is capable of synchronizing the internal clock of multiple interactive devices, despite the interactive devices being programmed on separate occasions. The interactive device may be synchronized by the setup module via a hard-wired connection or wireless means.02-02-2012
20120030497CONTROL CIRCUIT AND OPERATING METHOD THEREOF - A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal, and a clock supply block configured to sequentially supply the clock signals to the plurality of clock synchronization units.02-02-2012
20120030496Specification of Isochronous Data Transfer in a Graphical Programming Language - System and method for transferring data. A system diagram is displayed, where the system diagram includes multiple device icons corresponding to respective devices, each device icon having associated executable function nodes specified for deployment on the corresponding device. The function nodes are interconnected to form a distributed graphical program that is deployable and executable in a distributed manner on the devices. User input is received to the system diagram specifying isochronous data transfer among the function nodes. Invocation timing relationships among the function nodes are automatically determined based on the specified isochronous data transfer, including phase relationships between execution of the function nodes. The determined invocation timing relationships are displayed among the function nodes. The graphical program is deployable and executable in a distributed manner on the devices according to the determined invocation timing relationships, where during execution of the graphical program, data are transferred isochronously between the function nodes.02-02-2012
20120030495Clock Distribution in a Distributed System with Multiple Clock Domains Over a Switched Fabric - System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.02-02-2012
20130198554Systems and Methods for Idle Clock Insertion Based Power Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.08-01-2013
20120297231Interface for Storage Device Access Over Memory Bus - A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.11-22-2012
20120066537COMPOUND UNIVERSAL SERIAL BUS ARCHITECTURE PROVIDING PRECISION SYNCHRONISATION TO AN EXTERNAL TIMEBASE - A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.03-15-2012
20130205160SYNCHRONIZING DATA TRANSFER BETWEEN A FIRST CLOCK DOMAIN AND SECOND CLOCK DOMAIN - A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.08-08-2013
20120303995METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.11-29-2012
20120303994APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN - Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is clocked with the clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage is configured to take over an input data value in synchronization with the first clock domain and to provide an output data value in synchronization with the second clock domain and in response to a current synchronization pulse. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the subsequent synchronization pulse such that the subsequent synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The fill level information provider is configured to provide a fill level information describing a fill level of the first-in-first-out storage. The feedback path is configured for feeding back the fill level information to the calculator that is further configured to adjust the synchronization pulse cycle duration information based on the fill level information.11-29-2012
20120096301MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK - An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.04-19-2012
20130212420TIME-STAMPING OF INDUSTRIAL CLOUD DATA FOR SYNCHRONIZATION - A cloud-capable industrial device that provides time-stamped industrial data to a cloud platform is provided. The industrial device collects or generates industrial data in connection with monitoring and/or controlling an automation system, and includes a cloud interface that couples the industrial device to one or more cloud-based services running on a cloud platform. The industrial device can apply time stamps to respective items of industrial data reflecting a time that the data was measured or generated prior to providing the data to the cloud platform. To accurately reflect temporal relationships between data sets provided to the cloud platform from different locations and time zones, the industrial device can synchronize its internal clock with a clock associated with the cloud platform.08-15-2013

Patent applications in class SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES

Patent applications in all subclasses SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES