Class / Patent application number | Description | Number of patent applications / Date published |
712245000 | Processing sequence control (i.e., microsequencing) | 40 |
20080209192 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 08-28-2008 |
20080294884 | Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors - A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread. | 11-27-2008 |
20080294885 | Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution - A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution. | 11-27-2008 |
20090049288 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR RUNTIME INVOCATION OF AN APPROPRIATE VERSION OF PROGRAM INSTRUCTIONS IN AN ON-DEMAND DATABASE - In accordance with embodiments, there are provided mechanisms and methods for runtime invocation of an appropriate version of program instructions in an on-demand database service. These mechanisms and methods for providing such runtime invocation can enable embodiments to ensure that new versions of developed applications will operate in the same application environment of a previous version. The ability of embodiments to provide such runtime invocation may lead to an improved application migration development/runtime framework, etc. | 02-19-2009 |
20090119495 | Architectural Enhancements to CPU Microde Load Mechanism for Information Handling Systems - A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core. | 05-07-2009 |
20090158019 | Computer Program Code Size Partitioning System for Multiple Memory Multi-Processing Systems - The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic. | 06-18-2009 |
20090204800 | MICROPROCESSOR WITH MICROARCHITECTURE FOR EFFICIENTLY EXECUTING READ/MODIFY/WRITE MEMORY OPERAND INSTRUCTIONS - The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location. | 08-13-2009 |
20090217020 | Commit Groups for Strand-Based Computing - Strand-based computing hardware and dynamically optimizing strandware are included in a high performance microprocessor system. The system operates in real time automatically and unobservably to parallelize single-threaded software into parallel strands for execution by cores implemented in a multi-core and/or multi-threaded microprocessor of the system. The system organizes native instructions of the strands into commit groups. With respect to each commit group, results are either atomically committed or entirely discarded. A hierarchical two-level rollback mechanism enables rolling back at a granularity of a single one of the commit groups, or alternatively rollback at a granularity of an entire strand. The system operates to respond to local events (e.g. branch misprediction) via rollback of commit groups, and to global events (e.g. strand-level mis-speculation) via rollback of strands. Rolling back of commit groups of a particular strand only affects commit groups of the particular strand, leaving other strands unaffected. | 08-27-2009 |
20090307473 | METHOD FOR ADOPTING SEQUENTIAL PROCESSING FROM A PARALLEL PROCESSING ARCHITECTURE - Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order. | 12-10-2009 |
20100088496 | METHOD AND SYSTEM FOR EXECUTING AN EXECUTABLE FILE - A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the anonymous file by the first process, and accessing the executable file by the second process. | 04-08-2010 |
20100153694 | PROGRAM AND INFORMATION PROCESSING APPARATUS - A computer readable medium includes: storing an evaluation value and relating, to a plurality of evaluating target information, the evaluation value indicative of a possibility that a second processing for sequentially executing a first processing that is predetermined for each of the evaluating target information is successful; updating the evaluation value related to the evaluating target information based on a content of a third processing that is predetermined for the evaluating target information or information to be a processing target of the first processing corresponding to the evaluating target information when the third processing is executed; and determining an executing order in a sequential execution of the second processing for each of the evaluating target information based on the evaluation value. | 06-17-2010 |
20100223450 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD AND COMPUTER READABLE MEDIUM - A storage part stores correspondence information on incorporation or change in processing sequence of processing elements. An acquiring part acquires a target processing element group. An extracting part extracts the correspondence information on the processing elements included in the target processing element group. An incorporation determining part determines a set of processing elements to be incorporated in the target processing element group on the basis of the information on the incorporation of the correspondence information. An updating part updates the processing elements included in the target processing element group and the correspondence information of the processing elements included in the target processing element group based on the set of processing elements. A processing sequence determining part determines the processing sequence of the processing elements included in the target processing element group updated on the basis of the information on the change in processing sequence in the correspondence information updated. | 09-02-2010 |
20100241835 | PROCESSOR WITH AUTOMATIC SCHEDULING OF OPERATIONS - A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors. | 09-23-2010 |
20110016296 | APPARATUS AND METHOD FOR EXECUTING FAST BIT SCAN FORWARD/REVERSE (BSR/BSF) INSTRUCTIONS - An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector. Selection logic selects a concatenation of the third and fourth bit vectors into the fifth bit vector if an input indicates forward bit scan, and the selection logic selects an inverted version of a concatenation of the seventh and eighth bit vectors into the fifth bit vector if the input indicates reverse bit scan. | 01-20-2011 |
20110055531 | Synchronizing Commands and Dependencies in an Asynchronous Command Queue - Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue. | 03-03-2011 |
20110138158 | INTEGRATED CIRCUIT - The present invention allows an integrated circuit to easily control interfaces utilizing new interface types. In order to achieve the above, an ASIC ( | 06-09-2011 |
20110258423 | COMPUTER PROCESSOR AND METHOD WITH INCREASED SECURITY POLICIES - A computer processor | 10-20-2011 |
20110283096 | REGISTER FILE SUPPORTING TRANSACTIONAL PROCESSING - A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value. | 11-17-2011 |
20120023317 | DIGITAL DATA PROCESSING SYSTEMS - A digital data processing system that is designed to facilitate use of UML activity diagrams. | 01-26-2012 |
20120036343 | ELECTRONIC APPARATUS AND METER OPERABLE DURING PROGRAM UPDATING - There are provided an electronic apparatus and a meter which are operable during the updating of an operating program and firmware. The electronic apparatus operable during program updating includes an operation unit performing a preset operation, a micro controller controlling an operation result of the operation unit to be stored according to a predetermined period of storing time, and controlling a program received from the outside to be stored, an update controller allowing the program stored during the predetermined period of storing time to be updated in the micro controller, and a storing unit storing the program and the operation result under control of the micro controller. | 02-09-2012 |
20120144173 | UNIFIED SCHEDULER FOR A PROCESSOR MULTI-PIPELINE EXECUTION UNIT AND METHODS - A unified scheduler for a processor execution unit and methods are disclosed for providing faster throughput of micro-instruction/operation execution with respect to a multi-pipeline processor execution unit. In one example, an execution unit has a plurality of pipelines that operate at a predetermined clock rate, each pipeline configured to process a selected subset of microinstructions. The execution unit has a scheduler that includes a unified queue configured to queue microinstructions for all of the pipelines and a picker configured to direct a queued microinstruction to an appropriate pipeline for processing based on an indication of readiness for picking. Preferably, when all of the pipelines are ready to receive a microinstruction for processing and there is at least one microinstruction queued that is ready for picking for each pipeline, the picker picks and directs a queued microinstructions to each of the pipelines in a single clock cycle. | 06-07-2012 |
20120166777 | METHOD AND APPARATUS FOR SWITCHING THREADS - Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur. | 06-28-2012 |
20120210108 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first sequencer and a second sequencer. The first sequencer operates at a first frequency. The second sequencer operates at a second frequency that is higher than the first frequency. In the first mode, the first sequencer operates in accordance with an instruction received from an external apparatus, and the second sequencer operates under control of the first sequencer. In the second mode, the second sequencer operates in accordance with an instruction received from the external apparatus, and the operation of the first sequencer is stopped. | 08-16-2012 |
20130185546 | Method For Checking the Operability of a Digital Signal Processing Unit of a Position Sensor and Position Encoder - A method for checking the operability of a digital signal processing unit of a position sensor, wherein the digital signal processing unit executes an instruction queue of N instructions one after another in sequences, wherein an additional number of x instructions is executed by the digital signal processing unit during each sequence, wherein the additional instructions are provided in a unit different from the memory, and that the results of the additional instructions are stored. The results of the additional instructions are read by a microcomputer. The results of the additional instructions are compared by the microcomputer with the expected results achieved by execution of identical additional instructions by the microcomputer or with expected results stored in the microcomputer. This includes a position encoder comprising a digital signal processing unit for calculating position information. | 07-18-2013 |
20130339711 | METHOD AND APPARATUS FOR RECONSTRUCTING REAL PROGRAM ORDER OF INSTRUCTIONS IN MULTI-STRAND OUT-OF-ORDER PROCESSOR - A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence. | 12-19-2013 |
20140032887 | HYBRID HARDWIRED/PROGRAMMABLE RESET SEQUENCE CONTROLLER - A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register | 01-30-2014 |
20140115306 | Next Instruction Access Intent Instruction - Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction. | 04-24-2014 |
20140258697 | Apparatus and Method for Transitive Instruction Scheduling - A processor includes a multiple stage pipeline with a scheduler with a wakeup block and select logic. The wakeup block is configured to wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set. In a second cycle, the wakeup block wakes instructions dependent upon the wake instruction set to augment the wake instruction set. The select logic selects instructions from the wake instruction set based upon program order. | 09-11-2014 |
20140281442 | SYSTEM MANAGEMENT AND INSTRUCTION COUNTING - Techniques for managing a plurality of threads on a multi-threading processing core. Embodiments provide an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads. A first plurality of instructions for a first one of the plurality of threads is processed on the multi-threading processing core. Embodiments determine, for each of the first plurality of instructions, whether the instruction is a countable instruction, wherein at least one of the first plurality of instructions is not a countable instruction. A count of the countable instructions is maintained. Upon determining that the instruction count threshold condition is satisfied, based on the maintained count, embodiments context switch the multi-threading processing core to process a second plurality of instructions for a second one of the plurality of threads. | 09-18-2014 |
20140365754 | CONTEXT CONTROL AND PARAMETER PASSING WITHIN MICROCODE BASED INSTRUCTION ROUTINES - A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations. | 12-11-2014 |
20150095629 | METHOD AND SYSTEM FOR IMPLEMENTING RECOVERY FROM SPECULATIVE FORWARDING MISS-PREDICTIONS/ERRORS RESULTING FROM LOAD STORE REORDERING AND OPTIMIZATION - A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier. | 04-02-2015 |
20150293766 | PROCESSOR AND METHOD - A processor includes a plurality of processing units prepared for processing an instruction to be implemented at a plurality of stages and corresponding to the respective stages, and controller controls the plurality of processing units such that a processing unit for a preceding stage consecutively performs processing of a plurality of instructions, and then a processing unit for a subsequent stage consecutively performs processing of the plurality of instructions for which processing by the processing unit for the preceding stage has ended. | 10-15-2015 |
20160162292 | BINARY TRANSLATOR WITH PRECISE EXCEPTION SYNCHRONIZATION MECHANISM - A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The invention includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream; by “precise” is meant that the atomic execution of the source instructions is guaranteed, and that the application of actions, including those that originate from asynchronous exceptions, occurs at the latest at the completion of the current source instruction at the time of the request for the action. The binary translation and exception-handling subsystems are preferably included as components of a virtual machine monitor which is installed between the target hardware system and the source system, which is preferably a virtual machine. | 06-09-2016 |
20160179536 | Early termination of segment monitoring in run-time code parallelization | 06-23-2016 |
20180024835 | PC-RELATIVE ADDRESSING AND TRANSMISSION | 01-25-2018 |
20190146795 | BULK STORE AND LOAD OPERATIONS OF CONFIGURATION STATE REGISTERS | 05-16-2019 |
712246000 | Plural microsequencers (e.g., dual microsequencers) | 3 |
20090198986 | Configurable Instruction Sequence Generation - A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence. | 08-06-2009 |
20120144174 | MULTIFLOW METHOD AND APPARATUS FOR OPERATION FUSION - A method and apparatus for utilizing scheduling resources in a processor are disclosed. A complex operation is assigned for execution as two micro-operations; a first micro-operation and a second micro-operation. The first micro-operation, which may be an address-generation operation, is executed using at least one of a first processing unit or a load and store unit and the second micro-operation, which may be an execution operation, is executed using a second processing unit, where at least one operand of the second micro-operation is an outcome of the first micro-operation. | 06-07-2012 |
20120144175 | METHOD AND APPARATUS FOR AN ENHANCED SPEED UNIFIED SCHEDULER UTILIZING OPTYPES FOR COMPACT LOGIC - An integrated circuit is disclosed wherein microinstructions are selectively queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a selected subset of a set of supported microinstructions. The execution unit receives microinstruction data including an operation code OpCode and an operation type OpType. The OpType data being at least one bit less that a minimum binary size of an OpCode required to uniquely identify the microinstruction. The OpType data selected to indicate a category of microinstructions having common execution requirement characteristics. The microinstructions are selectively queued for pipeline processing by the execution unit pipelines based on the OpType without decoding the OpCode of the microinstruction. | 06-07-2012 |
712248000 | Writable/changeable control store architecture | 1 |
20100313002 | PRELOADING MODULES FOR PERFORMANCE IMPROVEMENTS - Described is a technology for preloading modules, such as modules that show clinical/medical data maintained at a service, so as to reduce a user's wait time to use a module. The modules for which a user is authenticated are preloaded according to a loading order that is based upon the user's historical usage data. If a user interacts to use a selected module that is not yet loaded, the selected module may be loaded immediately, independent of the order. A background thread preloads the modules according to the order. A normal thread loads the selected module, unless already being preloaded by the background thread; in either situation the loading thread's priority may be temporarily increased to expedite loading. The historical data may be in the form of weight values associated with the modules, with the weight values adjusted based upon module usage. | 12-09-2010 |