| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712244000 | Exeception processing (e.g., interrupts and traps) | 55 |
| 20080201566 | METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR - A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed. | 08-21-2008 |
| 20090193241 | Direct Register Access For Host Simulation - Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Various implementations of the invention provide for the processing of requests by the software to access memory within the embedded system. Still, various implementations of the invention provide for the identification of these memory access request and for the mapping of the desired memory location to a valid memory location. | 07-30-2009 |
| 20100077188 | EMERGENCY FILE PROTECTION SYSTEM FOR ELECTRONIC DEVICES - Disclosed is a method, system, and computer readable medium for completing critical write functions to a non-volatile memory (NVM) system within an electronic device upon experiencing a sudden or unexpected loss of the main power to the electronic device. A sudden loss of main external power is detected and determined if the loss of power crosses a minimum threshold level. If it does, an interrupt is generated to prevent new write requests. One embodiment uses a software interrupt and another embodiment uses a hardware interrupt. A switch over to a short term reserve internal power source occurs and the NVM write function in progress at the time of the power loss is completed. Upon completion of the NVM write operation, less critical shutdown activities can commence. | 03-25-2010 |
| 20090043997 | Time-Of-Life Counter For Handling Instruction Flushes From A Queue - Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values. | 02-12-2009 |
| 20090070570 | System and Method for Efficiently Handling Interrupts - A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt. | 03-12-2009 |
| 20090037710 | RECOVERY FROM NESTED KERNEL MODE EXCEPTIONS - A system and method for instrumentation of software, the software comprising a set of instructions (program or code) which are executable on a processor of a system, for example a computer system. A location in the instruction to insert a probe is first identified. The instruction is replaced with the probe by copying the instruction to a predefined location. The instruction is executed in the kernel space. A first exception is generated upon encountering the probe and calling a first exception handler, and the first exception handler is configured to call an instrumentation routine. A second exception is generated when the instrumentation routine encounters an error and calling a second exception handler, recovering from the exceptions and returning to a sane state to continue normal execution of the instruction. | 02-05-2009 |
| 20100169628 | Controlling non-redundant execution in a redundant multithreading (RMT) processor - In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed. | 07-01-2010 |
| 20100122073 | HANDLING EXCEPTIONS IN SOFTWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit. | 05-13-2010 |
| 20080250235 | Microcomputer and method of setting operation of microcomputer - Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates. | 10-09-2008 |
| 20080209191 | Nested exception roles - A method and apparatus for managing a nested EXCEPTION role in a directory server is described. In one embodiment, a plurality of entries is defined in the directory server. At least one of the plurality of entries possesses a role. An entry is queried to determine its possessed role. A nested EXCEPTION role possesses at least two roles. An entry possesses the nested EXCEPTION role by possessing none of the roles within the nested EXCEPTION role. | 08-28-2008 |
| 20090019273 | Exception-based error handling in an array-based language - A computer-readable medium stores computer-executable instructions. The medium may hold: one or more instructions for executing a first code block; one or more instructions for generating an exception object based on the executing of the first code block; one or more instructions for receiving the exception object at a second code block; and one or more instructions for storing the exception object in a memory. | 01-15-2009 |
| 20090187750 | Binary Translator with Precise Exception Synchronization Mechanism - A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The invention includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream; by “precise” is meant that the atomic execution of the source instructions is guaranteed, and that the application of actions, including those that originate from asynchronous exceptions, occurs at the latest at the completion of the current source instruction at the time of the request for the action. The binary translation and exception-handling subsystems are preferably included as components of a virtual machine monitor which is installed between the target hardware system and the source system, which is preferably a virtual machine. | 07-23-2009 |
| 20090049287 | Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution - This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty. | 02-19-2009 |
| 20090063832 | FAULT DISCOVERY AND SELECTION APPARATUS AND METHOD - A method and apparatus are disclosed for discovering and selecting faults where more than one programming model is involved. The present invention enables selection of faults and the mappings necessary to handle exceptions across multiple code environments. | 03-05-2009 |
| 20110225402 | Apparatus and method for handling exception events - Processing circuitry | 09-15-2011 |
| 20120079257 | METHODS AND SYSTEMS THAT DEFER EXCEPTION HANDLING - Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set. | 03-29-2012 |
| 20120079256 | Interrupt suppression - A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing. | 03-29-2012 |
| 20080263342 | Apparatus and method for handling exception signals in a computing system - Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and handles others with respect to a subject state derived from the target state. Signal handling sub-units are arranged to process the exception signal with respect to the target state and output a request either to return to execution or to pass on the exception signal. A delivery path selection unit is arranged to determine a delivery path of the exception signal to a selected group of the plurality of signal handling sub-units. A signal control unit is arranged to deliver the exception signal in turn to each of the selected group of signal handling sub-units. | 10-23-2008 |
| 20090055636 | METHOD FOR GENERATING AND APPLYING A MODEL TO PREDICT HARDWARE PERFORMANCE HAZARDS IN A MACHINE INSTRUCTION SEQUENCE - A computer implemented method, data processing system, and computer program product for generating and applying a model to predict hardware performance hazards in a machine instruction sequence. The illustrative embodiments generate rules which specify relationships between a first instruction code sequence and hardware performance hazards. This rule generation is performed as a machine task rather than a human task (e.g., traditional hand coding tools). When a second instruction code sequence is received, the rules are applied to the second instruction code sequence. Responsive to a prediction that execution of the second instruction code sequence will cause the hardware performance hazards, instructions in the second instruction code sequence that cause the hardware performance hazards are identified. | 02-26-2009 |
| 20080229084 | METHOD OF DETERMING REQUEST TRANSMISSION PRIORITY SUBJECT TO REQUEST CHANNEL AND TRANSTTING REQUEST SUBJECT TO SUCH REQUEST TRANSMISSION PRIORITY IN APPLICATION OF FIELDBUS COMMUNICATION FRAMEWORK - A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time. | 09-18-2008 |
| 20100262814 | HANDLING EXCEPTIONS RELATED TO CORRUPT APPLICATION STATE - An exception handling system is described herein that provides one or more distinguished classes of software exceptions that are handled differently than other exceptions. The system treats a distinguished exception as a “hard to catch” exception that is not passed to the catch block of program code unless a developer performs extra steps to acknowledge the distinguished nature of the exception and confirm that the program code is prepared to properly handle the exception. Exceptions that fall into this class are typically those that represent conditions from which normal exception handling practices cannot successfully recover, namely exceptions that corrupt application state. Accordingly, the system prevents the developer from catching these classes of exceptions by default unless the developer explicitly requests to have these exceptions delivered to the program code. Thus, the exception handling system encourages correct programming practices by preventing developer error by default. | 10-14-2010 |
| 20100235613 | METHOD, APPARATUS OR SOFTWARE FOR PROCESSING EXCEPTIONS PRODUCED BY AN APPLICATION PROGRAM - A method, apparatus and software is disclosed in which original exceptions issued by an application program are encoded as substitute exceptions with associated metadata identifying the original exception so as to enable to enable a first application program receiving the exception but not arranged to process the original exception to process the substitute exception and to enable a second application program receiving the exception and arranged to process the original exception to extract and process that original exception. | 09-16-2010 |
| 20120144172 | Interrupt Distribution Scheme - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 06-07-2012 |
| 20110066834 | CONCURRENT EXCEPTION HANDLING - Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown. | 03-17-2011 |
| 20080270775 | MANAGEMENT OF EXCEPTIONS AND HARDWARE INTERRUPTIONS BY AN EXCEPTION SIMULATOR - Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption. | 10-30-2008 |
| 20110040956 | Symmetric Multiprocessor Operating System for Execution On Non-Independent Lightweight Thread Contexts - A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator. | 02-17-2011 |
| 20110055530 | FAST REP STOS USING GRABLINE OPERATIONS - A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception. | 03-03-2011 |
| 20110078427 | TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT - A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment. | 03-31-2011 |
| 20100223449 | INTERRUPT HANDLING APPARATUS AND METHOD FOR EQUAL-MODEL PROCESSOR AND PROCESSOR INCLUDING THE INTERRUPT HANDLING APPARATUS - An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency. | 09-02-2010 |
| 20100131745 | EXCEPTIONAL EVENTS - An event-driven system enables handlers to be specified for success and failure, among other things. In other words, events can be explicitly encoded with an option of returning either a success or a failure result. In this manner, asynchronous programming and events can be unified. Multiple event streams can be employed to represent success and/or exceptional values. Alternatively, a disjoint union of regular and exceptional values can be employed with respect to a single event stream. | 05-27-2010 |
| 20110087867 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 04-14-2011 |
| 20120246453 | METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR - Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised. | 09-27-2012 |
| 20090217019 | Method for Processing Interrupt Requests in a Processor - A method for processing interrupt requests in a processor is suitable for executing at least two threads in parallel, wherein an instruction pipeline is provided for each of the at least two threads. One of the at least two threads is defined as a main thread for processing programs. Another thread of the at least two threads is assigned to the main thread as an interrupt thread. After an interrupt request is received, the processor stores interrupt data in a register assigned to the interrupt thread. Subsequently, the processing of an interrupt routine is started in the interrupt thread and at least part of the interrupt routine is executed in the interrupt thread. | 08-27-2009 |
| 20090217018 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY - Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction. | 08-27-2009 |
| 20110078426 | SYSTEMS AND METHODS FOR SCENARIO-BASED PROCESS MODELING - Methods and systems for scenario-based process modeling are described. In one example embodiment, a system for scenario-based process modeling can include a scenario module, a deviations module, a parallel tasks module, and a workflow generation engine. The scenario module is to receive a series of tasks to define a standard process flow. The deviations module is to receive a deviation from the standard process flow. The parallel tasks module is to enable identification of one or more parallel tasks. The workflow generation engine is to generate a workflow model based on the standard process flow, deviation, and one or more parallel tasks. | 03-31-2011 |
| 20110016295 | PROGRAMMABLE EXCEPTION PROCESSING LATENCY - A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with said CPU, and a control register coupled with said CPU, wherein the control register is operable to set the operation mode of said CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time. | 01-20-2011 |
| 20110016294 | TECHNIQUE FOR REPLAYING OPERATIONS USING REPLAY LOOK-AHEAD INSTRUCTIONS - A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation. Alternatively, if a blocking user-interface request occurred when the first operation was previously performed (such as a mandatory query), the replay look-ahead instruction may include one or more events associated with the user answer to the blocking user-interface request so that the same user answer may be provided when replaying the first operation. | 01-20-2011 |
| 20120204017 | Microprocessor for Executing Byte Compiled Java Code - A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. | 08-09-2012 |
| 20100185840 | PROPAGATING UNOBSERVED EXCEPTIONS IN A PARALLEL SYSTEM - A method of handling an exception in a parallel system includes constructing a task object, executing a method with the task object, and catching an exception with the task object during execution of the method. The exception is propagated in response to the task object becoming inaccessible without the exception having been observed. | 07-22-2010 |
| 20080294883 | Mock exceptions in a host add-in environment - Mock exceptions, including mock exception types, are defined by a host to be raised in a plug-in. The mock exceptions might be sanitized. They might be transported from the plug-in to the host. Mock exceptions might also be mapped to real exceptions, which are raised in the host and handled by the host. | 11-27-2008 |
| 20090172372 | METHODS AND APPARATUS FOR GENERATING SYSTEM MANAGEMENT INTERRUPTS - A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed. | 07-02-2009 |
| 20120066484 | PATCHING METHOD AND PATCHING DEVICE IN MULTI-CORE ENVIRONMENT - A patching mechanism in a multi-core environment that includes sending an inter-core non-maskable interrupt to each target Virtual Central Processing Unit (CPU) (VCPU) in a target VCPU group, which share a code segment, so that said each target VCPU enters a patch synchronization state in response to the inter-core non-maskable interrupt. Thereafter, the patch synchronization state of said each target VCPU is monitored, and after all the target VCPUs have entered the patch synchronization state, embodiments modify a first instruction of an original function to be patched of said each target VCPU into an abnormal instruction, and outputting a patch synchronization state end notification to all the target VCPUs, so that the original function to be patched is enabled to jump to a new patch function in an exception handling process. | 03-15-2012 |
| 20120159133 | BUSINESS EXCEPTION MANAGEMENT PATTERN FOR BUSINESS PROCESSES - Handling business process exceptions. A method includes a computing system using a template, causing one or more operations to be performed to determine a problem that caused a business process exception. The computing system uses a template to cause one or more operations to be performed to perform one or more repair operations to address the business process exception. The computing system uses a template, to cause one or more operations to be performed to take action on the business process exception. | 06-21-2012 |
| 20120159134 | EXCEPTION CONTROL METHOD, SYSTEM, AND PROGRAM - A method for programmably controlling an exception includes performing, by a processor, a step of executing a control specification instruction for exception control specification that indicates whether an exception is enabled or not and setting a control specification value for the exception in a register and a step of executing a control execution instruction for exception control execution that indicates whether the exception is to be raised or not, determining whether the control specification value set in the register is a value for enabling the exception, and, when the control specification value is the value for enabling the exception, raising the exception. The method further includes performing a step of not raising the exception when the control specification value set in the register is not the value for enabling the exception. | 06-21-2012 |
| 20080320290 | EXCEPTION-BASED TIMER CONTROL - A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in response to the exception and based on a characteristic of the exception. A method of utilizing the processing device includes receiving an exception and determining a characteristic of the exception. The method further includes, at a first time, selectively enabling/disabling the timer of the processing device based on the characteristic, and, at a second time subsequent to the first time, accessing a count value stored at the timer. The method further includes providing the count value for output from the processing device. | 12-25-2008 |
| 20080320291 | Concurrent exception handling - Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown. | 12-25-2008 |
| 20100174893 | RUNTIME CHECKING OF DYNAMIC SUBRANGES - Software defects (e.g., array access out of bounds, stack overflow, infinite loops, and data corruption) occur due to integer values falling outside their expected range. Because programming languages do not include range-checking instructions as part of their language, to detect software defects and ensure that the code runs smoothly, programmers generally use 1) runtime assertions and/or 2) sub-range data types. However, these techniques cause additional conditional branches, incur additional overhead, and decrease processor performance. Processors comprising a range checking hardware feature supported by machine instructions for runtime integer range checking can eliminate the conditional branches generated during runtime integer range checks. Programming language extensions for the range checking hardware can allow dynamic range bounds to be defined during runtime without decreasing the processor's performance. This can allow for easier programming and code that is easier to maintain. | 07-08-2010 |
| 20120173855 | Exception Transporting and Handling of Concurrent Exceptions - Methods and systems for handling exceptions, including being provided with a catch list, the catch list being a flattened inheritance tree for exception types in ascending inheritance order, receiving an exception from a thread, searching the catch list in ascending inheritance order to find a matching exception type to received exception. | 07-05-2012 |
| 20120233446 | Program-Instruction-Controlled Instruction Flow Supervision - A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly. | 09-13-2012 |
| 20100011196 | Method and program network for exception handling - A method and a program network for exception handling are described. At least one error program element including an input and an output and an item of exception information stored for exception handling in the form of a data structure are defined in a graphical programming language. | 01-14-2010 |
| 20120317403 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND INTERRUPT METHOD - A multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core. | 12-13-2012 |
| 20120084540 | DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT - A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith. | 04-05-2012 |
| 20120239915 | Interrupt Handling - Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another. | 09-20-2012 |
| 20120102303 | Exception control in a multiprocessor system - A data processing apparatus is provided with a plurality of processing units ( | 04-26-2012 |
| 20130024676 | Control flow integrity - In at least some embodiments, a processor in accordance with the present disclosure is operable to enforce control flow integrity. For examiner, a processor may comprise logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. | 01-24-2013 |
