Class / Patent application number | Description | Number of patent applications / Date published |
712235000 | Simultaneous parallel fetching or executing of both branch and fall-through path | 6 |
20080270773 | Processing element having dual control stores to minimize branch latency - Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches). | 10-30-2008 |
20080288759 | Memory-hazard detection and avoidance instructions for vector processing - A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses. Note that critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially. Furthermore, an execution unit within the processor is configured to execute the instructions for detecting the one or more critical memory hazards. | 11-20-2008 |
20110219221 | Dynamic warp subdivision for integrated branch and memory latency divergence tolerance - Dynamic warp subdivision (DWS), which allows a single warp to occupy more than one slot in the scheduler without requiring extra register file space, is described. Independent scheduling entities also allow divergent branch paths to interleave their execution, and allow threads that hit in the cache or otherwise have divergent memory-access latency to run ahead. The result is improved latency hiding and memory level parallelism (MLP). | 09-08-2011 |
20130046964 | SYSTEM AND METHOD FOR ZERO PENALTY BRANCH MIS-PREDICTIONS - A system and method may execute a branch instruction in a program. The branch instruction may be received defining a plurality of different possible instruction paths. Instructions for an initial predefined one of the paths may be automatically retrieved from a program memory while the correct path is being determined. If the initial path is determined to be correct, the instructions retrieved for the initial path may continue to be processed and if a different path is determined to be correct, instructions from a stored reserve of instructions may be processed for the different path to supply the program with enough correct path instructions to run the program at least until the program retrieves the correct path instructions from the program memory to recover from taking the incorrect path. The system and method may recover from taking the incorrect path with zero computational penalty. | 02-21-2013 |
20130346731 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS - Instructions are tracked in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group. | 12-26-2013 |
20160062769 | COMBINING INSTRUCTIONS FROM DIFFERENT BRANCHES FOR EXECUTION IN A SINGLE PROCESSING ELEMENT OF A MULTITHREADED PROCESSOR - A data processing system includes a processor operable to execute a program partitioned into a number of discrete instructions, the processor having multiple processing elements each capable of executing more than one instruction per cycle, and an interface configured to read a first program and, on detecting a branch operation by that program creating m number of branches each having a different sequence of instructions, combine an instruction from one of the branches with an instruction from at least one of the other branches so as to cause a processing element to execute the combined instructions during a single cycle. | 03-03-2016 |