| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712223000 | Logic operation instruction processing | 36 |
| 20120204014 | Systems and Methods for Improving Divergent Conditional Branches - Embodiments of the present invention provide systems, methods, and computer program products for improving divergent conditional branches in code being executed by a processor. For example, in an embodiment, a method comprises detecting a conditional statement of a program being simultaneously executed by a plurality of threads, determining which threads evaluate a condition of the conditional statement as true and which threads evaluate the condition as false, pushing an identifier associated with the larger set of the threads onto a stack, executing code associated with a smaller set of the threads, and executing code associated with the larger set of the threads. | 08-09-2012 |
| 20100077187 | System and Method to Execute a Linear Feedback-Shift Instruction - A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data. | 03-25-2010 |
| 20130067205 | INSTRUCTION PACKET INCLUDING MULTIPLE INSTRUCTIONS HAVING A COMMON DESTINATION - An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination. | 03-14-2013 |
| 20110191570 | Method And Apparatus For Performing Logical Compare Operations - A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting one or more flags, which in turn may be utilized by a branching unit. Alternatively, the branch support actions may include branching to an indicated target code location. | 08-04-2011 |
| 20100100714 | System and Method of Indirect Register Access - Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address. | 04-22-2010 |
| 20090089556 | High-Speed Add-Compare-Select (ACS) Circuit - A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay. | 04-02-2009 |
| 20090292904 | APPARATUS AND METHOD FOR DISABLING A MICROPROCESSOR THAT PROVIDES FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that is configured to transfer program control to one of a plurality of event handlers within the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20100293358 | DYNAMIC PROCESSOR-SET MANAGEMENT - A dynamic processor-set management method provides for transferring a process from a shared processor set to a dedicated processor set when that process meets a first utilization-related criterion. The method also provides for transferring a process between from a dedicated processor set to a shared processor set when that process meets a second utilization-related criterion. The processor sets are mapped to processor cores that execute the processes. | 11-18-2010 |
| 20090177870 | Method and System for a Wiring-Efficient Permute Unit - A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit. | 07-09-2009 |
| 20090100253 | METHODS FOR PERFORMING EXTENDED TABLE LOOKUPS - A permutation instruction generates vector elements for a destination register using identified source and destination registers. A plurality of partial table lookups corresponding to an extended table produces a plurality of intermediate results. At least one source register stores a plurality of index values corresponding to the extended table. Out-of-range index values are values that are not contained in at least one additional source register and result in a predetermined constant value being stored into a predetermined vector element of the destination register. The index values are adjusted between the partial table lookups. A final result is formed by performing a logic function with the plurality of intermediate results. The final result is thereby formed without a full table lookup of each element of the final result. | 04-16-2009 |
| 20080307206 | METHOD AND APPARATUS TO EFFICIENTLY EVALUATE MONOTONICITY - A method and processor to evaluate a monotonicity of a set of input values is disclosed. The processor achieves high processing power by means of an arbitrary number of identical parallel processing elements. Each processing element allows instruction dependent data paths and makes use of ALU factories which consist of a number of separate arithmetic logical units (ALUs) are arranged in a special kind of matrix. The processor allows parallel evaluation and analysis of the monotonicity of a multitude of sets of values. A threshold value can be freely configured to allow an uncertainty of nearly equal values which is of high importance in digital signal processing. | 12-11-2008 |
| 20100217960 | Method of Performing Serial Functions in Parallel - A method for performing serial functions in parallel, where a datapath is divided into several independent stages, or pipeline stages, so that logical functions can be implemented in each pipeline stage concurrently. In an illustrative embodiment of the invention, a pipelined logic tree is described. This method allows for n-bits to be input to the system and n-bits to output from the system concurrently. | 08-26-2010 |
| 20120144170 | DYNAMICALLY SCALABLE PER-CPU COUNTERS - Embodiments include a reference counting system and method for a multiprocessor system including distributed per-CPU counters having a dynamically variable batch size. A global counter is dynamically updated as each per-CPU counter reaches its associated batch size. An initial batch size provides a desired scalability. The batch size is automatically reduced as the global count approaches a predefined target, to increase the accuracy of the global count. Counting can be performed atomically using architecturally supported atomic operations. Using synchronized counters, counting can be done with a lock held by each processor to provide the necessary mutual exclusion for performing the atomic operations. | 06-07-2012 |
| 20090319759 | SEAMLESS FREQUENCY SEQUESTERING - A method and apparatus for seamless frequency sequestering is herein described. In response to a frequency throttle event, controlling software, such as an OS, is provided access to a throttled amount of frequency associated with the frequency throttle event, while another amount of frequency is transparently sequestered for performance of non-controlling software tasks. | 12-24-2009 |
| 20100318773 | INCLUSIVE "OR" BIT MATRIX COMPARE RESOLUTION OF VECTOR UPDATE CONFLICT MASKS - A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array. | 12-16-2010 |
| 20100185837 | Reconfigurable Logic Automata - A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. A reconfigurable asynchronous logic element comprises a set of edges for communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring tokens to at least one neighboring cell, circuitry configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, and circuitry. A reconfigurable lattice of asynchronous logic automata comprises a plurality of reconfigurable logic automata that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic elements. | 07-22-2010 |
| 20080276078 | Method and Apparatus for Context Address Generation for Motion Vectors and Coefficients - A method for high/low usage is provided. The method receives a macroblock data structure and a syntax element at a digital signal processing engine. Further, the method classifies the syntax element as high use or low use. In addition, the method sends the syntax element from the digital signal processing engine to a logic unit, distinct from the digital processing engine, for binarization if the syntax element is high use. | 11-06-2008 |
| 20090249041 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES - A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device. | 10-01-2009 |
| 20080256343 | Convergence determination and scaling factor estimation based on sensed switching activity or measured power consumption - A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data. | 10-16-2008 |
| 20110153997 | Bit Range Isolation Instructions, Methods, and Apparatus - Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed. | 06-23-2011 |
| 20110258419 | Attaching And Virtualizing Reconfigurable Logic Units To A Processor - In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed. | 10-20-2011 |
| 20080222399 | METHOD FOR THE HANDLING OF MODE-SETTING INSTRUCTIONS IN A MULTITHREADED COMPUTING ENVIRONMENT - The present invention relates to the provisioning of mode-setting instruction as they relate to requisite hardware within a processing system. As such, the processing system allows for multiple programs, or processing threads of execution, to independently specify Modes, wherein modes are program specified assertions in regard to the processing system hardware environment (e.g., the temperature, voltage, frequency, gating functions, etc.). Thus, the objectives of the present invention are to facilitate a mutually acceptable environment for all of the processing threads that are being executed within a processing system; this objecting being subject to the respective processing requirements as requested by Mode-setting instructions that are specified by each executed processing thread. | 09-11-2008 |
| 20110138156 | METHOD AND APPARATUS FOR EVALUATING A LOGICAL EXPRESSION AND PROCESSOR MAKING USE OF SAME - A method and associated processor suitable for executing machine instructions for evaluating a logical expression are provided. The approach suggested makes use of a memory and an extended set of instructions. The memory, which can be embodied in a general purpose register for example, is for storing information related to an intermediate results obtained in evaluating the logical expression as well as a nesting level of sub-expressions in the logical expression being evaluated. The extended set of instruction allows for initializing and updating the information in that memory. A processor for executing the extended set of instruction is also provided along with a process for generating machine code making use of this extended set of instructions for evaluating a logical expression. | 06-09-2011 |
| 20090164762 | OPTIMIZING XOR-BASED CODES - A “code optimizer” provides various techniques for optimizing arbitrary XOR-based codes for encoding and/or decoding of data. Further, the optimization techniques enabled by the code optimizer do not depend on any underlining code structure. Therefore, the optimization techniques provided by the code optimizer are applicable to arbitrary codes with arbitrary redundancy. As such, the optimized XOR-based codes generated by the code optimizer are more flexible than specially designed codes, and allow for any desired level of fault tolerance. Typical uses of XOR-based codes include, for example, encoding and/or decoding data using redundant data packets for data transmission real-time communications systems, encoding and/or decoding operations for storage systems such as RAID arrays, etc. | 06-25-2009 |
| 20120047355 | Information Processing Apparatus Performing Various Bit Operation and Information Processing Method Thereof - An information processing apparatus operates data stored in an input register for each bit and stores a result thereof in an output register. A selector circuit selects output data of a bit from input data of 128 bits in the input register. An AND circuit outputs, only when data from a corresponding selector circuit is valid, the data to a corresponding bit of the output register. A control signal generator inputs a select signal indicating the number of a bit to be selected to each selector circuit, and also inputs a signal indicating whether data input from the selector circuit is valid or invalid to each AND circuit. | 02-23-2012 |
| 20120030451 | PARALLEL AND LONG ADAPTIVE INSTRUCTION SET ARCHITECTURE - An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status. | 02-02-2012 |
| 20120072704 | "OR" BIT MATRIX MULTIPLY VECTOR INSTRUCTION - A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system. | 03-22-2012 |
| 20120216021 | Performing An All-To-All Data Exchange On A Plurality Of Data Buffers By Performing Swap Operations - Methods, apparatus, and products are disclosed for performing an all-to-all exchange on n number of data buffers using XOR swap operations. Each data buffer has n number of data elements. Performing an all-to-all exchange on n number of data buffers using XOR swap operations includes for each rank value of i and j where i is greater than j and where i is less than or equal to n: selecting data element i in data buffer j; selecting data element j in data buffer i; and exchanging contents of data element i in data buffer j with contents of data element j in data buffer i using an XOR swap operation. | 08-23-2012 |
| 20100299506 | ROTATE THEN OPERATE ON SELECTED BITS FACILITY AND INSTRUCTIONS THEREFORE - A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register. | 11-25-2010 |
| 20100049952 | MICROPROCESSOR THAT PERFORMS STORE FORWARDING BASED ON COMPARISON OF HASHED ADDRESS BITS - An apparatus for decreasing the likelihood of incorrectly forwarding store data includes a hash generator, which hashes J address bits to K hashed bits. The J address bits are a memory address specified by a load/store instruction, where K is an integer greater than zero and J is an integer greater than K. The apparatus also includes a comparator, which outputs a first value if L address bits specified by the load instruction match L address bits specified by the store instruction and K hashed bits of the load instruction match corresponding K hashed bits of the store instruction, and otherwise to output a second value, where L is greater than zero. The apparatus also includes forwarding logic, which forwards data from the store instruction to the load instruction if the comparator outputs the first value and foregoes forwarding the data when the comparator outputs the second value. | 02-25-2010 |
| 712224000 | Masking | 6 |
| 20090049283 | INFORMATION PROCESSING DEVICE AND INSTRUCTION EXECUTING METHOD - An information processing device including registers ( | 02-19-2009 |
| 20100169619 | Efficient Encoding for Detecting Load Dependency on Store with Misalignment - In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation. | 07-01-2010 |
| 20090150655 | METHOD OF UPDATING REGISTER, AND REGISTER AND COMPUTER SYSTEM TO WHICH THE METHOD CAN BE APPLIED - A register updating method includes generating third information including first information and second information, wherein the first information indicates whether updating of regions of a register block is allowed and the second information includes information that is to be updated in the register block, transmitting the third information to an address of the register block that is to be updated, and selecting a part of the second information in a unit of the regions and writing the selected second information to the register block, based on the first information included in the received third information. | 06-11-2009 |
| 20090089557 | UTILIZING MASKED DATA BITS DURING ACCESSES TO A MEMORY - Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted. | 04-02-2009 |
| 20090077354 | Techniques for Predicated Execution in an Out-of-Order Processor - A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved. | 03-19-2009 |
| 20100023734 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXECUTING A HIGH LEVEL PROGRAMMING LANGUAGE CONDITIONAL STATEMENT - A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement. | 01-28-2010 |
