Class / Patent application number | Description | Number of patent applications / Date published |
712042000 | Operation | 77 |
20080263323 | Reconfigurable Computing Architectures: Dynamic and Steering Vector Methods - A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution units. The instruction queue stores a plurality of instructions to be executed by at least one of the reconfigurable execution units. The configuration selection unit analyzes the dependency of instructions stored in the instruction queue to determine an error metric value for each of the steering vector processing hardware configurations indicative of an ability of a reconfigurable slot configured with the steering vector processing hardware configuration to execute the instructions in the instruction queue, and chooses one of the steering vector processing hardware configurations based upon the error metric values. The configuration loader determines whether one or more of the reconfigurable slots are available and reconfigures at least one of the reconfigurable slots with at least a part of the chosen steering vector processing hardware configuration responsive to at least one of the reconfigurable slots being available. | 10-23-2008 |
20090100249 | METHOD AND APPARATUS FOR ALLOCATING ARCHITECTURAL REGISTER RESOURCES AMONG THREADS IN A MULTI-THREADED MICROPROCESSOR CORE - One embodiment of a microprocessor core capable of executing a plurality of threads substantially simultaneously includes a plurality of register resources available for use by the threads, where the register resources are fewer in number than the number threads multiplied by a number of architectural register resources required per thread, and a supervisor for allocating the register resources among the plurality of threads. | 04-16-2009 |
20090187738 | SIMD-TYPE MICROPROCESSOR, METHOD OF PROCESSING DATA, IMAGE DATA PROCESSING SYSTEM, AND METHOD OF PROCESSING IMAGE DATA - Disclosed is an SIMD-type microprocessor comprising a processor element group, plural processor elements with an operation part and a register file being arranged therein and a processor element control signal generator configured to output a processor element control signal controlling an operation of the processor element, wherein a feed part configured to feed a processor element control signal output from the processor element control signal generator to the processor element is provided at a center of the processor element group. | 07-23-2009 |
20090300327 | EXECUTION ENGINE - The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. Possible applications include many types of digital signal processing computations, such as filtering, convolution, and deconvolution, as well as many types of linear algebra operators, such as iterative and direct solvers, singular value decomposition, and constraint optimization. The invention improves energy efficiency of these structured parallel operators as compared to a regular data flow or von Neumann computer. | 12-03-2009 |
20090327655 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD PERFORMED BY SEMICONDUCTOR DEVICE - The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information. | 12-31-2009 |
20100058031 | Executing A Service Program For An Accelerator Application Program In A Hybrid Computing Environment - Executing a service program for an accelerator application program in a hybrid computing environment that includes a host computer and an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module; where the service program includes a host portion and an accelerator portion and executing a service program for an accelerator includes receiving, from the host portion, operating information for the accelerator portion; starting the accelerator portion on the accelerator; providing, to the accelerator portion, operating information for the accelerator application program; establishing direct data communications between the host portion and the accelerator portion; and, responsive to an instruction communicated directly from the host portion, executing the accelerator application program. | 03-04-2010 |
20100191935 | Architecture and implementation method of programmable arithmetic controller for cryptographic applications - An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography. | 07-29-2010 |
20100191936 | Method and system for operating-system-independent power management using performance verifications - Systems and methods are disclosed for power management in information handling systems using processor performance data to validate changes to processor performance states. Processor utilization data and processor performance data is obtained during system operation. The processor utilization data is analyzed to determine a desired performance state for the processor. Before setting the actual performance state of the processor to this desired performance state, however, processor performance data is analyzed to determine if prior changes to the performance state have been effective. The performance state of the processor is then changed are maintained based upon this additional performance verification analysis. | 07-29-2010 |
20100241830 | Transfer Triggered Microcontroller with Orthogonal Instruction Set - A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and the destination module to which data is to be stored. The address/data capability of an instruction word may be extended via a prefix module. If an operation is performed on the data, the source module or the destination module may perform the operation during the same clock cycle in which the data is transferred. | 09-23-2010 |
20100241831 | DATA PACKET PROCESSING METHOD FOR A MULTI CORE PROCESSOR - A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection to a network between the network and a designated CPU core, such that for all data packets received from the network an interrupt is created in the designated CPU core for received data packet processing. Each data packet received from the network is associated with an application connection established in a CPU core selected based on processor load and an interrupt thread is created on the CPU core associated with the application connection for processing the data packet. Each data packet being sent to the network is associated with an application connected established either in the CPU core in which the application is executing or an alternative CPU core selected based on processor load. Where the application connection is established in an alternative CPU core, an interrupt thread is created on the CPU core associated with the connection for processing the data packet. | 09-23-2010 |
20110153984 | DYNAMIC VOLTAGE CHANGE FOR MULTI-CORE PROCESSING - Embodiments of the disclosure generally set forth techniques for supplying different voltage levels and clock signals to a processor core. One example method includes determining a first workload of a first processor core in the multi-core processor for performing a first computing task associated with a first image area and a first geometric mapping between the first computing task and the first processor core, selecting a first voltage level or a first clock signal having a first clock frequency for the first processor core based on the determined first workload, wherein the first voltage level is compatible with the selected first clock frequency, initiating a voltage change to the first processor core based on the selected first voltage level, and initiating a clock change to the first processor core based on the selected first clock signal having the first clock frequency. | 06-23-2011 |
20110153985 | SYSTEMS AND METHODS FOR QUEUE LEVEL SSL CARD MAPPING TO MULTI-CORE PACKET ENGINE - The present invention is directed towards systems and methods for distributed operation of a plurality of cryptographic cards in a multi-core system. In various embodiments, a plurality of cryptographic cards providing encryption/decryption resources are assigned to a plurality of packet processing engines in operation on a multi-core processing system. One or more cryptographic cards can be configured with a plurality of hardware or software queues. The plurality of queues can be assigned to plural packet processing engines so that the plural packet processing engines share cryptographic services of a cryptographic card having multiple queues. In some embodiments, all cryptographic cards are configured with multiple queues which are assigned to the plurality of packet processing engines configured for encryption operation. | 06-23-2011 |
20110179253 | EFFICIENT MULTI-CORE PROCESSING OF EVENTS - A computer implemented method for handling events in a multi-core processing environment is provided. The method comprises handling an event by a second application running on a second core, in response to determining that the event is initiated by a first application running on a first core; and running a third application on the first core, while the first application is waiting for the event to be handled by the second application. | 07-21-2011 |
20110185155 | MICROPROCESSOR THAT PERFORMS FAST REPEAT STRING LOADS - A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a cache memory of the microprocessor a series of cache lines implicated by a string of data bytes specified by the instruction. A memory subsystem of the microprocessor guarantees within architectural limits that the cache line specified by each GPREFETCH instruction will be fetched into the cache. The memory subsystem completes each GPREFETCH instruction once it determines that no conditions exist that would prevent fetching the cache line specified by the GPREFETCH instruction and once it allocates a fill queue buffer to receive the cache line. A retire unit frees a reorder buffer entry allocated to each GPREFETCH instruction in response to completion of the GPREFETCH instruction regardless of whether the cache line specified by the GPREFETCH instruction has been fetched into the cache. | 07-28-2011 |
20110289297 | INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE - A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream. | 11-24-2011 |
20120011345 | Utilization Of A Microcode Interpreter Built In To A Processor - Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized. | 01-12-2012 |
20120011346 | MICROCODE-BASED CHALLENGE/RESPONSE PROCESS - Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a challenge from a service requiring authentication, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, tampering by potentially abusive device software may be avoided. | 01-12-2012 |
20120023310 | Intermediate Language Accelerator Chip - An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine. | 01-26-2012 |
20120066476 | MICRO-OPERATION PROCESSING SYSTEM AND DATA WRITING METHOD THEREOF - A data writing method and a micro-operation processing system are provided. The micro-operation processing system is adapted to access a plurality of registers and each of the registers defines at least one logic storing area. The data writing method comprises the following steps: executing a first micro-operation; selecting a target area of the first micro-operation, which has been updated by the second micro-operation before, as one of the logic storing areas; assigning each of the first micro-operation and the second micro-operation a respective identification number; determining that a execution order of the first micro-operation is later than a execution order of the second micro-operation according to the identification numbers of the first micro-operation and the second micro-operation; and recording that the target area has been updated by the first micro-operation. | 03-15-2012 |
20120144161 | CARRYLESS MULTIPLICATION PREFORMATTING APPARATUS AND METHOD - An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result. | 06-07-2012 |
20120221834 | PROCESSOR ARCHITECTURE - A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction. | 08-30-2012 |
20130013893 | PORTABLE HANDHELD DEVICE WITH MULTI-CORE MICROCODED IMAGE PROCESSOR - A portable handheld device includes a CPU for processing a script; a multi-core processor for processing images; and a flash memory connected to the CPU, the flash memory storing therein a table of micro-codes. The multi-core processor includes a plurality of micro-coded processing units. The CPU is configured to read one or more micro-codes from the flash memory and load the one or more micro-codes into the processing unit to execute the script being processed thereby | 01-10-2013 |
20130024660 | PORTABLE HANDHELD DEVICE WITH MULTI-CORE IMAGE PROCESSOR - A portable handheld device includes an image sensor for capturing an image; and a one-chip microcontroller having integrated therein a CPU for processing a script language and a multi-core processor for processing an image captured by the image sensor. The multi-core processor includes therein multiple processing units connected in parallel by a crossbar switch. Each processing unit includes an arithmetic and logic unit (ALU). Each ALU includes a first register set for accepting data from the first crossbar switch, and a second register set for loading data to the crossbar switch. | 01-24-2013 |
20130054939 | INTEGRATED CIRCUIT HAVING A HARD CORE AND A SOFT CORE - An integrated circuit (IC) is disclosed. The integrated circuit includes a non-reconfigurable multi-threaded processor core that implements a pipeline having n ordered stages, wherein n is an integer greater than 1. The multi-threaded processor core implements a default instruction set. The integrated circuit also includes reconfigurable hardware that implements n discrete pipeline stages of a reconfigurable execution unit. The n discrete pipeline stages of the reconfigurable execution unit are pipeline stages of the pipeline that is implemented by the multi-threaded processor core. | 02-28-2013 |
20130061023 | COMBINING DATA VALUES THROUGH ASSOCIATIVE OPERATIONS - A method for combining data values through associative operations. The method includes, with a processor, arranging any number of data values into a plurality of columns according to natural parallelism of the associative operations and reading each column to a register of an individual processor. The processors are directed to combine the data values in the columns in parallel using a first associative operation. The results of the first associative operation for each column are stored in a register of each processor. | 03-07-2013 |
20130080739 | SIMD PROCESSOR AND CONTROL PROCESSOR, AND PROCESSOR ELEMENT - To improve processing efficiency of a SIMD processor that divides two-dimensional data into blocks, each having a width of PE number N, to store the data in a local memory of each of PEs by a lateral direction priority method. | 03-28-2013 |
20130086358 | COLLECTIVE OPERATION PROTOCOL SELECTION IN A PARALLEL COMPUTER - Collective operation protocol selection in a parallel computer that includes compute nodes may be carried out by calling a collective operation with operating parameters; selecting a protocol for executing the operation and executing the operation with the selected protocol. Selecting a protocol includes: iteratively, until a prospective protocol meets predetermined performance criteria: providing, to a protocol performance function for the prospective protocol, the operating parameters; determining whether the prospective protocol meets predefined performance criteria by evaluating a predefined performance fit equation, calculating a measure of performance of the protocol for the operating parameters; determining that the prospective protocol meets predetermined performance criteria and selecting the protocol for executing the operation only if the calculated measure of performance is greater than a predefined minimum performance threshold. | 04-04-2013 |
20130103929 | COUPLING PROCESSORS TO EACH OTHER FOR HIGH PERFORMANCE COMPUTING (HPC) - A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard. | 04-25-2013 |
20130132708 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a first core that is of a multi-core processor and configured to detect preprocessing for access of shared resources by a second core that is of the multi-core processor excluding the first core, when the first core is accessing the shared resources shared by the multi-core processor; and switch a task being executed by the second core to another task upon detecting the preprocessing. | 05-23-2013 |
20130151815 | RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR - A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected. | 06-13-2013 |
20140019717 | SYNCHRONIZATION METHOD, MULTI-CORE PROCESSOR SYSTEM, AND SYNCHRONIZATION SYSTEM - A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs. | 01-16-2014 |
20140059325 | INTEGRATED CIRCUIT APPARATUS, THREE-DIMENSIONAL INTEGRATED CIRCUIT, THREE-DIMENSIONAL PROCESSOR DEVICE, AND PROCESS SCHEDULER, WITH CONFIGURATION TAKING ACCOUNT OF HEAT - The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately. | 02-27-2014 |
20140101411 | Dynamically Switching A Workload Between Heterogeneous Cores Of A Processor - In one embodiment, a policy manager may receive operating system scheduling information, performance prediction information for at least one future quantum, and current processor utilization information, and determine a performance prediction for a future quantum and whether to cause a switch between asymmetric cores of a multicore processor based at least in part on this received information. Other embodiments are described and claimed. | 04-10-2014 |
20140156971 | Range Selection for Data Parallel Programming Environments - According to some embodiments, the workgroup divisibility requirement may be dispensed with on a selective or permanent basis, i.e. in all cases, particular cases or at particular times and/or under particular conditions. An application programming interface implementation may be allowed to launch workgroups with non-uniform local sizes. Two different local sizes may be used in a case of a one-dimensional workload. | 06-05-2014 |
20140189304 | BIT-LEVEL REGISTER FILE UPDATES IN EXTENSIBLE PROCESSOR ARCHITECTURE - This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register. | 07-03-2014 |
20140281382 | MODIFIED EXECUTION USING CONTEXT SENSITIVE AUXILIARY CODE - A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code. | 09-18-2014 |
20140281383 | GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE - A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling. | 09-18-2014 |
20140281384 | METHOD AND APPARATUS FOR PREDICTING FORWARDING OF DATA FROM A STORE TO A LOAD - A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to a prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table. The method further comprises determining if the matching entry provides a valid prediction and, if valid, retrieving a location for the prior aliasing store instruction using the distance field. It finally comprises performing a gating operation on said load operation. | 09-18-2014 |
20140297993 | UNCORE MICROCODE ROM - A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions. | 10-02-2014 |
20140304491 | PROCESSOR SYSTEM AND ACCELERATOR - It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written. | 10-09-2014 |
20140325184 | MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT - A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data. | 10-30-2014 |
20140325185 | Method for Operating a Processor - A method for operating a processor in which a first program comprising a first sequence of commands is provided, at least one second program is provided comprising a second sequence of commands, where the first program comprises a time-critical section with time-critical commands, commands from the first and second programs are processed in a processor pipeline, a start time is identified for the time-critical section in the first program, and a predefined interrupt program is incorporated into the at least one second program once the start time of the time critical section in the first program has been identified. | 10-30-2014 |
20140359256 | COUPLED DYNAMICAL SYSTEMS FOR CHAOS COMPUTING - The present invention provides systems and methods for coupled dynamical systems for chaos computing. For example, a system for the coupled dynamical system comprises a first, second, and third circuit. The first circuit comprising a plurality of single dynamical systems forms a coupled dynamical system that reduces local noises in the plurality of single dynamical systems by diffusing the local noises across the coupled dynamical system. The second circuit, connected to the first circuit, receives the data and control inputs and builds an encoding map that translates the data and control inputs to an initial condition on an unstable manifold of the plurality of single dynamical systems in the coupled dynamical system. After the coupled dynamical system evolves, a third circuit, connected to the first circuit, samples a state of one of the plurality of single dynamical systems in the coupled dynamical system and builds a decoding map. | 12-04-2014 |
20150032993 | SYSTEMS AND METHODS FOR ACHIEVING ORTHOGONAL CONTROL OF NON-ORTHOGONAL QUBIT PARAMETERS - Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together. | 01-29-2015 |
20150032994 | SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR BY REDUCING ERRORS - Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction. | 01-29-2015 |
20150046681 | SYSTEMS AND DEVICES FOR QUANTUM PROCESSOR ARCHITECTURES - Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices. | 02-12-2015 |
20150067301 | MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA - A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions. | 03-05-2015 |
20150095614 | APPARATUS AND METHOD FOR EFFICIENT MIGRATION OF ARCHITECTURAL STATE BETWEEN PROCESSOR CORES - An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being executed thereon; a second processing core having a second instruction execution pipeline including a second register set for storing a second architectural state of a second thread being executed thereon; and architectural state migration logic to perform a direct, simultaneous swap of the first architectural state from the first register set with the second architectural state from the second register set responsive to detecting that the execution of the first thread is to be migrated from the first core to the second core. | 04-02-2015 |
20150113247 | Processing Sytem with a Secure Set of Executable Instructions and/or Addressing Scheme - A method for securing a data processing system having a processing unit is disclosed. At least a group of N1 digital words of m1 bits is selected from among the set of M1 digital words. N1 is less than M1. These words are selected in such a way that each selected digital word differs from all the other selected digital words by a number of bits at least equal to an integer p which is at least equal to 2. The group of N1 digital words of m1 bits form at least one group of N1 executable digital instructions. The processing unit is configured to make it capable of executing each instruction of the at least one group of N1 executable digital instructions. | 04-23-2015 |
20150363707 | FREQUENCY SEPARATION BETWEEN QUBIT AND CHIP MODE TO REDUCE PURCELL LOSS - A system, method, and chip to control Purcell loss are described. The chip includes qubits formed on a first surface of a substrate. The method includes determining frequencies of the qubits, and controlling a separation between the frequencies of the qubits and chip mode frequencies of the chip. | 12-17-2015 |
20150363708 | SYSTEMS AND METHODS EMPLOYING NEW EVOLUTION SCHEDULES IN AN ANALOG COMPUTER WITH APPLICATIONS TO DETERMINING ISOMORPHIC GRAPHS AND POST-PROCESSING SOLUTIONS - A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian. | 12-17-2015 |
20160012347 | SYSTEMS AND DEVICES FOR QUANTUM PROCESSOR ARCHITECTURES | 01-14-2016 |
20160070572 | CONDITION CODE GENERATION - A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline. | 03-10-2016 |
20160110311 | Method For Projecting Out Irreducible Representations From a Quantum State of n Particles with d Colors - We describe a method for using a classical computer to generate a particular sequence of elementary operations (SEO), an instruction set for a quantum computer. Such a SEO will induce a quantum computer to perform a unitary transformation U that we call an Irreps Gen U. This U simultaneously diagonalizes a set of operators H | 04-21-2016 |
20160132785 | SYSTEMS AND METHODS FOR OPERATING A QUANTUM PROCESSOR TO DETERMINE ENERGY EIGENVALUES OF A HAMILTONIAN - Systems and methods for employing macroscopic resonant tunneling operations in quantum processors are described. New modes of use for quantum processor architectures employ probe qubits to determine energy eigenvalues of a problem Hamiltonian through macroscopic resonant tunneling operations. A dedicated probe qubit design that may be added to quantum processor architectures is also described. The dedicated probe qubit enables improved performance of macroscopic resonant tunneling operations and, consequently, improved performance of the new modes of use described. | 05-12-2016 |
20160188534 | COMPUTING SYSTEM WITH PARALLEL MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an identification block configured to determine a structural profile for representing a parallel structure of architectural components; and an arrangement block, coupled to the identification block, configured to generate memory sets based on the structural profile for representing the parallel structure. | 06-30-2016 |
712043000 | Mode switching | 21 |
20080209170 | Method and Device for Performing Switchover Operations and for Signal Comparison in a Computer System Having at Least Two Processing Units - A method for switchover and for signal comparison is used in a computer system having at least two processing units, a switchover device being provided, and a switch taking place between at least two operating modes, and a comparison device being provided; and a first operating mode corresponds to a compare mode, and a second operating mode corresponds to a performance mode, wherein at least two analog signals of the processing units are compared in that at least one analog signal is converted into at least one digital value. | 08-28-2008 |
20080263324 | DYNAMIC CORE SWITCHING - A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode. | 10-23-2008 |
20090077349 | METHOD OF MANAGING INSTRUCTION CACHE AND PROCESSOR USING THE METHOD - A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during the inactive mode, wherein the first instruction is performed by the processor core during the active mode. | 03-19-2009 |
20090083520 | DATA PROCESSING DEVICE - Provided is a data processing device that can prevent data used by a program from being used by another program in an unauthorized manner, regardless of the quality of the programs. The data processing device includes: a CPU | 03-26-2009 |
20090100250 | SWITCHING BETWEEN MULTIPLE SOFTWARE ENTITIES USING DIFFERENT OPERATING MODES OF A PROCESSOR - The computer program includes a virtualization software that is executable on the new processor in the legacy mode. The new processor includes a legacy instruction set for a legacy operating mode and a new instruction set for a new operation mode. The switching includes switching from the new instruction set to the legacy instruction set and switching paging tables. Each of the new operating mode and the legacy operating mode has separate paging tables. The switch routine is incorporated in a switch page that is locked in physical memory. The switch page has a first section to store a part of switching instructions conforming to the new instruction set and a second section to store another part of the switching instructions conforming to the legacy instruction set. | 04-16-2009 |
20090327656 | EFFICIENCY-BASED DETERMINATION OF OPERATIONAL CHARACTERISTICS - Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed. | 12-31-2009 |
20100031005 | Instruction Encoding For System Register Bit Set And Clear - An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification. | 02-04-2010 |
20100082943 | DYNAMIC RECONFIGURATION SUPPORT APPARATUS, DYNAMIC RECONFIGURATION SUPPORT METHOD, AND COMPUTER PRODUCT - An apparatus controls a circuit having rewritable processor elements and includes an acquiring unit that acquires information concerning a first task under execution by the circuit; a reading unit that, when the information concerning the first task is acquired, reads from a memory, a completion time of the first task; a first calculating unit that calculates a deadline time using the read completion time; an identifying unit that refers to scheduling information in the memory and identifies for a second task, the quantity of processor elements to be rewritten by the deadline time; a second calculating unit that divides the identified quantity of the processor elements by the deadline time to calculate the quantity of processor elements to be rewritten per unit time; and an executing unit that causes the circuit to rewrite the processor elements for the second task, in the quantity per unit time calculated. | 04-01-2010 |
20100169609 | Method for optimizing voltage-frequency setup in multi-core processor systems - A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode. | 07-01-2010 |
20100332799 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - According to an aspect of the present invention, there is provided an information processing apparatus including: a first processor; a second processor that has an information processing capability and a power consumption higher than those of the first processor; a temperature monitoring module configured to acquire an operating temperature of the second processor; and a processor switching control module configured to perform, when the operating temperature of the second processor is equal to or higher than a given temperature: stopping an operation of the second processor; causing the first processor to perform an information process; and prohibiting the operation of the second processor. | 12-30-2010 |
20120042151 | PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES - A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock. | 02-16-2012 |
20120166764 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire. | 06-28-2012 |
20120179894 | Data Processing Circuit With A Plurality Of Instruction Modes, Method Of Operating Such A Data Circuit And Scheduling Method For Such A Data Circuit - A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command. | 07-12-2012 |
20140164736 | LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR - Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode. | 06-12-2014 |
20140281385 | CONFIGURABLE MULTICORE NETWORK PROCESSOR - A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus, configurable to interconnect the processing cores to operate in either the pipeline processing mode or the parallel processing mode. | 09-18-2014 |
20150301828 | PROCESSOR CORE ARRANGEMENT, COMPUTING SYSTEM AND METHODS FOR DESIGNING AND OPERATING A PROCESSOR CORE ARRANGEMENT - The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa. | 10-22-2015 |
20150370568 | INTEGRATED CIRCUIT PROCESSOR AND METHOD OF OPERATING A INTEGRATED CIRCUIT PROCESSOR - A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed. | 12-24-2015 |
20160011869 | RUNNING A 32-BIT OPERATING SYSTEM ON A 64-BIT PROCESSOR | 01-14-2016 |
20160026436 | Dynamic Multi-processing In Multi-core Processors - Aspects include computing devices, systems, and methods for implementing a pipeline multi-processing (PMP) mode on a computing device using a common FIFO unit. The computing device may use configuration information for the PMP mode to allocate FIFO components of the common FIFO unit to input write data from and output read data to specific processor cores. At least first and second processor cores may be allocated a FIFO component. The first processor core may request to input write data to the FIFO component and the second processor core may request to output the read data from the FIFO component. The allocation of the FIFO components may be static and/or dynamic. FIFO access request may be denied when the common FIFO unit is already executing a similar FIFO access request, or when the FIFO components are either full and cannot input write data or empty an cannot output read data. | 01-28-2016 |
20160140081 | Method, Apparatus, And System For Optimizing Frequency And Performance In A Multidie Microprocessor - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 05-19-2016 |
20160147536 | Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes - Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode. | 05-26-2016 |