Class / Patent application number | Description | Number of patent applications / Date published |
712034000 | Including coprocessor | 36 |
20080294876 | Control Device with Flag Registers for Synchronization of Communications Between Cores - A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C | 11-27-2008 |
20080313429 | INFORMATION PROCESSING APPARATUS - When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction “GETACX Dm,Dn” performs saving of necessary data from all registers. “Dm” is a value output from a general register group | 12-18-2008 |
20080313430 | METHOD AND SYSTEM FOR INCREASING QUANTUM COMPUTER PROCESSING SPEED USING DIGITAL CO-PROCESSOR - A computer system includes a quantum computer, a classical co-processor and an interface that transmits at least part of at least one problem between the quantum computer and the classical co-processor. A digital computer may be coupled to the quantum computer and classical co-processor. Problems may be decomposed for solution by the quantum computer and co-processor based on computational efficiency. | 12-18-2008 |
20080320280 | MICROPROGRAMMED PROCESSOR HAVING MUTIPLE PROCESSOR CORES USING TIME-SHARED ACCESS TO A MICROPROGRAM CONTROL STORE - There is provided a novel microprogrammed processor ( | 12-25-2008 |
20090024834 | MULTIPROCESSOR APPARATUS - Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor through a tightly coupled bus by the processors. | 01-22-2009 |
20090070553 | DISPATCH MECHANISM FOR DISPATCHING INSTURCTIONS FROM A HOST PROCESSOR TO A CO-PROCESSOR - A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor. | 03-12-2009 |
20090077346 | PROCESSING MODULE, PROCESSOR CIRCUIT, INSTRUCTION SET FOR PROCESSING DATA, AND METHOD FOR SYNCHRONIZING THE PROCESSING OF CODES - A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The processing module includes a first processing circuit configured to process the instructions relating to the control data, and a second processing circuit configured to process the instructions relating to the user data. | 03-19-2009 |
20090077347 | Systems and methods for wake on event in a network - Embodiments include systems and methods for allowing a host CPU to sleep while service presence packets and responses to search requests are sent by an alternate processor. While the CPU is in a low power state, the alternate processor monitors the network for incoming request packets. Also, while the CPU is asleep, the alternate processor periodically may transmit presence packets, announcing the presence of a service available from the host system of the CPU. In one embodiment, the alternate processor is a low power processor. If a search request is received when the CPU is in a low power state, the alternate processor responds to the search request according to whether the PC provides that service. If a service request is received, then the ME wakes the CPU of the PC to provide the requested service. In the wireless case, when the CPU is asleep, portions of the wireless upper MAC are implemented by the ME. When the CPU is awake the wireless upper MAC is implemented in the CPU. Thus, embodiments enable the PC to appear available to wireless devices when the CPU is asleep. | 03-19-2009 |
20090113174 | Sign Operation Instructions and Circuitry - A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to | 04-30-2009 |
20090193230 | COMPUTER SYSTEM INCLUDING A MAIN PROCESSOR AND A BOUND SECURITY COPROCESSOR - A computer system includes a main processor and a security control processor that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the main processor in a slave mode during initialization of the security control processor such that the main processor is not operable to fetch and execute instructions from an instruction source external to the main processor, for example. In addition, the security control processor may be configured to initialize the operational state of the main processor to a predetermined state by transferring to the main processor via a control interface one or more instructions and to cause the main processor to execute the one or more instructions while the main processor is held in the slave mode. | 07-30-2009 |
20090210657 | Multi-Microprocessor System and Control Method for the Same - A multi-microprocessor system and a control method for the same are provided. The multi-microprocessor system includes a first microprocessor and a second microprocessor. The second microprocessor is coupled to the first microprocessor. The second microprocessor transmits a detecting signal to the first microprocessor and determines a state of the first microprocessor by monitoring the first microprocessor for a predetermined time period. In the event that the first microprocessor crashes, the first microprocessor is immediately rest or restarted by the second microprocessor in order to maximize stability of the multi-microprocessor system. | 08-20-2009 |
20090216998 | Apparatus for and Method of Processor to Processor Communication for Coprocessor Functionality Activation - A novel and useful mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication. | 08-27-2009 |
20100088490 | METHODS AND SYSTEMS FOR MANAGING COMPUTATIONS ON A HYBRID COMPUTING PLATFORM INCLUDING A PARALLEL ACCELERATOR - In accordance with exemplary implementations, application computation operations and communications between operations on a host processing platform may be adapted to conform to the memory capacity of a parallel accelerator. Computation operations may be split and scheduled such that the computation operations fit within the memory capacity of the accelerator. Further, the operations may be automatically adapted without any modification to the code of an application. In addition, data transfers between a host processing platform and the parallel accelerator may be minimized in accordance with exemplary aspects of the present principles to improve processing performance. | 04-08-2010 |
20100115237 | CO-PROCESSOR INFRASTRUCTURE SUPPORTING DYNAMICALLY-MODIFIABLE PERSONALITIES - A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities. | 05-06-2010 |
20100122064 | METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS - A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory. In a method for operating a reconfigurable unit having runtime-limited configurations, the configurations may be able to increase their maximum allowed runtime, e.g., by triggering a parallel counter. An increase in configuration runtime by the configurations may be suppressed in response to an interrupt. | 05-13-2010 |
20100153686 | Coprocessor Unit with Shared Instruction Stream - A processor unit and a coprocessor unit are disclosed. In one embodiment, the processor unit includes a functional unit that receives a set of instructions in an instruction stream and provides the set of instructions to the coprocessor unit. The coprocessor executes the instructions and initiates transmission of a set of execution results corresponding to the set of instructions to the processor unit's functional unit. The processor functional unit may be coupled to the coprocessor unit through a shared bus circuit implementing a packet-based protocol. The processor unit and the coprocessor unit may share a coherent view of system memory. In various embodiments, the functional unit may alter entries in a translation lookaside buffer (TLB) located in the coprocessor unit, resume and suspend a thread executing on the coprocessor unit, etc. | 06-17-2010 |
20100185832 | Data Moving Processor - A system and method for processing data is disclosed. In one embodiment, a data moving processor comprises a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode. | 07-22-2010 |
20100217956 | COMPANION CHIP FOR A MICROCONTROLLER - A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation. | 08-26-2010 |
20110029757 | STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF - A stream processor includes a programmable main processor MP, and a coprocessor CP that executes an extension instruction, the extension instruction being different from a basic instruction executed by the main processor MP. The main processor MP includes a coprocessor controller CPC outputting the extension instruction to the coprocessor CP, and the coprocessor CP includes a task controller TC, the task controller controlling a task performed based on the extension instruction and outputting status information ST of the task on every clock. The coprocessor controller CPC controls the coprocessor CP based on the status information ST and a basic instruction executed by the main processor MP in background in advance. | 02-03-2011 |
20120144158 | SYSTEMS AND METHODS FOR COMPILING AN APPLICATION FOR A PARALLEL-PROCESSING COMPUTER SYSTEM - A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications. | 06-07-2012 |
20120254587 | ACCELERATOR ENGINE COMMANDS SUBMISSION OVER AN INTERCONNECT LINK - An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command. | 10-04-2012 |
20130013892 | HIERARCHICAL MULTI-CORE PROCESSOR, MULTI-CORE PROCESSOR SYSTEM, AND COMPUTER PRODUCT - A hierarchical multi-core processor includes a core group for each hierarchy of a hierarchy group constituting a series of communication functions divided according to communication protocol, where a first core group of a given hierarchy among the hierarchy group is connected to a second core group of another hierarchy constituting a first communication function to be executed following a second communication function of the given hierarchy. | 01-10-2013 |
20130138921 | DE-COUPLED CO-PROCESSOR INTERFACE - A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP. | 05-30-2013 |
20130238878 | LOW POWER, HIGH PERFORMANCE, HETEROGENEOUS, SCALABLE PROCESSOR ARCHITECTURE - One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations. | 09-12-2013 |
20140244975 | MULTI-CORE PROCESSOR, CONTROLLING METHOD THEREOF AND COMPUTER SYSTEM WITH SUCH PROCESSOR - A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M. | 08-28-2014 |
20150046680 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core. | 02-12-2015 |
20160048396 | CENTRAL PROCESSOR-COPROCESSOR SYNCHRONIZATION - An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register. | 02-18-2016 |
20160092397 | ANALOG CO-PROCESSOR - An analog co-processor for a mixed signal processing system. The analog co-processor includes a plurality of components that cannot be manufactured in a sub-micron fabrication process. Each of the plurality of components is configured to perform analog or mixed signal processing. The plurality of components may be arranged on a single substrate. | 03-31-2016 |
712035000 | Digital Signal processor | 8 |
20080235494 | MUSICAL INSTRUMENT DIGITAL INTERFACE HARDWARE INSTRUCTION SET - Generating a digital waveform for a Musical Instrument Digital Interface (MIDI) voice using a set of machine-code instructions that is specialized for the generation of digital waveforms for MIDI voices. For example, a processor may execute a software program that generates a digital waveform for a MIDI voice. The instructions of the software program may be machine code instructions from an instruction set that is specialized for the generation of digital waveforms for MIDI voices. | 09-25-2008 |
20080282064 | System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment - A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor. | 11-13-2008 |
20090006810 | MECHANISM TO SUPPORT GENERIC COLLECTIVE COMMUNICATION ACROSS A VARIETY OF PROGRAMMING MODELS - A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor. | 01-01-2009 |
20090077348 | Providing a dedicated communication path for compliant sequencers - In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed. | 03-19-2009 |
20090172354 | HANDSHAKING DUAL-PROCESSOR ARCHITECTURE OF DIGITAL CAMERA - A handshaking dual-processor architecture of a digital camera includes a microprocessor and a digital signal processor (DSP). After accepting a user command, the microprocessor transmits a wakeup signal to trigger the DSP to switch from a sleep mode to an operation mode, and transmits a data packet and a processing request to the DSP. After receiving the data packet, the DSP generates a data packet processing result according to the processing request. After receiving the data packet processing result, the microprocessor returns a processing state in response to the user command. Through the handshaking dual-processor architecture, it is unnecessary to implement low-level device operation on application program, and it is only necessary to submit a required basic function, such that the microprocessor controls the corresponding DSP to execute the basic function and report the executing result of the basic function. | 07-02-2009 |
20100332797 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND PROGRAM - An information processing apparatus includes a first processing unit, a second processing unit which is different from the first processing unit, a supply unit configured to supply a clock to the first processing unit and the second processing unit, and a control unit configured to control the supply unit in such a manner as to stop a supply of the clock to the second processing unit in response to completion of activation of the second processing unit, and to resume the supply of the clock to the second processing unit in response to completion of activation of the first processing unit. | 12-30-2010 |
20110246749 | DYNAMIC ENERGY SAVINGS FOR A DIGITAL SIGNAL PROCESSOR MODULE - In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state. | 10-06-2011 |
20160124899 | MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATION - One or more processing functions may be off-loaded from a general-purpose processing device to auxiliary processing devices. The auxiliary processing devices may include a programmable element and a fixed-function element that may be pre-configured to perform the one or more processing functions. The programmable element and the fixed-function element may be dies of a multi-chip module (MOM) in a common package that can contain the general-purpose processing device, or the general-purpose processing device may reside outside of the MOM. | 05-05-2016 |