Class / Patent application number | Description | Number of patent applications / Date published |
711217000 | Generating a particular pattern/sequence of addresses | 27 |
20080229057 | ADAPTIVE PROFILING BY PROGRESSIVE REFINEMENT - A system/method for profiling a sequence of values from a range to determine a frequency of occurrence of a subrange includes, for a current block, determining whether cells of the current block include a count cell or a pointer cell. If the cell includes a pointer cell, follow an address that the pointer makes reference to and designate a new block as the current block and repeat the determining step for the new block. If the cell includes a count cell, increment the count cell and compare the incremented count cell to a threshold. If the count exceeds the threshold, convert the count cell to a pointer cell, which points to a newly allocated block. The newly allocated block is made the current block, and the steps are repeated until count cells do not exceed the threshold or a limit resolution is achieved. | 09-18-2008 |
20080235489 | Systems for forcing an update block to remain sequential - A non-volatile memory system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to provide a sequential update block, preexisting data associated with the sequential update block, and an option to convert the sequential update block to a chaotic update block. The processor is further configured to receive a write command to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from the logical addresses of the preexisting data, data are written to the sequential update block. However, if the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block. | 09-25-2008 |
20080270744 | BUFFER MEMORY SHARING APPARATUS - The present invention allows a buffer memory to be shared for data streams, while maintaining space efficiency of the buffer memory. A buffer memory sharing apparatus allowing the buffer memory to be shared includes: a flag managing circuit which manages flags each indicating an occupancy status of a region; and, for the each data stream, an address generating circuit. The address generating circuit includes: an occupancy managing circuit which manages exclusive allocation of regions based on the flags; a FIFO memory which stores a bit sequence indicating an allocated region; a write counter; and a read counter. The address generating circuit generates a write address by combining a bit sequence stored at an end of the FIFO memory and a value of the write counter, and generates a read address by combining a bit sequence stored at a start of the FIFO memory and a value of the read counter. | 10-30-2008 |
20090006807 | METHOD FOR MEMORY ADDRESS ARRANGEMENT - A method for memory address arrangement is provided. Data of different Y coordinates is moved to operation units divided by different X coordinates, or data of different X coordinates is moved to operation units divided by different Y coordinates, so as to realize the function of simultaneously longitudinally and laterally reading and writing a plurality of batches of data, thereby preventing the limitation of only longitudinally or laterally reading and writing a plurality of batches of data. | 01-01-2009 |
20090024828 | METHOD AND SYSTEM OF DIGITAL SIGNAL PROCESSING - A system comprises a system interface to receive one or more instruction sets from a microcontroller and to receive digital data to be processed. The system further comprises a controller that is reconfigurable according to the one or more instruction sets received by the system interface. The system further comprises a data path device to perform digital filtering operations on the digital data as directed by the controller according to the reconfiguration of the controller by the one or more instruction sets. | 01-22-2009 |
20090119478 | Memory Controller and Method for Multi-Path Address Translation in Non-Uniform Memory Configurations - In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected. | 05-07-2009 |
20100031001 | SERIAL MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM - In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller. | 02-04-2010 |
20100037033 | Exploit nonspecific host intrusion prevention/detection methods and systems and smart filters therefor - Exploit nonspecific host intrusion prevention/detection methods, systems and smart filters are described. Portion of network traffic is captured and searched for a network traffic pattern, comprising: searching for a branch instruction transferring control to a first address in the memory; provided the first instruction is found, searching for a subroutine call instruction within a first predetermined interval in the memory starting from the first address and pointing to a second address in the memory; provided the second instruction is found, searching for a third instruction at a third address in the memory, located at a second predetermined interval from the second address; provided the third instruction is a fetch instruction, indicating the presence of the exploit; provided the third instruction is a branch instruction, transferring control to a fourth address in the memory, and provided a fetch instruction is located at the fourth address, indicating the presence of the exploit. | 02-11-2010 |
20100058028 | ELECTRONIC DEVICE AND ADDRESS SPACE EXPANSION METHOD - An address space expansion method implemented by the electronic device which includes a storage unit, wherein the storage unit includes a first storage unit and a second storage unit, comprising: responding to the user operation to generate a target address; determining whether a address range of the target address is less than or equal to a predetermined address range, and generating a corresponding control signal; enabling the first storage unit or the second storage unit according to the generated corresponding control signal; acquiring a physical address corresponding to the target address and providing the physical address to the enabled storage unit according to the corresponding control signal and a predetermined converting rule; accessing and performing a reading/writing operation for data corresponding to the physical address of the enabled storage unit. | 03-04-2010 |
20100070737 | ADDRESS GENERATION - Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from −K to −1 for K a block size, and the second range is from 0 to K-1. | 03-18-2010 |
20100088487 | MEMORY MODULE AND AUXILIARY MODULE FOR MEMORY - In a memory module | 04-08-2010 |
20100191932 | ADDRESS GENERATION APPARATUS AND METHOD OF DATA INTERLEAVER/DEINTERLEAVER - Provided are an address generation apparatus and method of an interleaver/deinterleaver. By calculating coefficients of an address generator polynomial of an interleaver by determining exponents according to the number of prime factors forming a length of input data of the interleaver and generating an address of the deinterleaver using the calculated coefficients, errors generated when the address of the deinterleaver is generated can be removed, and right interleaver and deinterleaver addresses can be calculated. | 07-29-2010 |
20110035566 | HASHING AND SERIAL DECODING TECHNIQUES - A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software. | 02-10-2011 |
20110078409 | METHOD AND SYSTEM FOR LOCAL MEMORY ADDRESSING IN SINGLE INSTRUCTION, MULTIPLE DATA COMPUTER SYSTEM - A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE. | 03-31-2011 |
20110208945 | GENERATING RANDOM ADDRESSES FOR VERIFICATION OF DISTRIBUTED COMPUTERIZED DEVICES - Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities. | 08-25-2011 |
20110314251 | MEMORY SAFETY OF FLOATING-POINT COMPUTATIONS - Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any floating-point computations exist in the code, and if so, if the floating-point computations are memory safe. The analysis can include identifying floating-point instructions and conditional statements in the code. The code can be symbolically executed, and behavior of the floating-point instructions and the conditional statements can be monitored to determine if a floating point calculation is ever involved in computation of any memory address during the execution of the code. | 12-22-2011 |
20120005455 | DEVICE FOR STORING DATA BY UTILIZING PSEUDORANDOM NUMBER SEQUENCE - A device for storing data includes a sequence generator configured to generate a first number sequence that is a pseudorandom number sequence, a cross-correlation unit configured to produce a second number sequence that is a cross-correlation between the first number sequence and a third number sequence, and a write and read unit configured to write the second number sequence in memory and read the second number sequence from the memory, wherein the cross-correlation unit is further configured to reconstruct the third number sequence by obtaining a cross-correlation between the first number sequence and the second number sequence read from the memory. | 01-05-2012 |
20120030447 | PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESSES OF MAKING - A wireless communications device ( | 02-02-2012 |
20120191944 | PREDICTING A PATTERN IN ADDRESSES FOR A MEMORY-ACCESSING INSTRUCTION WHEN PROCESSING VECTOR INSTRUCTIONS - The described embodiments provide a processor that executes a vector instruction. In the described embodiments, while executing instructions, the processor encounters a vector memory-accessing instruction that performs a memory operation for a set of elements in the memory-accessing instruction. In these embodiments, if an optional predicate vector is received, for each element in the memory-accessing instruction for which a corresponding element of the predicate vector is active, otherwise, for each element in the memory-accessing instruction, upon determining that addresses in the elements are likely to be arranged in a predetermined pattern, the processor predicts that the addresses in the elements are arranged in the predetermined pattern. The processor then performs a fast version of the memory operation corresponding to the predetermined pattern. | 07-26-2012 |
20130103924 | EXPLOIT NONSPECIFIC HOST INTRUSION PREVENTION/DETECTION METHODS AND SYSTEMS AND SMART FILTERS THEREFOR - Exploit nonspecific host intrusion prevention/detection methods, systems and smart filters are described. Portion of network traffic is captured and searched for a network traffic pattern, comprising: searching for a branch instruction transferring control to a first address in the memory; provided the first instruction is found, searching for a subroutine call instruction within a first predetermined interval in the memory starting from the first address and pointing to a second address in the memory; provided the second instruction is found, searching for a third instruction at a third address in the memory, located at a second predetermined interval from the second address; provided the third instruction is a fetch instruction, indicating the presence of the exploit; | 04-25-2013 |
20130138916 | STORAGE APPARATUS AND ITS CONTROL METHOD - A controller for the storage apparatus: creates a second logical volume in a storage area provided by one or more storage devices; stores management information of a snapshot of a first logical volume, which is to be provided to a host computer, in the second logical volume; and reads the management information of a necessary snapshot from the second logical volume to a memory when needed, executes processing using the read management information, and returns the management information, which becomes no longer necessary, from the memory to the second logical volume. When reading the management information of the necessary snapshot from the second logical volume to the memory when needed, the controller changes the number of generations and address range of the snapshot of the management information to be read to the memory according to a generation and address of the snapshot whose management information is required. | 05-30-2013 |
20130339660 | METHOD AND APPARATUS FOR A PARTIAL-ADDRESS SELECT-SIGNAL GENERATOR WITH ADDRESS SHIFT - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift. For example, in one embodiment, such means may include receiving a plurality of address lines; splitting the plurality of address lines into a first sub-set of the plurality of address lines and a remaining sub-set of the plurality of address lines; passing the first subset of the plurality of address lines to an upper processing path; passing the remaining sub-set of the plurality of address lines to a lower processing path in parallel with the upper processing path; generating intermediate code on the upper processing path from the first sub-set of the plurality of address lines and from an intermediate carry result from the remaining sub-set of the plurality of address lines on the lower processing path; passing a hot signal type to a decoding unit on the upper processing path, wherein the hot signal type designates a decode scheme; generating specific hot-signal select line code based on the intermediate code and the hot signal type; and adopting decode scheme of the hot-signal select lines according to information from the lower processing path. Structure for performing the same are further disclosed. | 12-19-2013 |
20140101409 | 3D MEMORY BASED ADDRESS GENERATOR - Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit. | 04-10-2014 |
20150293844 | BROADCAST AND UNICAST COMMUNICATION BETWEEN NON-COHERENT PROCESSORS USING COHERENT ADDRESS OPERATIONS - Non-address data is received for transmission on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium. | 10-15-2015 |
711218000 | Sequential addresses generation | 3 |
20080307192 | Method And System For Storage Address Re-Mapping For A Memory Device - A method and system for storage address re-mapping is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of data dispersed in logical address space are mapped in a contiguous manner into blocks in storage address space. Valid data is flushed from blocks having both valid and obsolete data to make new blocks available for receiving data when an available number of new blocks falls below a desired threshold. The system includes a host file system, processor executable instructions residing on a host separately from the host file system or residing on a flash memory device such as an embedded solid state disk, or a backend memory manager of the flash memory device that is configured to map data from a logical address space to complete blocks in storage address space in a contiguous manner. | 12-11-2008 |
20100153683 | Specifying an Addressing Relationship In An Operand Data Structure - A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship. | 06-17-2010 |
20140281367 | ADDRESS CALCULATION FOR RECEIVED DATA - A method of address generation and corresponding index generator for one or more locations in a buffer with received data, determining an offset address for a specific data element in the buffer; calculating a correction factor in parallel with the determining an offset address; and providing an address for the specific data element in the buffer by combining the offset address and the correction factor, the correction factor adjusting for any impact on the offset address resulting from null elements. | 09-18-2014 |