Class / Patent application number | Description | Number of patent applications / Date published |
711214000 | Operand address generation | 9 |
20100138630 | Data-Processing Unit - A data-processing unit comprises a register unit ( | 06-03-2010 |
20110016291 | Serial Memory Interface for Extended Address Space - An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address. | 01-20-2011 |
20120216010 | CIRCUIT MODULE DEVICE WITH ADDRESS GENERATION FUNCTIONS - The present invention relates generally to a kind of circuit module device with address generation functions, which comprises: A plurality of circuit modules, wherein, each circuit module is a control unit, one signal input end and one signal output end; and thereat, the said control unit has an address generation function; and the signal input ends are being electrically connected in series with signal output ends at a plurality of said circuit modules; a plurality of said circuit modules at least consist of one primary circuit module and one secondary circuit module, in which, the signal output end of said primary circuit module is being electrically connected to the signal input end of said secondary circuit module; and wherein, when signal input end of the said primary circuit module is receiving one primary addressing command, the control unit of said primary circuit module will respond to the said primary addressing command and generate one primary address, and then it will send out one secondary addressing command to the signal input end of said secondary circuit module; in addition, when the signal input end of said secondary circuit module is receiving the said secondary addressing command, the control unit of said secondary circuit module will respond to the said secondary addressing command and generate one secondary address; and thus, it will in turn successfully generate address for each circuit module in this way. | 08-23-2012 |
20130111186 | INSTRUCTION ADDRESS ADJUSTMENT IN RESPONSE TO LOGICALLY NON-SIGNIFICANT OPERATIONS | 05-02-2013 |
20140089633 | METHOD AND APPARATUS FOR ENCODING DATA ADDRESS - The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand. | 03-27-2014 |
20140143519 | STORE OPERATION WITH CONDITIONAL PUSH - According to one embodiment, a method for a store operation with a conditional push of a tag value to a queue is provided. The method includes configuring a queue that is accessible by an application, setting a value at an address in a memory device including a memory and a controller, receiving a request for an operation using the value at the address and performing the operation. The method also includes the controller writing a result of the operation to the address, thus changing the value at the address, the controller determining if the result of the operation meets a condition and the controller pushing a tag value to the queue based on the condition being met, where the tag value in the queue indicates to the application that the condition is met. | 05-22-2014 |
20140173245 | RELATIVE ADDRESSING USAGE FOR CPU PERFORMANCE - The embodiments provide a computing device for incorporating data into code such that the data is relative to the code and, thereby, available for relative addressing. The computing device may include a code generator configured to receive source code from a source code database, and generate executable object code from the source code. The executable object code may include at least one instruction referencing data having an absolute address from a data source. Also, the computing device may include a data incorporator configured to transfer the data from the data source into the executable object code, where the transferred data is relative to the at least one instruction. Further, the computing device may include a relative addresser configured to adjust the at least one instruction to include a relative address for the transferred data including converting the absolute address to the relative address. | 06-19-2014 |
20140181464 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 06-26-2014 |
20150026431 | Method of Processing Data with an Array of Data Processors According to Application ID - A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel. | 01-22-2015 |