| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 711204000 | Predicting, look-ahead | 29 |
| 20120246440 | CO-STORAGE OF DATA STORAGE PAGE LINKAGE, SIZE, AND MAPPING - A logical page identity for a logical page containing data storage application data can be mapped to a physical storage page location in a storage where the data of the logical page are stored. The mapping as well as additional page data can be retained within a persistence layer accessible to the data storage application. The additional page data can include at least one of a size of the page and a next page linkage indicating a second page that follows the page in a page sequence of related pages. The retained mapping and additional page data can be retrieved from the persistence layer to initiate a page operation on the related pages, and the page operation can be executed on the related pages based on the retrieved mapping and additional page data. Related methods, systems, and articles of manufacture are also disclosed. | 09-27-2012 |
| 20090119476 | DATA MIGRATION - Data is extracted from at least one data source. The data is translated according to a metadata model and is stored in a staging data store. A migration management user interface is provided that includes a mechanism for indicating at least some of the data to be included in a migration event. The migration event is initiated based at least in part on the input received via the user interface. The at least some of the data is migrated from the staging data store to a target data store according to a hierarchy of controls. | 05-07-2009 |
| 20100106935 | Pretranslating Input/Output Buffers In Environments With Multiple Page Sizes - Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation page frame numbers to physical page numbers, and storing the physical page numbers in association with the pretranslation page size. Typical embodiments also include accessing the buffer, including translating a virtual memory address in the buffer to a physical memory address in dependence upon the physical page numbers and the pretranslation page size and accessing the physical memory of the buffer at the physical memory address. | 04-29-2010 |
| 20120216008 | DYNAMIC LOOK-AHEAD EXTENT MIGRATION FOR TIERED STORAGE ARCHITECTURES - A method for migrating extents between extent pools in a tiered storage architecture maintains a data access profile for an extent over a period of time. Using the data access profile, the method generates an extent profile graph that predicts data access rates for the extent into the future. The slope of the extent profile graph is calculated and used to determine whether the extent will reach a migration threshold within a specified “look-ahead” time. If so, the method calculates a migration window that allows the extent to be migrated prior to reaching the migration threshold. In certain embodiments, the method determines the overall performance impact on the source extent pool and destination extent pool during the migration window. If the overall performance impact is below a designated impact threshold, the method migrates the extent during the migration window. | 08-23-2012 |
| 20080276066 | Virtual memory translation with pre-fetch prediction - A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled to the processing device. The front end unit is configured to access the current block of data in an electronic memory device and to send the current block of data to the processor for processing. The address translation logic is coupled to the front end unit and the electronic memory device. The address translation logic is configured to pre-fetch a virtual address translation for a predicted virtual address based on a virtual address of the current block of data. Embodiments of the system increase address translation performance of computer systems including graphic rendering operations. | 11-06-2008 |
| 20080263313 | Pretranslating Input/Output Buffers In Environments With Multiple Page Sizes - Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation page frame numbers to physical page numbers, and storing the physical page numbers in association with the pretranslation page size. Typical embodiments also include accessing the buffer, including translating a virtual memory address in the buffer to a physical memory address in dependence upon the physical page numbers and the pretranslation page size and accessing the physical memory of the buffer at the physical memory address. | 10-23-2008 |
| 20100169606 | PROCESSOR AND METHOD FOR USING AN INSTRUCTION HINT TO PREVENT HARDWARE PREFETCH FROM USING CERTAIN MEMORY ACCESSES IN PREFETCH CALCULATIONS - A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon previous memory accesses. The prefetch unit may be further configured to use addresses of the memory accesses that miss to calculate each next memory block to prefetch. The detection logic may be configured to provide a notification to the prefetch unit in response to detecting a memory access instruction including a particular hint. In response to receiving the notification, the prefetch unit may be configured to inhibit using an address associated with the memory access instruction including the particular hint, when calculating subsequent memory blocks to prefetch. | 07-01-2010 |
| 20080294867 | ARITHMETIC PROCESSOR, INFORMATION PROCESING APPARATUS AND MEMORY ACCESS METHOD IN ARITHMETIC PROCESSOR - In an information processing apparatus of this invention having a cache memory, a TLB and a TSB, a second retrieval unit retrieves a second physical address from an address translation buffer by using a second virtual address corresponding one-to-one to a first virtual address, and a prefetch controller enters a first address translation pair of the first virtual address from an address translation table into a cache memory by using a second physical address which is a result of the retrieval, thereby largely shortening the processing time of a memory access when a TLB miss occurs at the time of the memory access. | 11-27-2008 |
| 20120066472 | MACROSCALAR PROCESSOR ARCHITECTURE - A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described. | 03-15-2012 |
| 20120060013 | Effective Memory Clustering to Minimize Page Fault and Optimize Memory Utilization - An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface. | 03-08-2012 |
| 20120131305 | PAGE AWARE PREFETCH MECHANISM - A processor includes a prefetch aware prefetch unit having a storage with a number of entries, and each entry corresponds to a different prefetch data stream. Each entry may be configured to store information corresponding to a page size of the prefetch data stream, along with, for example, an address corresponding to the prefetch data stream. For each entry, the prefetch unit may be configured to determine whether a prefetch of data in the data stream will cross a page boundary associated with the data stream based upon the page size information. | 05-24-2012 |
| 20120265962 | HIGH-PERFORMANCE SAS TARGET - A method for data storage includes, in a storage device that communicates with a host over a storage interface for executing a storage command in a memory of the storage device, estimating an expected data under-run between fetching data for the storage command from the memory and sending the data over the storage interface. A data size to be prefetched from the memory, in order to complete uninterrupted execution of the storage command, is calculated in the storage device based on the estimated data under-run. The storage command is executed in the memory while prefetching from the memory data of at least the calculated data size. | 10-18-2012 |
| 20100199063 | METHODS AND MECHANISMS FOR PROACTIVE MEMORY MANAGEMENT - A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed. The system includes mechanisms directed towards historical memory usage monitoring, memory usage analysis, refreshing memory with highly-valued (e.g., highly utilized) pages, I/O pre-fetching efficiency, and aggressive disk management. Based on the memory usage information, pages are prioritized with relative values, and mechanisms work to pre-fetch and/or maintain the more valuable pages in memory. Pages are pre-fetched and maintained in a prioritized standby page set that includes a number of subsets, by which more valuable pages remain in memory over less valuable pages. Valuable data that is paged out may be automatically brought back, in a resilient manner. Benefits include significantly reducing or even eliminating disk I/O due to memory page faults. | 08-05-2010 |
| 20080201552 | COMPUTER-READABLE MEDIUM STORING PROGRAM FOR CONTROLLING ARCHIVING OF ELECTRONIC DOUCUMENT, DOCUMENT MANAGEMENT SYSTEM, DOCUMENT MANAGEMENT METHOD, AND COMPUTER DATA SIGNAL - There is provided a computer-readable medium storing a program causing a computer to execute a process for controlling archiving of an electronic document, the program causing the computer to function as: a requirement memory that stores a document archive requirement for each rule; and an archive processor that judges, on the basis of the requirement memory, each document archive requirement corresponding to each rule to be applied to an electronic document to be archived, determines an archive mode which satisfies all of the judged document archive requirements, and executes a process to archive the electronic document in an archiving device in the determined archive mode. | 08-21-2008 |
| 711205000 | Directories and tables (e.g., DLAT, TLB) | 15 |
| 20090187727 | INDEX GENERATION FOR CACHE MEMORIES - Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory. | 07-23-2009 |
| 20100106936 | Calculator and TLB control method - A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance. | 04-29-2010 |
| 20120166756 | INDEX GENERATION FOR CACHE MEMORIES - Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory. | 06-28-2012 |
| 20090043985 | ADDRESS TRANSLATION DEVICE AND METHODS - A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When the data processing device is in a hypervisor mode, a second TLB is accessed in response to the request to access the page tables. If the virtual address is located in the second TLB, the hypervisor page tables are bypassed and the second TLB provides a physical address or information to access another table in the set of page tables. By bypassing the hypervisor page tables, the time to translate an address in the hypervisor mode is reduced, thereby improving the efficiency of the data processing device. | 02-12-2009 |
| 20080270738 | Virtual address hashing - Embodiments include methods, apparatus, and systems for virtual address hashing. One embodiment evenly distributes page-table entries throughout a hash table so applications do not generate a same hash index for mapping virtual addresses to physical addresses. | 10-30-2008 |
| 20090070545 | PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION USING A MULTIPLE PAGE PER ENTRY TRANSLATION LOOKASIDE BUFFER - A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry. | 03-12-2009 |
| 20100122062 | Using an IOMMU to Create Memory Archetypes - In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field. | 05-13-2010 |
| 20090198950 | Techniques for Indirect Data Prefetching - A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address. | 08-06-2009 |
| 20090204785 | Computer with two execution modes - A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page. | 08-13-2009 |
| 20100161933 | Storage device with manual learning - In a particular embodiment, a system is disclosed that includes a controller to read data from and write data to a first storage medium. The controller is adapted to monitor logical block addresses (LBAs) of each read operation from the first storage medium and to selectively store files associated with the monitored LBAs that are less than a predetermined length at a second storage medium to enhance performance of applications associated with the LBAs. | 06-24-2010 |
| 20090106523 | TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES - Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled. | 04-23-2009 |
| 20110264887 | Preload instruction control - A processor | 10-27-2011 |
| 20120131306 | Streaming Translation in Display Pipe - In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page. | 05-24-2012 |
| 20130097402 | DATA PREFETCHING METHOD FOR DISTRIBUTED HASH TABLE DHT STORAGE SYSTEM, NODE, AND SYSTEM - Embodiments of the present disclosure provide a data prefetching method, a node, and a system. The method includes: a first storage node receives a read request sent by a client, determines a to-be-prefetched data block and a second storage node where the to-be-prefetched data block resides according to a read data block and a set to-be-prefetched data block threshold, and sends a prefetching request to the second storage node, the prefetching request includes identification information of the to-be-prefetched data block, and the identification information is used to identify the to-be-prefetched data block; and the second storage node reads the to-be-prefetched data block from a disk according to the prefetching request, and stores the to-be-prefetched data block in a local buffer, so that the client reads the to-be-prefetched data block from the local buffer of the second storage node. | 04-18-2013 |
| 20130151809 | ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: an processing unit configured to execute threads and output a memory request including a virtual address; a buffer configured to register some of address translation pairs stored in a memory, each of the address translation pairs including a virtual address and a physical address; a controller configured to issue requests for obtaining the corresponding address translation pairs to the memory for individual threads when an address translation pair corresponding to the virtual address included in the memory request output from the processing unit is not registered in the buffer; table fetch units configured to obtain the corresponding address translation pairs from the memory for individual threads when the requests for obtaining the corresponding address translation pairs are issued; and a registration controller configured to register one of the obtained address translation pairs in the buffer. | 06-13-2013 |
