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Address mapping (e.g., conversion, translation)

Subclass of:

711 - Electrical computers and digital processing systems: memory

711200000 - ADDRESS FORMATION

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Class / Patent application numberDescriptionNumber of patent applications / Date published
711203000 Virtual addressing 457
711210000 Resolving conflict, coherency, or synonym problem 8
Entries
DocumentTitleDate
20120173840SAS EXPANDER CONNECTION ROUTING TECHNIQUES - Disclosed are techniques for allowing an increase in topology size of a serial attached SCSI expander network, as well as limiting entries in content addressable memory that are used to store address locations relating to the system topology. In accordance with one method, addresses are provided in the OAF request to reduce lookup table entries. In accordance with another embodiment, address ranges are provided in the lookup table. In addition, virtual memory techniques are used, so that either a software lookup process can be used, or a hardware process can be used, so that only the most recently used addresses are stored in the lookup table.07-05-2012
20100082936Cache Mapping for Solid State Drives - An approach is provided that loads software files, such as an operating system, on a hybrid storage device. The hybrid storage device is a device that includes a nonvolatile storage device and a nonvolatile memory cache. The nonvolatile memory cache has less storage capacity than the nonvolatile storage device. The nonvolatile memory cache is preset (“pinned”) to data corresponding to an initial set of address ranges of the nonvolatile storage device, such as all or part of the operating system that was loaded onto the nonvolatile storage device. A system usage metric is initialized along with a threshold value. The nonvolatile memory cache remains pinned to the initial set of address ranges until the system usage metric reaches the threshold value. When the system usage metric reaches the threshold value, then a caching algorithm is used to determine what data should be cached to the nonvolatile memory cache.04-01-2010
20090187726Alternate Address Space to Permit Virtual Machine Monitor Access to Guest Virtual Address Space - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.07-23-2009
20100042804SYSTEMS AND METHODS FOR TRANSFERRING DATA IN A BLOCK-LEVEL STORAGE OPERATION - The invention provides a system and method for storing a copy of data stored in an information store. In one embodiment, a data agent reads one or more blocks containing the data from the information store. The data agent maps the one or more blocks to provide a mapping of the blocks, and transmits the one or more blocks and mapping to a media agent for a storage device. The media agent stores the one or more blocks in the storage device according to the mapping.02-18-2010
20100042803State transistion management device and state transistion management method thereof - A state transition management device includes a memory that stores subsequent state number candidates for a current state number and a selection circuit that selects a subsequent state number from among the subsequent state number candidates that have been read out from the memory. For the state number having the subsequent state number candidates that are branch destinations of the current state number and are small in number, the memory stores the subsequent state number candidates for a plurality of current state numbers at one address in the memory that can be concurrently read out. The selection circuit selects the subsequent state number based on an event identification code (02-18-2010
20090158000Computer System, Memory Management Method and Program Thereof - A computer system, having a non-volatile storage unit (06-18-2009
20090158002NETWORK STORAGE DEVICE AND DATA READ-WRITE CONTROL METHOD - An embodiment of the present invention discloses a network storage device including a physical storage medium. The network storage device further includes: a storage controller, configured to map the physical storage medium to sub-logical units and map the sub-logical units to logical units, so as to implement data storing, reading, and writing, wherein the sub-logical units are identified by sub-logical unit numbers and the logical units are identified by logical unit numbers. In addition, an embodiment of the present invention further discloses a data read-write control method. The present invention can enlarge valid storage capacity of the logical units, and is compatible with existing logical unit data read-write manners.06-18-2009
20130061021SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR CONTROLLING SAME - Disclosed are a semiconductor memory system and a method for controlling same. The semiconductor memory system according to one embodiment of the present invention includes: a first memory for storing normal data and master metadata, the master metadata representing a relationship between a local address and a physical address for accessing the normal data; and a control logic generating compression metadata compressed in accordance with update metadata and storing the generated metadata in the first memory in response to a first control signal.03-07-2013
20130061020Computer System with Processor Local Coherency for Virtualized Input/Output - A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.03-07-2013
20130067192Data Object Profiling During Program Execution - Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.03-14-2013
20110022817Mapping Processing Logic Having Data-Parallel Threads Across Processors - A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging.01-27-2011
20090006803L2 Cache/Nest Address Translation - A method and apparatus for accessing cache memory in a processor. The method includes accessing requested data in one or more level one caches of the processor using requested effective addresses of the requested data. If the one or more level one caches of the processor do not contain requested data corresponding to the requested effective addresses, the requested effective addresses are translated to real addresses. A lookaside buffer includes a corresponding entry for each cache line in each of the one or more level one caches of the processor. The corresponding entry indicates a translation from the effective addresses to the real addresses for the cache line. The translated real addresses are used to access a level two cache.01-01-2009
20090193221METHOD AND APPARATUS FOR MEMORY MANAGEMENT IN A NON-VOLATILE MEMORY SYSTEM USING A BLOCK TABLE - An invention is provided for memory management in a non-volatile memory which includes a plurality of memory blocks. The invention includes loading a block table from a memory block of the non-volatile memory into system memory, where the block table includes, inter alia, a plurality of entries mapping a physical block address of the non-volatile memory to a logical block address of the non-volatile memory. The block table is updated as data is accessed in the non-volatile memory, and the updated block table is stored into a memory block of the non-volatile memory. Generally, the block table is stored periodically and/or at system shutdown.07-30-2009
20110283082Scalable, Concurrent Resizing Of Hash Tables - A system, method and computer program product for resizing a hash table while supporting hash table scalability and concurrency. The hash table has one or more hash buckets each containing one or more items that are chained together in a linked list. Each item in the hash table is processed to determine if the item requires relocation from a first bucket associated with a first table size to second bucket associated with a second table size. If the item requires relocation, it is linked to the second bucket without moving or copying the item in memory. The item is unlinked from the first bucket after waiting until there is no current hash table reader whose search of the hash table could be affected by the unlinking, again without moving or copying the item in memory.11-17-2011
20080282053METHOD FOR CONVERTING MEMORY ADDRESSES OF DIFFERENT PROGRAMMABLE LOGIC CONTROLLERS CONNECTED TO HUMAN-MACHINE INTERFACE - A method converts the memory addresses of different programmable logic controllers (PLC) connected to human-machine interface (HMI). The PLCs of different specifications are associated with different memory addresses. The memory address data corresponding to PLCs with various specifications is first established in HMI. A mapping condition is checked for the memory type and memory size for the PLC with different specification. A mapping relationship is established when the mapping condition is satisfied and data is automatically sent to the memory area of the new PLC.11-13-2008
20110296134ADAPTIVE ADDRESS TRANSLATION METHOD FOR HIGH BANDWIDTH AND LOW IR CONCURRENTLY AND MEMORY CONTROLLER USING THE SAME - An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.12-01-2011
20120131304Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.05-24-2012
20090150641APPARATUS, SYSTEM, AND METHOD FOR EFFICIENT MAPPING OF VIRTUAL AND PHYSICAL ADDRESSES - An apparatus, system, and method are disclosed for efficiently mapping virtual and physical addresses. A forward mapping module uses a forward map to identify physical addresses of data of a data segment from a virtual address. The data segment is identified in a storage request. The virtual addresses include discrete addresses within a virtual address space where the virtual addresses sparsely populate the virtual address space. A reverse mapping module uses a reverse map to determine a virtual address of a data segment from a physical address. The reverse map maps the data storage device into erase regions such that a portion of the reverse map spans an erase region of the data storage device erased together during a storage space recovery operation. A storage space recovery module uses the reverse map to identify valid data in an erase region prior to an operation to recover the erase region.06-11-2009
20120272036ADAPTIVE MEMORY SYSTEM - An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations.10-25-2012
20090222641ADDRESS TRANSLATION CIRCUIT - Disclosed herein is an address translation circuit including an area address holding section configured to hold at least part of a translation target address as an area address; a translation flag holding section configured to hold a translation flag specifying whether or not the translation target address is to be translated; a match detection section configured to detect a match between a predetermined part of at least one bit in an input address on the one hand, and the area address held by the area address holding section on the other hand; and a translation section configured such that if a match is detected by the match detection section and if the translation flag held by the translation flag holding section specifies that the translation target address is to be translated, then the translation section translates the input address into an address paired with the input address before outputting the paired address.09-03-2009
20080209159MEMORY ACCESS METHOD USING THREE DIMENSIONAL ADDRESS MAPPING - A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.08-28-2008
20090037688Communicating between Partitions in a Statically Partitioned Multiprocessing System - In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.02-05-2009
20100146240Method, Application System and Storage Device for Managing Application Configuration Information - The present invention provides a method, an application system and a storage device for managing the configuration information of applications, and it is applied to the storage device where an application extension area is created for every logical resource and their application extension area to physical resource mappings are maintained. The method comprises: the application system accessing the application extension area of a logical resource on the storage device when executing an application; the storage device storing the configuration information generated by the application system for the application to the appropriate physical resource based on the said mappings. The present invention ensures that the configuration information of applications can survive the failure of the application system or storage device and be restored when the application system or the storage device recovers.06-10-2010
20100146239CONTINUOUS ADDRESS SPACE IN NON-VOLATILE-MEMORIES (NVM) USING EFFICIENT EMBEDDED MANAGEMENT OF ARRAY DEFICIENCIES - The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and writing algorithms are presented.06-10-2010
20100005268MAINTAINING CORRESPONDING RELATIONSHIPS BETWEEN CHAT TRANSCRIPTS AND RELATED CHAT CONTENT - A method, apparatus, and system for maintaining corresponding relationships between at least one chat transcript and related chat content in an instant messaging system may include establishing a chat session in the instant messaging system. Corresponding chat content may be displayed synchronously according to a changed address of the chat content. The changed address of the chat content may be inserted into a chat transcript, and the chat transcript may be segmented into at least two segments to create a segmented chat transcript. The segmented chat transcript and corresponding relationship between the changed address of the chat content and corresponding chat transcript segments may be stored.01-07-2010
20080282052Operating Media Devices in Pre-Os Environment - According to one embodiment, a method for initializing a plurality of media devices in communication with a computing device; mapping information corresponding to each initialized media device to a plurality of memory locations of the computing device; and operating the initialized media devices based on the mapped information corresponding to each operated media device while the computing device is in a pre-OS environment. According to another embodiment a system comprising a plurality of media devices in communication with a computing device and adapted for initialization by the computing device; and a memory mapping logic adapted to map information corresponding to the initialized media devices to a plurality of memory locations in a system memory of the computing device, wherein the computing device is adapted to operate the initialized media devices based on the mapped information corresponding to each operated media device while the computing device is in a pre-OS environment.11-13-2008
20080301396DYNAMIC LOGICAL MAPPING - Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of the data storage library, DLM manages the physical to logical address mapping of each storage cartridge so as to optimize efficiency and speed of the data storage library.12-04-2008
20080270735Association of Host Translations that are Associated to an Access Control Level on a PCI Bridge that Supports Virtualization - A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.10-30-2008
20090164747Method,system and apparatus for memory address mapping for sub-socket partitioning - Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.06-25-2009
20090164748EFFICIENT ADDRESS GENERATION FOR PRUNED INTERLEAVERS AND DE-INTERLEAVERS - Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.06-25-2009
20120198203MODIFYING DATA STORAGE IN RESPONSE TO DETECTION OF A MEMORY SYSTEM IMBALANCE - A method begins by a processing module determining an imbalance between inode memory utilization and data storage memory utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether the inode memory utilization is out of balance with respect to the data storage memory utilization or whether the data storage memory utilization is out of balance with respect to the inode memory utilization. When the inode memory utilization is out of balance with respect to the data storage memory utilization, the method continues with the processing module transferring a set of data objects from a data object section to a data block section and transferring object mapping information of the set of data objects into block mapping information for the set of data objects.08-02-2012
20090177861SYSTEM AND METHODS FOR MEMORY EXPANSION - This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.07-09-2009
20090198947Memory Mapping Restore and Garbage Collection Operations - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.08-06-2009
20090083513Simplified Run-Time Program Translation for Emulating Complex Processor Pipelines - Simplification of run-time program translation for emulating complex processor pipelines is disclosed. Problem of dynamic pipeline states are moved into a cache lookup process leaving a code translation process to deal only with static pipeline states. With dynamic pipeline states removed from the translation process, translation becomes more simple and efficient like that of a non-pipelined processor.03-26-2009
20090049269HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR - A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.02-19-2009
20090055621Column redundancy system for a memory array - A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another.02-26-2009
20090055620DEFECT MANAGEMENT USING MUTABLE LOGICAL TO PHYSICAL ASSOCIATION - The application relates to defect management using mutable logical to physical association. Embodiments disclosed utilize mutable mapping between logical blocks and physical blocks. Dynamically updated mapping data, which mutably associates the logical blocks and the physical blocks, also includes physical block defect allocations.02-26-2009
20090204783Systems And Methods For Handling Addresses Within A Database Application - A system and method store addresses within a database. An address and an address usage type that define an intended use of the address for an entity are captured. Address elements of the address are determined using an address template based upon the address usage type. If the address is not already stored within the database, an address entry having a new unique address identification number is created within an address table, each of the address elements are stored within an address element table of the database in association with the new unique address identification number, and an association entry is created within an address association table to associate the new unique address identification number with the entity, as well as to store the address usage type. If the address is already stored within the database, an existing unique address identification number for the address within the database is determined and an association entry within the address association table is created to associate the existing unique address identification number with the entity and to store the address usage type.08-13-2009
20090249021Method And Systems For Invoking An Advice Operation Associated With A Joinpoint - Methods and systems are described for invoking an advice operation associated with a joinpoint. In one embodiment, the method includes identifying, based on a pointcut specification included in an aspect specification, a joinpoint in a machine code program component. The joinpoint includes a machine code instruction. The method further includes identifying, based on an advice specification included in the aspect specification, an advice operation included in a machine code program component. The method still further includes detecting an access to the machine code instruction in the joinpoint for execution by a processor. The method also includes invoking the advice operation in association with detecting the access to the machine code instruction.10-01-2009
20100161932METHODS FOR WRITING DATA FROM A SOURCE LOCATION TO A DESTINATION LOCATION IN A MEMORY DEVICE - Methods for writing data from a source location to a destination location in a memory device are provided. In one embodiment, a memory device receives a command from a host device, wherein the command specifies a logical address of a source location in the memory and a logical address of a destination location in the memory. The memory device translates the logical addresses of the source and destination locations to physical addresses of the memory, reads data from the source location, and writes the data to the destination location. In this embodiment, the data is read from the source location and written to the destination location without a need of further involvement of the host device after the host device sends the command to the memory device. Other embodiments are provided.06-24-2010
20130219146METHOD, DEVICE AND SYSTEM FOR A CONFIGURABLE ADDRESS SPACE FOR NON-VOLATILE MEMORY - Example embodiments described herein may relate to memory devices, and may relate more particularly to configurable address space for non-volatile memory devices.08-22-2013
20090077342METHOD TO ACHIEVE PARTIAL STRUCTURE ALIGNMENT - A computer-implemented method including receiving a set of data having a mapping. The set of data has groups of subsets of data. The mapping describes in what order the groups of subsets of data are to be stored in a memory. The mapping also describes the offsets of the groups of subsets of data in the memory. The mapping is not changed when the set of data is stored in the memory. The method also includes determining a starting address for the set of data. The starting address corresponds to an address in the memory. The starting address is determined such that an optimum number of subsets of data in the groups of subsets of data are aligned. The method also includes storing the set of data in the memory, wherein the mapping is unaffected when the set of data is stored in the memory.03-19-2009
20100115227PARALLEL PRUNED BIT-REVERSAL INTERLEAVER - A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)−1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side.05-06-2010
20100199062MANAGING REQUESTS OF OPERATING SYSTEMS EXECUTING IN VIRTUAL MACHINES - A coordinator in a computer system receives a request from one of a plurality of operating systems (that coexist in the computer system) to invoke a service of a management routine in the computer system. The plurality of operating systems execute in respective virtual machines of the computer system. The coordinator processes the received request to invoke the service of the management routine to prevent a conflict from occurring with respect to at least another one of the plurality of operating systems.08-05-2010
20090158001ACCESSING CONTROL AND STATUS REGISTER (CSR) - A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more transactions generated by the source agents is to be sent. A controller may identify one of a plurality of directory agents to process the transactions. The directory agent may determine the control and status registers of the target agents to which the transaction is to be sent. The target agent may complete the transaction after receiving the transaction from the directory agent. The directory agents may store a memory map to resolve the target agent to which the transactions is to be sent. The directory based distributed CSR access may provide scalability to ever increasing number of heterogeneous agents in the system.06-18-2009
20090113164Method, System and Program Product for Address Translation Through an Intermediate Address Space - In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.04-30-2009
20090106522ELECTRONIC SYSTEM WITH DYNAMIC SELECTION OF MULTIPLE COMPUTING DEVICE - An electronic system is provided including powering a computing integrated circuit device having a first processor device and a second processor device; generating an address transform for the first processor device and the second processor device; operating a software code having a first processor address for the first processor device and a second processor address for the second processor device with the software code provides a display or actuates a mechanic device; mapping the first processor address with the address transform to the second processor address; and reconfiguring the address transform.04-23-2009
20100306497Computer implemented masked representation of data tables - In the computer software field, method and apparatus to obfuscate (mask or hide) computer data which is part of or accessed by a computer program. The method protects (hides) accesses to tables of data in terms of the place or position of each element in the table. It does this by providing an intermediate table which describes the positions of the elements of the first table or tables, but in a transformed (modified) fashion.12-02-2010
20090070544Microcontrollers with instruction sets - A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each primary data has a first width. The secondary register includes the plurality of primary registers and stores a secondary data having a second width. The secondary data includes a combination of the plurality of primary data. The CPU executes a first instruction in a first mode in which a primary data is fetched for operation and executes a second instruction in a second mode in which the secondary data is fetched for operation.03-12-2009
20090024823OVERLAYED SEPARATE DMA MAPPING OF ADAPTERS - DMA mapping for adapters configured to communicate with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of the another group are overlayed in the DMA mapping space for control information for the respective adapters.01-22-2009
20110087855Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages.04-14-2011
20120173841Explicitly Regioned Memory Organization in a Network Element - A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.07-05-2012
20090172339Apparatus and method for controlling queue - An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which controls the queue element. The controller includes an address decision element which decides whether a first address of a first memory access request and a second address of a second memory access request relate with each other. The controller issues the second memory access request together with issuing of the first memory access request when the first address and the second address relate with each other.07-02-2009
20100131736MEMORY DEVICE AND METHOD OF OPERATION - A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data.05-27-2010
20090327644CPU AND MEMORY CONNECTION ASSEMBLY TO EXTEND MEMORY ADDRESS SPACE - Disclosed is a CPU and memory connection assembly to extend memory address space without extending address pins. The CPU and memory connection assembly extends entire accessible memory address of a CPU using a small number of address pins by synthesizing a final memory address by receiving an offset address setting command inputted from a CPU through an offset address decoder to generate an offset address and by receiving CPU max address bit setting command directly inputted from the CPU through an address synthesizer to combine the CPU max address bit setting command with the address directly inputted from the CPU.12-31-2009
20100058023EFFICIENTLY MANAGING MODULAR DATA STORAGE SYSTEMS - The management of a data storage system. The system may store data objects that are subject to change in container sets. The data storage system uses location maps to map the data objects to a corresponding container. When there has been, or will be, a change in the availability of containers, a new location map is created which maps the data objects to a new potentially overlapping set of containers. New data objects are added to the new set of containers, and a data object is found by searching all location maps. As an alternative or as an addition to this system, data objects may be stored in a manner that they may be efficiently removed when a condition is met. A container is created which stores all data objects to be removed when the condition occurs. When the condition occurs, the container is removed.03-04-2010
20110078406Unified Addressing and Instructions for Accessing Parallel Memory Spaces - One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.03-31-2011
20130159660SYSTEM AND METHOD FOR IDENTIFYING A CHARACTER-OF-INTEREST - A method of generating an output vector to identify a character-of-interest using a sparse distributed memory (SDM) module. The method includes obtaining a feature vector having a vector address. The feature vector is based on a character-of-interest in an acquired image. The method also includes identifying activated locations from hard locations by determining relative distances between the vector address and the stored vector location addresses. Stored content counters of the activated locations include first and second stored sub-sets of counters. The method also includes combining the counters of the first stored sub-sets of the activated locations using a first summation thread to provide a first combined sub-set of values. The method also includes combining the counters of the second stored sub-sets of the activated locations using a second summation thread to provide a second combined sub-set of values. The first and second summation threads are run in parallel.06-20-2013
20110016288Serial Flash Memory and Address Transmission Method Thereof - A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.01-20-2011
20120204000ADDRESS TRANSLATION FOR USE IN A PATTERN MATCHING ACCELERATOR - A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.08-09-2012
20080320268INTERCONNECT IMPLEMENTING INTERNAL CONTROLS - In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.12-25-2008
20080229052Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit - A data processing apparatus and method are provided for implementing a replacement scheme for entries of a storage unit. The data processing apparatus has processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread. A storage unit is then shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. A record is maintained identifying for each entry whether the information stored in that entry is associated with a high priority program thread or a lower priority program thread. Replacement circuitry is then responsive to a predetermined event in order to select a victim entry whose stored information is to be replaced. To achieve this, the replacement circuitry performs a candidate generation operation to identify a plurality of randomly selected candidate entries, and then references the record in order to preferentially select as the victim entry a candidate entry whose stored information is associated with a lower priority program thread. This improves the performance of the high priority program thread(s) by preferentially evicting from the storage unit entries associated with lower priority program threads.09-18-2008
20120311298MOUNT-TIME UNMAPPING OF UNUSED LOGICAL ADDRESSES IN NON-VOLATILE MEMORY SYSTEMS - Systems and methods are provided for unmapping unused logical addresses at mount-time of a file system. An electronic device, which includes a non-volatile memory (“NVM”), may implement a file system that, at mount-time of the NVM, identifies all of the logical addresses associated with the NVM that are unallocated. The file system may then pass this information on to a NVM manager, such as in one or more unmap requests. This can ensure that the NVM manager does not maintain data associated with a logical address that is no longer needed by the file system.12-06-2012
20120311297LOGICAL UNIT ADDRESS ASSIGNMENT - Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.12-06-2012
20100180097Generation and Self-Synchronizing Detection of Sequences Using Addressable Memories - Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can be decomposed into unique words are also disclosed. Methods and apparatus to implement Fibonacci and Galois LFSRs are disclosed.07-15-2010
20120210093METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING TO MODIFY SOURCE IDENTITY - A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.08-16-2012
20120124323METHOD FOR SETTING MEMORY ADDRESS SPACE - A method for setting a memory address space is provided. A memory access frequency of an application program is obtained under execution of an operating system (OS). And a mapping of a memory region is decided according to the memory access frequency. Next, an interrupt signal is used for executing an interrupt handler routine. The mapping of the memory region is set under execution the interrupt handler routine. And the application program is loaded into the memory region for executing in the OS.05-17-2012
20090132783System and Method of Determining an Address of an Element Within a Table - In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.05-21-2009
20120317394TRANSFORMING ADDRESSING ALIGNMENT DURING CODE GENERATION - The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.12-13-2012
20120272037TECHNIQUES FOR MAPPING DEVICE ADDRESSES TO PHYSICAL MEMORY ADDRESSES - A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.10-25-2012
20120179890REMAPPING OF DATA ADDRESSES FOR LARGE CAPACITY LOW-LATENCY RANDOM READ MEMORY - Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.07-12-2012
20120221827 ADDRESS DECODING DEVICE - An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.08-30-2012
20120226887LOGICAL ADDRESS TRANSLATION - The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.09-06-2012
20080301397Method and arrangements for utilizing NAND memory - A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag.12-04-2008
20120239903ADDRESS TRANSFORMING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.09-20-2012
20110047346EFFICIENT INTERLEAVING BETWEEN A NON-POWER-OF-TWO NUMBER OF ENTITIES - Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log02-24-2011
20110276777DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.11-10-2011
20120331259GEOMETRIC ARRAY DATA STRUCTURE - A method for implementing a geometric array in a computing environment is disclosed. In one embodiment, such a method includes providing an array of slots, where each slot is configured to store a pointer. Each pointer in the array points to a block of elements. Each pointer with the exception of the first pointer in the array points to a block of elements that is twice as large as the block of elements associated with the preceding pointer. Such a structure allows the geometric array to grow by simply adding a pointer to the array that points to a new block of elements that is twice as large as the block of elements associated with the preceding pointer in the array. A corresponding computer program product, as well as a method for accessing data in the geometric array, are also disclosed.12-27-2012
20110320757STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.12-29-2011
20110320756RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS - Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor.12-29-2011
20130013886ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.01-10-2013
20130013885MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND METHOD FOR IDENTIFYING VALID DATA - A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.01-10-2013
20110161618ASSIGNING EFFICIENTLY REFERENCED GLOBALLY UNIQUE IDENTIFIERS IN A MULTI-CORE ENVIRONMENT - A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.06-30-2011
20080256325Memory Device and Device for Reading Out - A device includes an input for an N-bit data word. A circuit is adapted to map the N-bit data word to a physical M-bit memory data word by means of a mapping rule. The mapping rule includes a quantity of values of possible physical M-bit memory data words the mean number of first physical bit values of which is smaller than N/2. The circuit also includes output for the physical M-bit memory data word. Memory cells are couplable to the output.10-16-2008
20130124820DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING MEMORY TRANSACTIONS WITHIN SUCH A DATA PROCESSING APPARATUS - A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing.05-16-2013
20130132702Processor with Kernel Mode Access to User Space Virtual Addresses - A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.05-23-2013
20130159661HARDWARE MONITOR - A monitor includes a register configured to store at least two contexts and a context change value. A context selector is configured to select at least one of the two contexts for context monitoring. The selection is made dependent on whether the context change value matches a first part of a memory access address.06-20-2013
20130185535APPARATUS AND METHOD FOR PROCESSING NON-SEQUENTIALLY STORED DATA - An apparatus and method for processing non-sequentially stored data is provided. The data processing apparatus may include an order information mapping unit to map transmission order information to data, an address list generating unit to generate an address list including addresses of the data arranged sequentially based on the transmission order information, and a data processing unit to process the data corresponding to each of the addresses based on an address order of the address list.07-18-2013

Patent applications in class Address mapping (e.g., conversion, translation)

Patent applications in all subclasses Address mapping (e.g., conversion, translation)