Entries |
Document | Title | Date |
20080209141 | Memory System And Device With Serialized Data Transfer - A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage. | 08-28-2008 |
20080215829 | OPTICAL DISC RECORDER AND BUFFER MANAGEMENT METHOD THEREOF - A buffer management method is provided. A host issues a read command requesting access for a read data block and a write command requesting recording of a write data block. A write buffer is dedicated to store the write data block. A read buffer is dedicated to store the read data block. The method comprises entering the optical disc recorder into a write loop. During the write loop, the optical disc recorder triggering a write command handling procedure in response to the write command; triggering a read command handling procedure in response to the read command; and triggering a pre-recording procedure to prepare the write data block in the write buffer for recording. Wherein contents between the write buffer and read buffer are exchangeable during the write handling procedure, the read handling procedure or the pre-recording procedure. | 09-04-2008 |
20080270712 | METHOD OF OVERWRITING DATA IN WRITE-ONCE INFORMATION STORAGE MEDIUM AND DATA RECORDING AND/OR REPRODUCING APPARATUS FOR WRITE-ONCE INFORMATION STORAGE MEDIUM - A method of overwriting data in a write-once information storage medium and a data recording and/or reproducing apparatus provided for overwriting data in such a write-once information storage medium. In the data overwriting method, a command to overwrite new data in a first area of the write-once information storage medium where data has already been recorded is issued. Then, the first area is considered as a defective area, and the new data is recorded in a second area. Thereafter, updated defect management information, including information about the locations of the first and second areas, is recorded in the write-once information storage medium. Accordingly, overwriting can be performed in write-once information storage media, which is incapable of physical overwriting, by using a logical overwriting technique. Thus, data recorded in the write-once information storage medium may be changed or updated. | 10-30-2008 |
20080282044 | DATA CONTROL SYSTEM, CONTROL SERVER, DATA CONTROL METHOD, AND PROGRAM - There is provided a data control system that includes a control server and an information processing terminal equipped with a non-contact type IC chip. The information processing terminal includes a chip memory and a consistency check request portion. The chip memory includes at least one service area that stores a service data item and an index area that stores a link information item for accessing the service area. The consistency check request portion transmits a consistency check request. The control server includes a data acquisition portion that acquires the link information item according to the check request, an area determination portion that determines whether the corresponding service area exists for each link information item, a reading portion that reads the determined service area, and a data update portion that, if the service area could not be read, updates the link information item with information not indicating any access destination. | 11-13-2008 |
20080320252 | OPTIMIZED AND ROBUST IN-PLACE DATA TRANSFORMATION - In-place data transformations are performed on file data by moving data blocks from a source file into a temporary file and then from the temporary file into a destination file each time in a back to front fashion enabling truncation of the source file while the temporary file is being expanded and written into. Similar read, write, and truncate operations are performed between the temporary and destination files as well resulting in optimized use of available disk and/or memory space. An initial log file with information such as source file name, size, transformation type and direction is generated for recovery from a mid-transaction interruption. Based on a state (truncation, data content) of the temporary and source files, a status of data transfer prior to interruption is determined and remaining data transferred. | 12-25-2008 |
20080320253 | Memory device with circuitry for writing data of an atomic transaction - A memory device with circuitry for writing data of an atomic transaction is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory. | 12-25-2008 |
20090024807 | MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE - A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency. | 01-22-2009 |
20090024808 | MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE - A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency. | 01-22-2009 |
20090063792 | Memory control circuit, semiconductor integrated circuit, and verification method of nonvolatile memory - A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the memory cell, which is previously determined to be successfully storing an expectation value, to a corresponding expectation value expected to be stored in the memory cell, and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data. | 03-05-2009 |
20090089518 | SOLID STATE STORAGE RECLAMATION APPARATUS AND METHOD - A method and apparatus are disclosed for reclaiming solid state storage with limited write cycles such as flash memory. Through the use of shared storage for common data patterns, physical space may be conserved or reclaimed in a solid state device. The apparatus may use internal mappings and/or external device drivers to handle the reclamation of unused space. By enabling reclamation of physical space, the disclosed systems, apparatus, and methods may provide more efficient read and write access and improved wear leveling. | 04-02-2009 |
20090100235 | STORAGE SYSTEM AND DATA ERASING METHOD - This storage system includes a server management unit for managing in a server a maximum overwrite count and an overwrite count for overwriting the overwrite data in a disk cache, a controller cache for temporarily storing overwrite data sent from the server in the storage subsystem, a storage management unit for managing a maximum overwrite count and an overwrite count for overwriting overwrite data sent from the server in the controller cache so as to overwrite overwrite data sent from the controller cache in the hard disk drive according to the number of the maximum overwrite count, and an address management unit for managing the respective addresses of the disk cache, the controller cache and the hard disk drive storing the same file to be erased. | 04-16-2009 |
20090106512 | HISTOGRAM GENERATION WITH MIXED BINNING MEMORY - Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated. | 04-23-2009 |
20090132772 | System and method for performing data reading and writing on physical storage device - A system and a method for performing data reading and writing on a physical storage device. A plurality of controllers under a common storage environment is used to realize data read and write operation performed on the physical storage device by a remote client. Firstly, the client assigns a controller in the plurality of controllers as a controller for executing the read and write operation, and each controller performs transmission of management data and cache data of the data to be written in the physical storage device through interlink. Then, the assigned controller reads data from the physical storage device or writes data into the physical storage device through corresponding logical storage device. | 05-21-2009 |
20090150624 | SYSTEM, APPARATUS, AND METHOD FOR MODIFYING THE ORDER OF MEMORY ACCESSESES - Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations. | 06-11-2009 |
20090177850 | APPARATUS, SYSTEM, AND METHOD FOR A READ-BEFORE-WRITE STORAGE CONTROLLER INSTRUCTION - An apparatus, system, and method are disclosed for a read-before-write storage controller instruction. A sequencer receives an atomic read-before-write instruction comprising new data, a target address for the new data, and an undo log address. An I/O unit reads old data from the target address, writes the old data and the target address to the undo log address, and writes the new data to the target address as directed by the sequencer. | 07-09-2009 |
20090216966 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR STORING EXTERNAL DEVICE RESULT DATA - A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system. | 08-27-2009 |
20090240900 | MEMORY APPARATUS AND MEMORY CONTROL METHOD - A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal. | 09-24-2009 |
20090240901 | INFORMATION PROCESSING APPARATUS, STORAGE CONTROL DEVICE AND CONTROL METHOD - A computer, which includes multiple memory modules each of which is provided with an SPD for storing setting information about the memory, a setting information acquisition section of an SPD controller of a memory controller, obtains setting information from the SPD of each memory module, and the setting information is held in a setting information holding section. The storage control device of the computer compares the acquired pieces of setting information. When the contents of the pieces of setting information are different from one another, the storage control device overwrites setting information in the SPD's of the memory modules other than the memory module corresponding to the setting information by using the contents of any one of the pieces of setting information. | 09-24-2009 |
20090276587 | SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM - A circuit includes a memory having error correction, circuitry which initiates a write operation to memory. When error correction is enabled and the write operation to the memory has the width of N bits, the write operation to the memory is performed in one access to the memory, and when error correction is enabled and the write operation to the memory has the width of M bits, where M bits is less than N bits, the write operation to the memory is performed in more than one access to the memory. In one example, the one access to the memory includes a write access to the memory, and the more than one access to the memory includes a read access to the memory and a write access to the memory. | 11-05-2009 |
20090287890 | OPTIMIZING WRITE TRAFFIC TO A DISK - The write optimizer described in this disclosure optimizes write traffic to a disk. The write optimization technique writes small data sets to be written to a disk drive to a log file in write optimized order and rewrites the small data sets to disk drive in read optimized order when the disk drive is idle. The write optimizer reserves a portion of a disk to be used for write performance improvement, and then takes all small writes to the disk and writes them to the reserved area rather than to their intended destination. When the disk becomes idle (or the reserved area full), the write optimizer takes the data that has been written to the reserved area and that has not been subsequently overwritten and copies it to its final location. | 11-19-2009 |
20090287891 | LIQUID CONTAINER - In a semiconductor storage device | 11-19-2009 |
20090300297 | Data processing apparatus, memory controller, and access control method of memory controller - A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command. | 12-03-2009 |
20090319731 | DATA PROCESSING CONTROL METHOD, INFORMATION PROCESSING APPARATUS, AND DATA PROCESSING CONTROL SYSTEM - In a system which realizes to prevent leakage/loss of secret information by prohibiting a write operation to a secondary storage apparatus and a write operation to an external medium, an automatic collection of secret data to a server is executed, an existing application mode of PC is not damaged, and then an update of OS and an application is executed. The present invention places a secondary storage apparatus write control driver on the lower level than a file system, and redirects a write operation to the secondary storage apparatus, setting up a memory to be a primary cache, and cache data file on a cache server of a network destination to be a secondary cache. Thereby, the write operation to the secondary storage apparatus is not executed, and difference data is stored on the cache server, so that the automatic collection of secret data to the server can be realized. | 12-24-2009 |
20100005253 | MEMORY CONTROLLER, PCB, COMPUTER SYSTEM AND MEMORY ADJUSTING METHOD - A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range. | 01-07-2010 |
20100017571 | CONTENT WRITE-IN DEVICE - It is possible to classify a continuous content into separate series to be written into a storage medium. A reception device receives a digital broadcast program and EIT and generates program attribute information according to the information associated with the series contained in EIT. Upon reception of a write-into-DVD instruction of a recorded digital broadcast program in a program recording region inputted by a user via UI, a write control device integrates the program attribute information in the program attribute information storage region, the write-into-DVD history information in the write-into-DVD history information storage region, and the DVD information obtained from the DVD drive, so as to judge whether write into DVD is enabled. The write control device presents the judgment information to the user via UI and controls write of the recorded digital broadcast program into the DVD according to the user instruction input information acquired via the UI. | 01-21-2010 |
20100030978 | MEMORY CONTROLLER, MEMORY CONTROL METHOD, AND IMAGE PROCESSING DEVICE - A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address. | 02-04-2010 |
20100058005 | CONTROL UNIT FOR STORAGE APPARATUS AND METHOD FOR CONTROLLING STORAGE APPARATUS - Each CM retains a function management table in which entry information indicating which function is operating in which CM for what period is registered. Every time a command is executed in a function processing unit on the basis of an instruction from a GUI, components of a CM perform control, communicating registered pieces of content in a function management table to corresponding components of another CM for synchronization among the CMs. Regardless of which of a plurality of CMs in a storage apparatus is a master, processing can be executed in any CM from any GUI without inconsistency in the processing between the CMs. | 03-04-2010 |
20100077159 | IMAGE FORMING APPARATUS AND METHOD OF OVERWRITING FOR STORAGE UNIT IN IMAGE FORMING APPARATUS - An image forming apparatus and a method of overwriting for a storage unit in an image forming apparatus. The method of overwriting data in a storage unit of an image forming apparatus includes configuring a plurality of overwriting options corresponding to data stored in the storage unit; deleting the data stored in the storage unit according to a delete instruction; and overwriting data according to the configuration of the plurality of overwriting options corresponding to the data stored in the storage unit. | 03-25-2010 |
20100100694 | RECORDING/REPRODUCING APPARATUS FOR PERFORMING RMW FOR LOW, RECORDING/REPRODUCING METHOD THEREFOR, AND INFORMATION STORAGE MEDIUM THEREFOR - Replacement data for updating data recorded on an information storage medium is recorded in an area for logical overwrite (LOW) replacement; replacement data for replacing a defect generated on the medium is recorded in an area for defect replacement; and, if a defect is generated in an original block recorded in a predetermined area of the medium during a read-modify-write (RMW) process for a LOW for at least partial data of an original block, a replacement block replacing the original block is recorded in the area for LOW replacement and a defect list (DFL) entry including location information of the original block and location information of the replacement block is generated to indicate the replacement state. | 04-22-2010 |
20100122047 | SYSTEMS AND METHODS FOR ENHANCING A DATA STORE | 05-13-2010 |
20100131725 | Memory System And Device With Serialized Data Transfer - A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage. | 05-27-2010 |
20100169587 | CAUSATION OF A DATA READ AGAINST A FIRST STORAGE SYSTEM TO OPTIONALLY STORE A DATA WRITE TO PRESERVE THE VERSION TO ALLOW VIEWING AND RECOVERY - Machine readable instructions, methods, and systems of causation of a data read against a first storage system to optionally store a data write to preserve the version to allow viewing and recovery are disclosed. In an embodiment, a system for providing secondary data storage and recovery services for one or more networked host nodes includes a server application for facilitating data backup and recovery services; a first data storage medium accessible to the server application; a second data storage medium accessible to the server application; and at least one client application for mapping write locations allocated by the first data storage medium to write locations represented in a logical view of the first data storage medium. | 07-01-2010 |
20100174877 | Ring buffer circuit and control circuit for ring buffer circuit - Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory. | 07-08-2010 |
20100250874 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 09-30-2010 |
20100250875 | EEPROM EMULATION USING FLASH MEMORY - A device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased. | 09-30-2010 |
20100268901 | RECONFIGURABLE MEMORY SYSTEM DATA STROBES - In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array. | 10-21-2010 |
20100312975 | Mechanism for a Reader Page for a Ring Buffer - In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page for a reader of the ring buffer, the ring buffer stored in a physical memory device, and swapping, by the processing device, a head page of the ring buffer with the reader page so that the reader page is part of the ring buffer and the head page is no longer attached to the ring buffer. | 12-09-2010 |
20100318753 | MEMORY ARCHITECTURE OF DISPLAY DEVICE AND READING METHOD THEREOF - A memory architecture of a display device including a display data memory block and a processor is provided. The display data memory block includes N sub-memories and N arbiters respectfully coupled to the N sub-memories, wherein N is a positive integer larger than 1. The processor is used for respectfully and continuously outputting corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectfully output the corresponding address signals to corresponding sub-memories, such that the N sub-memories simultaneously access data respectfully according to the N address signals. | 12-16-2010 |
20110022809 | CONSOLIDATED ELECTRONIC CONTROL UNIT AND RELAY PROGRAM IMPLEMENTED IN THE SAME - In a consolidated electronic control unit (ECU) integrally produced by a plurality of conventional ECUs, an inventive relay program is adapted to enable a CPU of the consolidated ECU to rewrite internal and external parameters into the external and internal parameters, respectively, with reference to a correspondence list previously set between the internal parameter and the external parameter. The internal parameter is a parameter that is to be used by a specific program implemented in the consolidated ECU. The external parameter is a parameter that corresponds to the internal parameter and that is to be used by a non specific program implemented in the consolidated ECU. | 01-27-2011 |
20110035560 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 02-10-2011 |
20110072222 | METHOD FOR SECURE DATA READING AND DATA HANDLING SYSTEM - A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M | 03-24-2011 |
20110078392 | WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES - Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message. | 03-31-2011 |
20110078393 | MEMORY DEVICE AND DATA ACCESS METHOD - The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands. | 03-31-2011 |
20110099341 | SYSTEM, APPARATUS, AND METHOD FOR MODIFYING THE ORDER OF MEMORY ACCESSES - Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations. | 04-28-2011 |
20110153962 | ENDLESS MEMORY - A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the storage device itself are synchronized so as to prevent deletion of data from the storage device before it is offloaded to another storage platform. | 06-23-2011 |
20110179237 | Semiconductor device having resistance based memory array, method of reading, and systems associated therewith - One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array. | 07-21-2011 |
20110197036 | CONTROL METHOD FOR DISK ARRAY APPARATUS AND DISK ARRAY APPARATUS - According to an aspect of the embodiment, in a control method for a disk array apparatus, a CPU of a first control module acquires other system state information, which is decided based on a battery and a nonvolatile memory of the second control module and indicates a data saving possibility of a cache memory of a second control module. The CPU of the first control module determines, based on the other system state information acquired and own system state information, which is decided based on a battery and a nonvolatile memory of the first control module and indicates a data saving possibility of a cache memory of the first control module, whether the disk array apparatus is set in a write-back state or a write-through state. | 08-11-2011 |
20110208925 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 08-25-2011 |
20110225378 | Data Processing Apparatus, Data Processing Method, and Computer-Readable Recording Medium for Writing and Reading Data to and from a Storage - A data processing apparatus includes a storage controller and a processor. The storage controller is configured to write a series of data blocks constituting a particular unit of data to a storage and read out the series of data blocks from the storage. The processor is further configured to generate a write-side process and a read-side process, notify the read-side process from the write-side process of an identifier of a storage area in the storage, cause the storage controller to sequentially write the series of data blocks to the storage area using the write-side process, and cause the storage controller to read the series of data blocks from the storage area corresponding to the identifier using the read-side process after the identifier is received in the read-side process. | 09-15-2011 |
20110231621 | SYSTEM RECOVERY METHOD, AND STORAGE MEDIUM CONTROLLER AND STORAGE SYSTEM USING THE SAME - A system recovery method is provided. The system recovery method includes grouping storage addresses corresponding to a storage device into a first memory area and a second memory area. The system recovery method also includes storing initial data from a host system into the storage addresses of the first memory area, storing update data for updating the initial data into the storage addresses of the second memory area, and establishing an address corresponding table to record update information corresponding to the storage addresses for storing the update data. The system recovery method further includes erasing the update information from the address corresponding table when the storage device is powered off and re-coupled to the host system. Thereby, the system recovery method can instantly recover system settings. | 09-22-2011 |
20110231622 | STORAGE APPARATUS AND STORAGE SYSTEM - A storage apparatus includes: a memory allowing an operation to be carried out in order to additionally write new write data into a storage area already used for storing previous write data so as to store the new data in the storage area along with the previous write data; an input/output section configured to receive write data in a write access; and a control section configured to write the write data into the memory on the basis of the write access, wherein, in internal processing based on the write access, the control section carries out an additional-write operation for a storage area already used for storing the previous write data in the internal processing. | 09-22-2011 |
20110271066 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD - The present invention comprises a CHA | 11-03-2011 |
20110296120 | VIRTUAL BUFFER INTERFACE METHODS AND APPARATUSES FOR USE IN WIRELESS DEVICES - Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a virtual buffer interface capability between a plurality of processes/engines and a memory pool. | 12-01-2011 |
20110296121 | DATA WRITING METHOD AND COMPUTER SYSTEM - A data writing method for a storage device includes utilizing the storage device to transmit identification information according to a data writing request from a processing unit, utilizing the processing unit to transmit data writing information corresponding to the identification information according to the identification information, and utilizing the storage device to perform a data writing process according to the data writing information. | 12-01-2011 |
20110302378 | Method for implementation of memory management - A method for implementation of memory management on a read/write memory of a data processing device, in which a multiplicity of tasks (T | 12-08-2011 |
20110302379 | MEMORY DEVICE - There is provided a memory device capable of stably storing recorded data over a long term of several decades or longer and capable of reliably reading stored data. A first circuit | 12-08-2011 |
20120011335 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 01-12-2012 |
20120089793 | Memory Subsystem for Counter-Based and Other Applications - A memory device and related techniques are provided to modify data stored in the memory device without the need to send the data to an external device. A command is received at the memory device to modify data stored at a memory location in a memory array of the memory device. The command includes a value to be used for modifying the data. The memory device reads data from the memory location. The data read from the memory location is modified with modify circuit in the memory device based on the value obtained form the command to produce results data. The results data produced by the modify circuit is written back to the memory location. Since the memory device does not need to send the data read from the memory array off-chip to another device, referred to herein as a host device, to update the data, the input/output bandwidth of the bandwidth is substantially reduced, allowing for lower power memory device operation and reduced latency. | 04-12-2012 |
20120102278 | METHOD FOR PERSONALISING AN ELECTRONIC DEVICE, ASSOCIATED DATA PROCESSING METHOD AND DEVICE - The invention relates to any electronic device such as a chip card, a passport, a dongle or any other object requiring personalization of the content of a memory. More precisely, the invention provides for a method for processing a data item of a container stored in a memory, said method being implemented by the electronic device by utilizing in particular a table of identifiers. The invention furthermore provides for a prior step for associating a data identifier with a data item of a container and creating said table of identifiers. | 04-26-2012 |
20120144134 | NONVOLATILE SEMICONDUCTOR MEMORY AND STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor memory includes two memory planes in a chip, a I/O circuit in the chip, the I/O circuit shared by the two memory planes, and a control circuit in the chip, the control circuit controlling a write operation, a verify operation and a read operation to the two memory planes independently. Each of the two memory planes comprises a memory cell array and a data register stored write data temporarily. The control circuit configured to transfer the write data to the data registers in the two memory planes in parallel to execute the write and verify operations to every memory plane one by one in a mirroring write mode, and transfer the write data to the data register in one of the two memory planes to execute the write and verify operations in a normal write mode. | 06-07-2012 |
20120221809 | STORAGE APPARATUS AND DATA PROCESSING METHOD OF THE SAME - Comprises a memory control unit which transmits and receives data to and from respective interface control units in accordance with access requests and also controls access to the memory and a buffer which temporarily stores data smaller than 64 B, wherein the memory control unit, during access to the memory, if the processing data to be processed is 64 B, accesses the memory by using the processing data or, if the processing data is data smaller than 64 B, stores the data smaller than 64 B in the buffer, subsequently, if the address of the new processing data which became the processing data is sequential to the address of the data smaller than 64 B stored in the buffer, combines the new processing data and the data of the buffer and, on condition that the combined processing data is 64 B data, writes the combined processing data in the memory. | 08-30-2012 |
20120254562 | MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING - A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload. | 10-04-2012 |
20120254563 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 10-04-2012 |
20120265953 | MEMORY MANAGEMENT DEVICE, MEMORY MANAGEMENT METHOD, AND CONTROL PROGRAM - When a page on a random access memory (RAM) having a value matching a page on a read only memory (ROM) is detected, a memory management section of a memory manager updates a conversion table so that the page on the ROM having the matching value is referred to, and discards the detected page on the RAM. The present technology is applicable to, for example, a built-in device. | 10-18-2012 |
20120278564 | SECURE ERASURE OF DATA FROM A NON-VOLATILE MEMORY - Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained. | 11-01-2012 |
20120311276 | METHOD FOR CONTROLLING OPERATION OF A MEMORY, CORRESPONDING SYSTEM, AND COMPUTER PROGRAM PRODUCT - The operation of a FIFO buffer memory includes writing the data at input to the memory in a single write location, and making the single write location available for writing an input datum with a shift of the datum written in the single write location to another location of the memory. At each operation of writing of an input datum in the single write location, there is scheduled shifting of the datum written therein to another location, without waiting for a new write request, thus eliminating the combinational constraint between the two operations. | 12-06-2012 |
20120324179 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 12-20-2012 |
20120324180 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 12-20-2012 |
20130046941 | WRITE CIRCUIT, READ CIRCUIT, MEMORY BUFFER AND MEMORY MODULE - The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer. Advantages of the present invention lie in that: data can be transmitted with a memory controller in a low power consumption manner, and the data transmitted based on conversion control data can be read out of or written into a DDR4 memory chip. | 02-21-2013 |
20130054905 | CONCURRENT MEMORY OPERATIONS - Subject matter disclosed herein relates to performing concurrent memory operations. | 02-28-2013 |
20130061011 | METHOD OF MANAGING MEMORY AND IMAGE FORMING APPARATUS TO PERFORM THE SAME - A method of managing memory, the method including extracting location information of erasure data in which file allocation information has been deleted, and performing an overwrite job on the erasure data in a memory, based on the extracted location information. | 03-07-2013 |
20130067178 | MEMORY DUMP WITH EXPANDED DATA AND USER PRIVACY PROTECTION - A system and method for generating a triage dump of useful memory data from a computer that encounters an error while executing one or more software programs. The computer system may identify data values within the triage dump that are characteristic of personal data. To protect the privacy of the software user the personal data may be poisoned by overwriting the data values with overwrite values. The overwrite values used to poison the data values may be predetermined, based on the data values themselves, or chosen at random. The triage dump may be sent to an external server to associated with the developer of the one or more software programs for analysis. When overwrite values are dynamically selected, the specific overwrite values used may be sent to the server in connection with a triage dump. | 03-14-2013 |
20130166857 | STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A write DMA includes a write unit, a read unit and a parity generation unit. The read unit reads parity data from one of two NAND flashes storing the parity data therein. The parity generation unit generates parity data based on the read parity data and a plurality of stripes obtained by dividing user data. The write unit writes a stripe into any of a plurality of NAND flashes storing stripes therein, and writes generated parity data into the other NAND flash from which parity data is not read. | 06-27-2013 |
20130246721 | CONTROLLER, DATA STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit. The controller also includes a read control unit configured to a control that reads a piece of cluster data from the storage medium using an acquired physical address, and decompresses the read piece of cluster data. | 09-19-2013 |
20130254498 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD THEREFOR - A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed. | 09-26-2013 |
20130262795 | INFORMATION STORAGE DEVICE AND METHOD - An information storage device includes a storage unit to which a storage region is assigned, a first management information storage unit that stores address information indicating an address range of the storage region in association with identification information identifying the storage region, and a processor that executes a procedure that includes acquiring the address information corresponding to the identification information from the first management information storage unit and accesses the storage region corresponding to the address information and rewriting the identification information stored in the first management information storage unit. | 10-03-2013 |
20130282993 | STORAGE CONTROL DEVICE, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite. | 10-24-2013 |
20130290654 | DATA WRITING CONTROL DEVICE, DATA WRITING CONTROL METHOD, AND INFORMATION PROCESSING DEVICE - A data writing control device includes: a determination unit that determines whether a request from a requestor is a partial-write request for data and the partial-write is continuously performed to the same address; a transmission unit that, when the request from the requestor is the partial-write request for data and the partial-write is performed to an address different from an address of the previous partial-write, transmits a read request for data to the requestor; and a hold unit that holds write data included in the partial-write request and data indicating a rewritten location of the write data until read data corresponding to the read request for the data is received. | 10-31-2013 |
20130326165 | IMPLEMENTATION OF INSTRUCTION FOR DIRECT MEMORY COPY - Embodiments of the present invention relate to a method and system for performing a memory copy. In one embodiment of the present invention, there is provided a method for performing memory copy, including: decoding a memory copy instruction into at least one microcode in response to receipt of the memory copy instruction, transforming the at least one microcode into a ReadWrite Command for each of the at least one microcode, and notifying a memory controller to execute the ReadWrite Command, wherein the ReadWrite Command is executed by the memory controller and comprises at least a physical source address, a physical destination address and a ReadWrite length that are associated with the ReadWrite Command. In another embodiment of the present invention, there is provided a system for performing a memory copy. | 12-05-2013 |
20130339637 | MEMORY CONTROL APPARATUS, MEMORY APPARATUS, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD FOR USE THEREWITH - There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result. | 12-19-2013 |
20140006730 | MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY MEMORY DEVICES | 01-02-2014 |
20140006731 | FILTER APPLIANCE FOR OBJECT-BASED STORAGE SYSTEM | 01-02-2014 |
20140025906 | Device Controller for a Memory Device - The invention provides a method for controlling writing of data to a data storage card having a device controller and a storage medium. Particularly, the device controller receives a meta data synchronization disable command and in response, enters a first mode. In the first mode, the device controller does not synchronize meta data related to a data write request to write the data to the storage medium, leaving corresponding unsynchronized meta data. The device controller receives a data write request to write the data, and in response, effects the data write request such that the data is written to the storage medium. However, the meta data related to the data write request is not synchronized to the storage medium. Other aspects provide a corresponding device controller and software/firmware. | 01-23-2014 |
20140068203 | MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF - A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address. | 03-06-2014 |
20140075135 | SEMICONDUCTOR MEMORY DEVICE WITH OPERATION FUNCTIONS - A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode. | 03-13-2014 |
20140108749 | STORAGE SYSTEM EFFECTIVELY MANAGING A CAPACITY FOR REMOTE COPY - In one of the storage control apparatuses in the remote copy system which performs asynchronous remote copy between the storage control apparatuses, virtual logical volumes complying with Thin Provisioning are adopted as journal volumes to which journals are written. The controller in the one of the storage control apparatuses assigns a smaller actual area based on the storage apparatus than in case of assignment to the entire area of the journal volume, and adds a journal to the assigned actual area. If a new journal cannot be added, the controller performs wraparound, that is, overwrites the oldest journal in the assigned actual area by the new journal. | 04-17-2014 |
20140122814 | APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES - Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received. | 05-01-2014 |
20140129785 | Security Erase of a Delete File and of Sectors Not Currently Assigned to a File - Secure erase of files and unallocated sectors on storage media such that any previous data is non-recoverable. The database contains sets of data patterns used to overwrite the data on different physical media. The software programs manage the overwriting process automatically when a file has been deleted. When de-allocated sectors in the file system are pruned from a file or escaped the file deletion process also finds them. Data will never be found on deleted sectors or on pruned sectors is overwritten. | 05-08-2014 |
20140189265 | ATOMIC TIME COUNTER SYNCHRONIZATION - Methods, integrated circuit devices, and fabrication processes relating to synchronization of master and local timestamp counters (TSCs) are described. One method includes sending, to a memory bus, in response to an event that desynchronizes a master and a local TSC, a bus-lock command to perform atomic reading from a first memory location and atomic writing to a second memory location; reading a master timestamp from the master TSC via the first memory location; writing a local timestamp to the local TSC via the second memory location, to synchronize the local TSC with the master TSC; and sending, to the memory bus, a bus-unlock command; wherein the master TSC is memory mapped to the first memory location and the local TSC is memory mapped to the second memory location. | 07-03-2014 |
20140189266 | EFFICIENT READ AND WRITE OPERATIONS - Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks. | 07-03-2014 |
20140201476 | EVENT-BASED EXECUTION BUFFER MANAGEMENT - Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed. | 07-17-2014 |
20140237198 | REDUCING EFFECTIVE CYCLE TIME IN ACCESSING MEMORY MODULES - A method reduces a cycle time of an individual memory module to an effective cycle time shorter than the cycle time using a plurality of memory modules having a circular sequence. The method includes initiating a set of read operations on different memory modules of the plurality of memory modules in the circular sequence from a first read operation initiated on a first module of the plurality of memory modules to a last read operation initiated on the second module. After initiating each read operation of the set of read operations on a particular memory module of the plurality of memory modules and prior to initiating a next read operation in the set of read operations, the method initiates a set of write operations to write a same value to all of the plurality of memory modules in the circular sequence beginning one memory module after the particular memory module. | 08-21-2014 |
20140258648 | OVERWRITING PART OF COMPRESSED DATA WITHOUT DECOMPRESSING ON-DISK COMPRESSED DATA - Overwriting part of compressed data without decompressing on-disk compressed data is includes by receiving a write request for a block of data in a compression group from a client, wherein the compression group comprises a group of data blocks that is compressed, wherein the block of data is uncompressed. The storage server partially overwrites the compression group, wherein the compression group remains compressed while the partial overwriting is performed. The storage server determines whether the partially overwritten compression group including the uncompressed block of data should be compressed. The storage server defers compression of the partially overwritten compression group if the partially overwritten compression group should not be compressed. The storage server compresses the partially overwritten compression group if the partially overwritten compression group should be compressed. | 09-11-2014 |
20150039844 | MEMORY DEVICE IMPLEMENTING REDUCED ECC OVERHEAD - A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output. | 02-05-2015 |
20150074358 | HIGH PERFORMANCE SYSTEM PROVIDING SELECTIVE MERGING OF DATAFRAME SEGMENTS IN HARDWARE - A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary. | 03-12-2015 |
20150081988 | METHOD AND SYSTEM FOR PARALLEL PROGRAM EXECUTION - A method for executing a program in parallel includes creating a program replica, which includes a write operation on and an identifier of an object and is a copy of the program, for a thread. The identifier specifies whether the object is thread-local. The method includes modifying the write operation based on a speculation that the write operation uses only thread-local objects. The write operation executes in a transaction of the thread. The method includes determining, while executing the program replica and using the identifier, that the object used by the write operation is not thread-local, de-optimizing the write operation by adding instrumentation to implement a software transactional memory (STM) system for the write operation to obtain a de-optimized write operation, and performing the de-optimized write operation on the object to obtain a result and store the result in a redo log. | 03-19-2015 |
20150364205 | INTER-CELL INTERFERENCE ESTIMATION BASED ON A PATTERN DEPENDENT HISTOGRAM - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a plurality of reads on a victim cell. The controller may be configured to store measured victim information from the plurality of reads on the victim cell. The controller may be configured to perform one or more reads on a plurality of aggressor cells. The controller may be configured to store measured aggressor information from the one or more reads on the plurality of aggressor cells. The controller may be configured to generate inter-cell interference parameters based on the measured victim information and the measured aggressor information. The controller may be configured to mitigate inter-cell interference based on the inter-cell interference parameters. | 12-17-2015 |
20160004441 | ACCESS CONTROL METHOD FOR ACCESSING DATA IN STORAGE AND DISK DRIVE - An access control method includes: in response to a first access instruction that instructs accessing first data, reading the first data and second data from a storage and deleting the first data and the second data from the storage, the first data being read from a first storage area, the second data being read from a second storage area that is physically adjacent to the first storage area and is not an empty area; and in response to a second access instruction that instructs writing third data to the storage, writing the third data to a third storage area that is adjacent to a storage area located in a physically rearmost position among storage areas in which data has been stored in the storage. | 01-07-2016 |
20160034202 | MULTI-TIERED STORAGE DEVICE SYSTEM AND METHOD THEREOF - A system for controlling a multi-tiered storage device (MTSD) includes a first group of storage devices and a second group of storage devices, wherein each storage device of the first group of storage devices has a higher endurance than each storage device of a second group of storage devices of the MTSD. A block of data is received by a controller of the MTSD, and is written to a storage device of the first group of storage devices. Upon determination that the block of data has been written to infrequently, the block of data is written to a storage device of the second group of storage devices. The block of data may then be erased from the storage device of the first group of storage devices. In some embodiments, a storage device from the first group is associated with the second group, upon determination that the storage has degraded. | 02-04-2016 |
20160054929 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an update request reception unit receives a data update request to update data stored in a storage. A read request unit makes a read request to read data from the storage. A data reception unit receives the data from the storage. An update value calculator calculates an update value of the received data. A write request unit makes a write request to write the calculated update value into the storage. A data processing execution unit executes reading and writing on the storage. A history processing unit generates a history of the reading and deletes a history of reading corresponding to the writing. An update information estimator estimates, from the generated history, update information indicating how the data is to be updated. A data update unit updates the data read according to the estimated update information and output new updated data to the data reception unit. | 02-25-2016 |
20160124850 | REWRITING SYMBOL ADDRESS INITIALIZATION SEQUENCES - A system includes a memory to store a linker and one or modules, and a processor, communicatively coupled to the memory. The computer system is configured to recognize a first symbol address initialization sequence in a module. The system determines whether the first symbol address initialization sequence is a candidate for replacement, determines whether to replace the first symbol address initialization sequence with a second symbol address initialization sequence, and replaces the first symbol address initialization sequence with the second symbol address instruction sequence when it is determined to replace the first symbol address initialization sequence with the second symbol address initialization sequence. | 05-05-2016 |
20160162192 | OPTIMIZING ACCESS TO UNIVERSAL INTEGRATED CIRCUIT CARD (UICC) FILES IN A USER EQUIPMENT (UE) - A method and a User Equipment (UE) are provided for optimizing access to Universal Integrated Circuit Card (UICC) files in the UE. The method includes storing, by the UE, at least one File Control Parameter (FCP) file corresponding to a plurality of Elementary Files (EFs); and sending, by the UE, a command directly to the UICC, based on the at least one FCP file. The command includes one of a READ command and an UPDATE command. | 06-09-2016 |
20160170640 | SYSTEM AND METHOD FOR FAST MODIFICATION OF REGISTER CONTENT | 06-16-2016 |
20160179434 | STORAGE DEVICE AND METHOD FOR PERFORMING CONVOLUTION OPERATIONS | 06-23-2016 |